CN212034090U

CN212034090U - Automatic gain adjusting circuit applied to burst trans-impedance amplifier

Info

Publication number: CN212034090U
Application number: CN202020937142.1U
Authority: CN
Inventors: 张�浩; 邓青; 施家鹏
Original assignee: Nanjing Magnichip Microelectronics Co ltd
Current assignee: Nanjing Magnichip Microelectronics Co ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-11-27
Anticipated expiration: 2030-05-28

Abstract

The technology discloses an automatic gain adjusting circuit applied to a burst trans-impedance amplifier, which comprises an automatic gain adjusting loop, a threshold generating circuit and a control voltage generating circuit, wherein the threshold generating circuit is connected with the control voltage generating circuit; the automatic gain adjusting loop comprises a core amplifier, a working current adjusting circuit, a parallel transimpedance adjusting circuit and a parallel resistance adjusting circuit; the working current adjusting circuit, the parallel transimpedance adjusting circuit and the parallel resistance adjusting circuit are all connected with the core amplifier, and the working current adjusting circuit, the parallel transimpedance adjusting circuit and the parallel resistance adjusting circuit are all connected with the control voltage generating circuit. The automatic gain adjusting circuit of the technology can ensure that the loop of the trans-impedance amplifier is stable under the large dynamic range of input signals, and devices on a transmission link do not enter an abnormal working state, so that the safety of a chip and the signal transmission quality are obviously improved.

Description

Automatic gain adjusting circuit applied to burst trans-impedance amplifier

Technical Field

The technology relates to the technical field of microelectronics, in particular to an automatic gain adjusting circuit applied to a burst trans-impedance amplifier.

Background

With the rapid development of broadband access markets in the global scope, domestic hundred-mega broadband gradually becomes standard distribution, and the existing PON (passive optical network) technical standard faces new upgrading requirements in the aspects of bandwidth requirements, service supporting capability, performance improvement of access node equipment and supporting equipment, and the like. The PON adopts TDM broadcast mode at the downlink and time division multiple access mode at the uplink. This operation mode also determines that the receiving and transmitting circuit (including the transmitter at the OLT end and the receiver at the ONU end) in the downstream direction of the PON operates in the continuous mode; and the uplink transceiver circuit (including the ONU-side transmitter and the OLT-side receiver) operates in burst mode.

The trans-impedance amplifier is used for a receiving module of an optical communication system and completes the function of amplifying weak current generated by the photodiode into a voltage signal. The two most important parameters of a transimpedance amplifier are the sensitivity current and the overload current. The sensitivity current reflects the minimum signal processing capability of the trans-impedance amplifier and has close relation with the noise and the signal bandwidth of the trans-impedance amplifier; the overload current reflects the maximum signal processing capability of the transimpedance amplifier. The dynamic range of the transimpedance amplifier is formed by the two components, and the larger the dynamic range is, the stronger the capability of the transimpedance amplifier for identifying and processing optical signals is. AGC (automatic gain control) technology is usually used to achieve a large dynamic range, i.e. to reduce the transimpedance when a large signal is input to avoid distortion of the output signal. For a commonly used common-source amplifier, the dominant pole is determined by the trans-resistance Rf and the input capacitance CT, and the secondary pole is determined by the load resistance of the common-source amplifier and the node capacitance thereof. When a large signal is input, the AGC circuit works, the trans-resistance is reduced, the right shift of the dominant pole is increased, the phase margin of the loop is reduced, the loop is unstable, and the quality of an output eye diagram is poor.

Disclosure of Invention

The present invention provides an automatic gain adjusting circuit applied to a burst transimpedance amplifier, which can ensure that a transimpedance amplifier loop is stable under a large dynamic range of an input signal, and devices on a transmission link do not enter an abnormal operating state, so that the security of a chip and the signal transmission quality are significantly improved.

In order to achieve the technical purpose, the technical scheme adopted by the technology is as follows:

an automatic gain adjusting circuit applied to a burst transimpedance amplifier comprises an automatic gain adjusting loop, a threshold generating circuit and a control voltage generating circuit, wherein the threshold generating circuit is connected with the control voltage generating circuit;

the automatic gain adjusting loop comprises a core amplifier, a working current adjusting circuit, a parallel transimpedance adjusting circuit and a parallel resistance adjusting circuit;

the core amplifier comprises a triode Q2, a triode Q3, a triode Q4, a resistor R1, a resistor R3, a resistor R4 and a constant current source I1, wherein one end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is simultaneously connected with a collector of a triode Q2 and an emitter of a triode Q3, an emitter of the triode Q2 is connected with a ground wire, one end of the resistor R3 is connected with the power supply, the other end of the resistor R3 is simultaneously connected with a collector of a triode Q3 and a base of a triode Q4, a collector of the triode Q4 is connected with the power supply, the emitter is connected with the ground wire through a constant current source I1, one end of the resistor R4 is connected with the base of the;

the input end of the working current regulating circuit is connected with the control voltage generating circuit, the output end of the working current regulating circuit is connected with the collector of the triode Q2, and the working current regulating circuit is used for completing the regulation of the working current of the triode Q2 under the control of the voltage VF1 output by the control voltage generating circuit;

the input end of the parallel transimpedance regulating circuit is connected with the control voltage generating circuit, the output end of the parallel transimpedance regulating circuit is connected with the resistor R4, and the parallel transimpedance regulating circuit is used for completing parallel transimpedance regulation of the resistor R4 under the control of the voltage VF output by the control voltage generating circuit;

the input end of the parallel resistance value adjusting circuit is connected with the control voltage generating circuit, the output end of the parallel resistance value adjusting circuit is connected with the resistor R3, and the parallel resistance value adjusting circuit is used for completing the parallel resistance value adjustment of the resistor R3 under the control of the voltage VL output by the control voltage generating circuit.

As a further improvement of the present technology, the operating current regulating circuit includes a transistor Q1 and a resistor R2, the base of the transistor Q1 is connected to the control voltage generating circuit, the base of the transistor Q1 is used for receiving the voltage VF output by the control voltage generating circuit, the collector of the transistor Q1 is connected to the collector of the transistor Q2, and the emitter of the transistor Q1 is connected to the ground through the resistor R2.

As a further improvement of the present technology, the parallel transimpedance regulating circuit includes a MOS transistor M1, a gate of the MOS transistor M1 is connected to the control voltage generating circuit, a gate of the MOS transistor M1 is configured to receive the voltage VF output by the control voltage generating circuit, a source of the MOS transistor M1 is connected to one end of a resistor R4, and a drain of the MOS transistor M1 is connected to the other end of the resistor R4.

As a further improvement of the present technology, the parallel resistance value adjusting circuit includes a MOS transistor M2, a resistor R5, a transistor Q5, a transistor Q6, a resistor R6, and a constant current source I2, a gate of the MOS transistor M2 is connected to the control voltage generating circuit, a gate of the MOS transistor M2 is used for receiving the voltage VL output by the control voltage generating circuit, a source of the MOS transistor M2 is connected to the resistor R3, a drain of the MOS transistor M2 is connected to a collector and a base of the transistor Q5 through the resistor R5, the constant current source I2 is connected to a collector of the transistor Q5, an emitter of the transistor Q5 is connected to a collector of the transistor Q6 and one end of the resistor R6, the other end of the resistor R6 is connected to a base of the transistor Q6, and a collector of the transistor Q6 is connected to.

As a further improvement of the present technology, the threshold generating circuit includes a current mirror bias, a MOS transistor M3, a MOS transistor M4, a resistor R7, a resistor Rth, a capacitor C1, a transistor Q7, a transistor Q8, a resistor R8, a resistor R9, and a constant current source Itail; the current mirror bias comprises an MOS tube M5 and an MOS tube M6, the grids of the MOS tube M5 and the MOS tube M6 are both connected with a bias source, the source of the MOS tube M5 is connected with a power supply, the drain of the MOS tube M5 is simultaneously connected with a resistor Rth and the base of a triode Q7, the other end of the resistor Rth is connected with the source of the MOS tube M3, the drain of the MOS tube M3 is connected with a ground wire, the source of the MOS tube M6 is connected with the power supply, the drain of the MOS tube M6 is simultaneously connected with the source of the MOS tube M4 and the base of the triode Q8, one end of the resistor R7 is simultaneously connected with the grid of the MOS tube M4 and a capacitor C1, the other end of the capacitor C1 is connected with the ground wire with the drain of the MOS tube M4, the collector of the triode Q7 is connected with the power supply, the emitter of the triode Q8 is sequentially connected with the ground wire through a resistor R8 and an Itail, and a;

the gate of the MOS transistor M3 is used for inputting the output voltage Vcm of the burst buffer, the other end of the resistor R7 is used for inputting the output voltage Vref of the replica circuit of the core amplifier, and the collector of the triode Q8 is connected to the control voltage generating circuit.

As a further improvement of the technology, the control voltage generating circuit comprises a current mirror bias, a constant current source I3, a resistor R10, a triode Q13, a MOS tube M7, a triode Q12, a constant current source I6, a constant current source I4, a triode Q14, a resistor R11_、A cascode current mirror, a constant current source I5, a transistor Q15, a resistor R12 and a transistor Q16, wherein the current mirror bias comprises a transistor Q9, a transistor Q10 and a transistor Q11, bases of the transistor Q9, the transistor Q10 and the transistor Q11 are connected with each other, emitters of the transistor Q9, the transistor Q10 and the transistor Q11 are all connected with a power supply, a collector of the transistor Q9 is connected with a collector of the transistor Q8 in the threshold generation circuit, a collector of the transistor Q10 is simultaneously connected with the constant current source I10, one end of the resistor R10 and a gate of the MOS transistor M10, the other end of the resistor R10 is simultaneously connected with a collector and a base of the transistor Q10, an emitter of the transistor Q10 is connected with a ground, a base of the transistor Q10 and a collector of the transistor Q10 are both connected with a power supply, an emitter of the transistor Q10 is connected with a drain of the MOS transistor M10, constant current source I4 is connected with triode Q14's collecting electrode and cascade current mirror simultaneously, triode Q14's projecting pole passes through resistance R11 and connects ground wire, cascade current mirror simultaneously with triode Q15's transmissionThe collector of the triode Q11 is simultaneously connected with the constant current source I5, the collector of the triode Q15 and the base of the triode Q15, the other end of the resistor R12 is simultaneously connected with the collector and the base of the triode Q16, and the emitter of the triode Q16 is connected with the ground wire;

the collector of the triode Q10 is used for outputting the voltage VF, the source of the MOS transistor M7 is used for outputting the voltage VF1, and the collector of the triode Q11 is used for outputting the voltage VL.

The beneficial effect of this technique does: the automatic gain adjusting circuit of the technology is suitable for the trans-impedance amplifier, and is a protection point of the technology in a mode of detecting signal power and a mode of controlling a negative feedback loop of the trans-impedance amplifier under full power to enable the negative feedback loop to be stable and enable working points of all devices to be normal. The technology provides a circuit for detecting the input signal power of a transimpedance amplifier and automatically adjusting a transimpedance feedback loop, which can ensure that the transimpedance amplifier loop is stable under the large dynamic range of input signals and the quality of an output eye diagram is good. And devices on the transmission link do not enter an abnormal working state, so that the safety of the chip and the signal transmission quality are obviously improved.

Drawings

Fig. 1 is a schematic diagram of a transimpedance amplifier circuit applied to a burst PON system.

Fig. 2 is a schematic diagram of an automatic gain adjustment loop in an automatic gain adjustment circuit applied to a burst transimpedance amplifier.

Fig. 3 is a schematic diagram of a threshold generation circuit in an automatic gain adjustment circuit applied to a burst transimpedance amplifier.

Fig. 4 is a schematic diagram of a control voltage generation circuit applied to an automatic gain adjustment circuit of a burst transimpedance amplifier.

Fig. 5 is a gain phase plot without an AGC loop.

Fig. 6 is a gain phase curve with the present AGC loop.

Detailed Description

Embodiments of the present technique are further described below with reference to FIGS. 1-6:

the embodiment provides an automatic gain adjusting circuit applied to a burst transimpedance amplifier, which comprises an automatic gain adjusting loop, a threshold generating circuit and a control voltage generating circuit, wherein the threshold generating circuit is connected with the control voltage generating circuit, and the control voltage generating circuit is connected with the automatic gain adjusting loop.

The block diagram of the burst trans-impedance amplifier is shown in fig. 1, and the main link consists of a core amplifier Amp, a burst buffer (burst buffer), a single-ended differential-to-differential amplifier (S2D), an output buffer (buffer), Automatic Gain Control (AGC), and differential mode offset cancellation (DOC). The current signal is input from an IN end, converted into a single-ended voltage signal through a core trans-impedance amplifier (namely, a core amplifier Amp), transmitted to a burst buffer, processed and output to obtain a signal Vout with one end boosted by a direct current voltage and the other end serving as an average value of the signal voltage and serving as an input common mode level Vcm of the single-ended to differential module. The S2D module completes the operation of converting the single-ended signal voltage into differential voltage, outputs a buffer to transmit the differential signal to the next chip, and ensures impedance matching during transmission. The replica circuit (Dummy) of the core amplifier in fig. 1 is used to generate the voltage reference point Vref required for Automatic Gain Control (AGC). The output end of the differential mode offset elimination (DOC) is used for connecting the stage of an output buffer (buffer). The Automatic Gain Control (AGC) module inputs the voltage Vcm of the burst buffer and the voltage Vref of the Dummy Amp, and converts the difference into loop control voltages VL, VF 1.

An automatic gain adjustment loop in the transimpedance amplifier core circuit Amp is shown in fig. 2 and includes a core amplifier, a working current adjustment circuit, a parallel transimpedance adjustment circuit, and a parallel resistance adjustment circuit.

The core amplifier comprises a triode Q2, a triode Q3, a triode Q4, a resistor R1, a resistor R3, a resistor R4 and a constant current source I1, one end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is simultaneously connected with a collector of the triode Q2 and an emitter of the triode Q3, the emitter of the triode Q2 is connected with a ground wire, one end of the resistor R3 is connected with the power supply, the other end of the resistor R3 is simultaneously connected with a collector of the triode Q3 and a base of the triode Q4, the collector of the triode Q4 is connected with the power supply, the emitter is connected with the ground wire through the constant current source I1, one end of the resistor R4 is connected with the base of the triode. In fig. 2, VIN is the input terminal of the core amplifier, the point between Q4 and I1 is the output terminal of the core amplifier, and the base vb of the transistor Q3 is connected to a fixed potential.

The input end of the working current regulating circuit is connected with the control voltage generating circuit, the output end of the working current regulating circuit is connected with the collector of the triode Q2, and the working current regulating circuit is used for completing the regulation of the working current of the triode Q2 under the control of the voltage VF1 output by the control voltage generating circuit; the specific circuit comprises a triode Q1 and a resistor R2, wherein the base electrode of the triode Q1 is connected with the control voltage generating circuit, the base electrode of the triode Q1 is used for receiving the voltage VF output by the control voltage generating circuit, the collector electrode of the triode Q1 is connected with the collector electrode of the triode Q2, and the emitter electrode of the triode Q1 is connected with the ground wire through the resistor R2.

The input end of the parallel transimpedance regulating circuit is connected with the control voltage generating circuit, the output end of the parallel transimpedance regulating circuit is connected with the resistor R4, and the parallel transimpedance regulating circuit is used for completing parallel transimpedance regulation of the resistor R4 under the control of the voltage VF output by the control voltage generating circuit. The specific circuit comprises a MOS tube M1, the grid electrode of the MOS tube M1 is connected with the control voltage generating circuit, the grid electrode of the MOS tube M1 is used for receiving the voltage VF output by the control voltage generating circuit, the source electrode of the MOS tube M1 is connected with one end of a resistor R4, and the drain electrode of the MOS tube M1 is connected with the other end of a resistor R4.

The input end of the parallel resistance value adjusting circuit is connected with the control voltage generating circuit, the output end of the parallel resistance value adjusting circuit is connected with the resistor R3, and the parallel resistance value adjusting circuit is used for completing parallel resistance value adjustment of the resistor R3 under the control of the voltage VL output by the control voltage generating circuit. The specific circuit comprises an MOS tube M2, a resistor R5, a triode Q5, a triode Q6, a resistor R6 and a constant current source I2, wherein the grid of the MOS tube M2 is connected with a control voltage generating circuit, the grid of the MOS tube M2 is used for receiving the voltage VL output by the control voltage generating circuit, the source of the MOS tube M2 is connected with a resistor R3, the drain of the MOS tube M2 is simultaneously connected with the collector and the base of the triode Q5 through a resistor R5, the constant current source I2 is connected with the collector of the triode Q5, the emitter of the triode Q5 is simultaneously connected with the collector of the triode Q6 and one end of the resistor R6, the other end of the resistor R6 is connected with the base of the triode Q6, and the collector of the triode Q6 is.

As shown in fig. 2, devices Q2, Q3, Q4, R1, R3, R4 and I1 form a core transimpedance amplifier, Q1 and R2 complete adjustment of operating current of Q2 under control of voltage VF1, and M1 completes adjustment of parallel transimpedance of R4, M2, R5, Q5, Q6, R6 and I2 under control of voltage VF to complete adjustment of parallel resistance of load R3. The stability of a negative feedback loop of the trans-impedance amplifier when the dynamic range of an input current signal is large is ensured, and the direct-current working point of each device is in a linear state.

Fig. 3 is a threshold generating circuit of the automatic gain adjusting module, which includes a current mirror bias, a MOS transistor M3, a MOS transistor M4, a resistor R7, a resistor Rth, a capacitor C1, a transistor Q7, a transistor Q8, a resistor R8, a resistor R9, and a constant current source Itail; the current mirror bias comprises a MOS transistor M5 and a MOS transistor M6, the gates of the MOS transistor M5 and the MOS transistor M6 are both connected with a bias source, the source electrode of the MOS tube M5 is connected with a power supply, the drain electrode of the MOS tube M5 is simultaneously connected with a resistor Rth and the base electrode of a triode Q7, the other end of the resistor Rth is connected with the source electrode of a MOS tube M3, the drain electrode of the MOS tube M3 is connected with the ground wire, the source electrode of the MOS tube M6 is connected with a power supply, the drain electrode of the MOS tube M6 is simultaneously connected with the source electrode of the MOS tube M4 and the base electrode of the triode Q8, one end of the resistor R7 is simultaneously connected with the grid of the MOS tube M4 and the capacitor C1, the other end of the capacitor C1 and the drain of the MOS tube M4 are both connected with the ground wire, the collector of the triode Q7 is connected with a power supply, the emitter is connected with the ground wire through a resistor R8 and a constant current source Itail in turn, the emitter of the transistor Q8 is connected to the ground line through the resistor R9 and the constant current source Itail.

As shown in fig. 3, where Vcm is the average value of the signal processed by burst buffer in fig. 1, Vref is the output of the replicated trans-impedance core amplifier, M5 and M6 are current mirror biases (Vbias controls the current value thereof, the voltage is provided by the bias source of the circuit), MOS transistors M3 and M4 complete level conversion, the voltage difference across the Rth resistor is the threshold of the AGC loop, and the amplifier composed of Q7, Q8, R8, R9, Itail completes the conversion of the voltage difference of V1 and V2 to the current iagc. When the Vcm voltage is less than Vref minus the threshold voltage, the iagc current becomes large.

Fig. 4 is a circuit for generating three control voltages VF, VF1, VL in the agc loop of fig. 2, that is, a control voltage generating circuit in the agc module, where the control voltage generating circuit includes a current mirror bias, a constant current source I3, a resistor R10, a transistor Q13, a MOS transistor M7, a transistor Q12, a constant current source I6, a constant current source I4, a transistor Q14, and a resistor R11_、A cascode current mirror, a constant current source I5, a transistor Q15, a resistor R12 and a transistor Q16, wherein the current mirror bias comprises a transistor Q9, a transistor Q10 and a transistor Q11, bases of the transistor Q9, the transistor Q10 and the transistor Q11 are connected with each other, emitters of the transistor Q9, the transistor Q10 and the transistor Q11 are all connected with a power supply, a collector of the transistor Q9 is connected with a collector of the transistor Q8 in the threshold generation circuit, a collector of the transistor Q10 is simultaneously connected with the constant current source I10, one end of the resistor R10 and a gate of the MOS transistor M10, the other end of the resistor R10 is simultaneously connected with a collector and a base of the transistor Q10, an emitter of the transistor Q10 is connected with a ground, a base of the transistor Q10 and a collector of the transistor Q10 are both connected with a power supply, an emitter of the transistor Q10 is connected with a drain of the MOS transistor M10, constant current source I4 is connected with triode Q14's collecting electrode and cascade current mirror simultaneously, triode Q14's projecting pole passes through resistance R11 and connects ground wire, cascade current mirror is connected with triode Q15's projecting pole and resistance R12 one end simultaneously, triode Q11's collecting electrode is connected with constant current source I5, triode Q15's collecting electrode and triode Q15's base simultaneously, resistance R12's the other end is connected with triode Q16's collecting electrode and base simultaneously, triode Q16's projecting pole connects ground wire.

The collector of the transistor Q10 is used for outputting the voltage VF, the source of the MOS transistor M7 is used for outputting the voltage VF1, and the collector of the transistor Q11 is used for outputting the voltage VL.

As shown in fig. 4, devices Q9, Q10, Q11 are current mirror biased (base-connected) controlled by an automatically varying current Iagc, I3, R10, Q13, and Q10 collectively generate a VF voltage; m7, Q12, I6 act as a buffer to convert VF to VF 1; the devices I4, Q14 and R11 are current generation circuits controlled by voltage VF, the difference of currents on resistors of the output I4 and R11 is output, M8, M9, M10 and M11 are cascode current mirrors, the output currents are connected to an emitter of Q15, and voltage VL is generated under the combined action of I5, Q15, R12, Q16 and Q11. The voltage difference between VF and VL is the current introduced by the base emitter electrode difference Vbe of a triode, M9 and M11, and the phase margin at a medium power point can be improved.

Fig. 5 and 6 are open-loop gain curves and phase margin curves of the transimpedance core amplifier loop before and after the AGC loop is added, and before the AGC loop proposed by the present technology is not added, the open-loop gain is consistent from a small signal input to a large signal input (in fig. 5 and 6, the solid lines are both small signal input phases, and the dotted lines are both large signal input phases), but the phase margin is reduced from 60 ° to 10 °, and the loop cannot be stabilized. After the AGC circuit of the technology is added, the open-loop gain is reduced from 30dB to 17dB from a small signal to a large signal, the phase margin is improved from 60 degrees to 72 degrees, and the stability of a trans-impedance amplifier loop in a large dynamic range is well ensured.

The technical innovation provides a circuit for detecting the input signal power of a transimpedance amplifier and automatically adjusting a transimpedance feedback loop, the circuit can ensure that the transimpedance amplifier loop is stable under the large dynamic range of input signals, devices on a transmission link do not enter an abnormal working state, and the safety of a chip and the signal transmission quality can be obviously improved.

The technical scope of the present invention includes, but is not limited to, the above embodiments, the technical scope of the present invention is defined by the claims, and any replacement, modification, and improvement that can be easily conceived by those skilled in the art are included in the technical scope of the present invention.

Claims

1. An automatic gain adjusting circuit applied to a burst trans-impedance amplifier is characterized in that: the automatic gain control circuit comprises an automatic gain control loop, a threshold value generating circuit and a control voltage generating circuit, wherein the threshold value generating circuit is connected with the control voltage generating circuit, and the control voltage generating circuit is connected with the automatic gain control loop;

2. The automatic gain adjustment circuit applied to the burst transimpedance amplifier according to claim 1, characterized in that: the working current regulating circuit comprises a triode Q1 and a resistor R2, the base electrode of the triode Q1 is connected with the control voltage generating circuit, the base electrode of the triode Q1 is used for receiving the voltage VF output by the control voltage generating circuit, the collector electrode of the triode Q1 is connected with the collector electrode of the triode Q2, and the emitter electrode of the triode Q1 is connected with the ground wire through the resistor R2.

3. The automatic gain adjustment circuit applied to the burst transimpedance amplifier according to claim 2, characterized in that: the parallel transimpedance regulating circuit comprises a MOS tube M1, the grid of the MOS tube M1 is connected with the control voltage generating circuit, the grid of the MOS tube M1 is used for receiving the voltage VF output by the control voltage generating circuit, the source of the MOS tube M1 is connected with one end of a resistor R4, and the drain of the MOS tube M1 is connected with the other end of the resistor R4.

4. The automatic gain adjustment circuit applied to the burst transimpedance amplifier according to claim 3, characterized in that: the parallel resistance value adjusting circuit comprises an MOS tube M2, a resistor R5, a triode Q5, a triode Q6, a resistor R6 and a constant current source I2, wherein the grid electrode of the MOS tube M2 is connected with a control voltage generating circuit, the grid electrode of the MOS tube M2 is used for receiving the voltage VL output by the control voltage generating circuit, the source electrode of the MOS tube M2 is connected with a resistor R3, the drain electrode of the MOS tube M2 is simultaneously connected with the collector electrode and the base electrode of the triode Q5 through a resistor R5, the constant current source I2 is connected with the collector electrode of the triode Q42, the emitter electrode of the triode Q5 is simultaneously connected with the collector electrode of the triode Q6 and one end of the resistor R6, the other end of the resistor R6 is connected with the base electrode of the triode Q6, and.

5. The automatic gain adjustment circuit applied to the burst transimpedance amplifier according to claim 4, wherein: the threshold generating circuit comprises a current mirror bias, an MOS transistor M3, an MOS transistor M4, a resistor R7, a resistor Rth, a capacitor C1, a triode Q7, a triode Q8, a resistor R8, a resistor R9 and a constant current source Itail; the current mirror bias comprises an MOS tube M5 and an MOS tube M6, the grids of the MOS tube M5 and the MOS tube M6 are both connected with a bias source, the source of the MOS tube M5 is connected with a power supply, the drain of the MOS tube M5 is simultaneously connected with a resistor Rth and the base of a triode Q7, the other end of the resistor Rth is connected with the source of the MOS tube M3, the drain of the MOS tube M3 is connected with a ground wire, the source of the MOS tube M6 is connected with the power supply, the drain of the MOS tube M6 is simultaneously connected with the source of the MOS tube M4 and the base of the triode Q8, one end of the resistor R7 is simultaneously connected with the grid of the MOS tube M4 and a capacitor C1, the other end of the capacitor C1 is connected with the ground wire with the drain of the MOS tube M4, the collector of the triode Q7 is connected with the power supply, the emitter of the triode Q8 is sequentially connected with the ground wire through a resistor R8 and an Itail, and a;

6. The automatic gain adjustment circuit applied to the burst transimpedance amplifier according to claim 5, characterized in that: the control voltage generating circuit comprises a current mirror bias, a constant current source I3, a resistor R10, a triode Q13, a MOS tube M7, a triode Q12, a constant current source I6, a constant current source I4, a triode Q14 and a resistor R11_、A cascode current mirror, a constant current source I5, a triode Q15, a resistor R12 and a triode Q16, the current mirror bias comprises a transistor Q9, a transistor Q10 and a transistor Q11, the bases of the transistor Q9, the transistor Q10 and the transistor Q11 are connected with each other, the emitting electrodes of the triode Q9, the triode Q10 and the triode Q11 are all connected with a power supply, the collector of the transistor Q9 is connected to the collector of the transistor Q8 in the threshold generation circuit, the collector of the triode Q10 is simultaneously connected with a constant current source I3, one end of a resistor R10 and the gate of an MOS tube M7, the other end of the resistor R10 is connected with the collector and the base of a triode Q13, the emitter of the triode Q13 is connected with the ground wire, the base electrode and the collector electrode of the triode Q12 are both connected with a power supply, the emitter electrode of the triode Q12 is connected with the drain electrode of the MOS tube M7, and the source electrode of the MOS tube M7 is simultaneously connected with the constant current source I6 and the triode Q14.The constant current source I4 is connected with the collector of a triode Q14 and a cascode current mirror at the same time, the emitter of the triode Q14 is connected with the ground wire through a resistor R11, the cascode current mirror is connected with the emitter of a triode Q15 and one end of a resistor R12 at the same time, the collector of a triode Q11 is connected with the constant current source I5, the collector of the triode Q15 and the base of a triode Q15 at the same time, the other end of the resistor R12 is connected with the collector and the base of a triode Q16 at the same time, and the emitter of the triode Q16 is connected with the ground wire;