CN212031655U - Over-temperature detection circuit of inverter circuit - Google Patents
Over-temperature detection circuit of inverter circuit Download PDFInfo
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- CN212031655U CN212031655U CN202020543211.0U CN202020543211U CN212031655U CN 212031655 U CN212031655 U CN 212031655U CN 202020543211 U CN202020543211 U CN 202020543211U CN 212031655 U CN212031655 U CN 212031655U
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Abstract
The utility model relates to a converter technical field discloses a temperature monitoring degree of accuracy is high and respond timely inverter circuit's overtemperature detection circuit, possesses: the temperature sensor comprises a sampling circuit (corresponding to PTC-1 and PTC-2), a controller (110), field effect transistors (MOS-1 and MOS-2) and a driver (120), wherein the controller (110) is used for receiving a temperature signal and comparing the temperature signal with a preset value; the signal input end of the driver (120) is connected with the drain electrodes of the field effect transistors (MOS-1 and MOS-2); the signal output end of the driver (120) is coupled to the grid of the IGBT; if the temperature signal is greater than or equal to the preset value, the controller (110) outputs low level to the field effect transistors (MOS-1 and MOS-2), and then the field effect transistors (MOS-1 and MOS-2) are closed, so that the driver (120) is controlled to stop outputting the pulse signal.
Description
Technical Field
The utility model relates to a converter technical field, more specifically say, relate to an inverter circuit's excess temperature detection circuitry.
Background
The frequency converter is applied to an inversion technology and a microelectronic technology, and controls power control equipment of an alternating current load by changing a load working power supply frequency mode. At present, a driving circuit outputs a Pulse Width Modulation (PWM) signal to drive an IGBT to operate, when a driving voltage output by the circuit is in a low voltage state, an internal temperature of the IGBT rises, and when the driving circuit is used for a long time, the internal temperature of the IGBT is in a critical point for a long time, which easily causes a performance reduction of the IGBT.
Therefore, how to improve the accuracy of the IGBT temperature monitoring and the feedback signal is a technical problem that needs to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, when the driving voltage to prior art's above-mentioned circuit output was in under-voltage state for IGBT's inside temperature risees and leads to IGBT's the defect of performance degradation, provides a temperature monitoring degree of accuracy height and responds timely inverter circuit's overtemperature prote detection circuit.
The utility model provides a technical scheme that its technical problem adopted is: an overtemperature detection circuit of an inverter circuit is constructed, and the overtemperature detection circuit is provided with:
the sampling circuit is configured at the bottom of the IGBT substrate and is used for acquiring a temperature signal of the IGBT;
the detection end of the controller is coupled with the output end of the sampling circuit, and the controller is used for receiving the temperature signal and comparing the temperature signal with a preset value;
at least one field effect transistor, the grid of which is coupled with the signal output end of the controller;
the signal input end of the driver is connected with the drain electrode of the field effect transistor;
the signal output end of the driver is coupled to the grid of the IGBT;
if the temperature signal is greater than or equal to the preset value, the controller outputs a low level to the field effect transistor, and then the field effect transistor is closed, so that the driver is controlled to stop outputting the pulse signal.
In some embodiments, the driver further comprises at least one clamping circuit for clamping the voltage input to the driver.
In some embodiments, the clamping circuit comprises a first clamping circuit and a second clamping circuit,
the first clamping circuit comprises a first diode and a second diode,
the anode of the first diode and the cathode of the second diode are respectively connected with the first signal input end of the driver,
the second clamping circuit comprises a fourth diode and a fifth diode,
and the anode of the fourth diode and the cathode of the fifth diode are respectively connected with the second signal input end of the driver.
In some embodiments, the field effect transistor comprises a first field effect transistor and a second field effect transistor,
the drain electrode of the first field effect transistor is respectively connected with the anode of the first diode and the cathode of the second diode;
and the drain electrode of the second field effect transistor is respectively connected with the anode of the fourth diode and the cathode of the fifth diode.
In some embodiments, the device further comprises a first triode and a second triode,
the base electrode of the first triode is connected with the drain electrode of the first field effect transistor through a fourth resistor, and the collector electrode of the first triode is connected with the first signal input end of the driver;
and the base electrode of the second triode is connected with the drain electrode of the second field effect transistor through a fourteenth resistor, and the collector electrode of the second triode is connected with the second signal input end of the driver.
In some embodiments, the system further comprises a first Schmitt trigger and a second Schmitt trigger,
the input end of the first Schmitt trigger is coupled to the drain electrode of the first field effect transistor, and the output end of the first Schmitt trigger is connected with the first signal input end of the driver;
the input end of the second Schmitt trigger is coupled to the drain electrode of the second field effect transistor, and the output end of the second Schmitt trigger is connected with the second signal input end of the driver.
The over-temperature detection circuit of the inverter circuit of the present invention comprises at least one sampling circuit, a controller, at least one field effect transistor and a driver, wherein the sampling circuit is used for acquiring a temperature signal of the IGBT and feeding the signal back to the controller for comparison with a preset value; if the temperature signal is greater than or equal to the preset value, the controller outputs low level to the field effect transistor, and then the field effect transistor is closed, so that the driver is controlled to stop outputting the pulse signal. Compared with the prior art, the surface temperature parameter of the IGBT is obtained through the sampling circuit and fed back to the controller, after the parameter is processed by the controller, if the processed parameter is larger than or equal to the preset value, the controller outputs a stop signal for controlling the driver, and the IGBT can be effectively ensured to run in a safer state.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a partial circuit diagram of an embodiment of an over-temperature detection circuit of an inverter circuit.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a partial circuit diagram of an embodiment of an over-temperature detection circuit of an inverter circuit. As shown in fig. 1, in a first embodiment of the over-temperature detection circuit of the inverter circuit of the present invention, the over-temperature detection circuit 100 of the inverter circuit includes at least one sampling circuit (corresponding to PTC-1 and PTC-2), a controller 110, at least one field effect transistor (corresponding to MOS-1 and MOS-2), at least one clamping circuit, and a driver 120.
Specifically, the sampling circuit (corresponding to PTC-1 and PTC-2) is disposed at the bottom of the IGBT module substrate or at one side of the IGBT module, and is configured to obtain a temperature signal of the IGBT module and feed back the signal to the detection terminal (corresponding to the PTC-IN terminal) of the controller 110.
Wherein, the sampling circuit (corresponding to PTC-1 and PTC-2) can be set as a thermistor.
The controller 100 is configured to generate driving signals a and B, wherein the driving signals a and B are PWM pulse signals.
After being conditioned by the preceding-stage driving circuit, the PWM pulse signals are respectively sent to the driving signal input ends INA and INB of the driver 120, and the INA and the INB respectively control an upper bridge arm (corresponding to the IGBT-1) and a lower bridge arm (corresponding to the IGBT-2) of the IGBT module.
The controller 100 is provided with a fault alarm signal circuit and a signal conditioning circuit, detects fault states of over-temperature, over-current, short circuit and the like of the IGBT, and is internally provided with a preset value, namely a temperature preset value or an over-current preset value, so as to enhance the triggering capability of a driving signal and improve the switching characteristic of the IGBT.
Specifically, the detection terminal (corresponding to the PTC-IN terminal) of the controller 100 is coupled to the output terminal of the sampling circuit (corresponding to the PTC-1 and the PTC-2), and the controller 100 is configured to receive the temperature signal fed back by the sampling circuit (corresponding to the PTC-1 and the PTC-2) and compare the temperature signal with the preset temperature value of the controller 100.
For example, the range of the preset temperature value may be set to 90-100 degrees, that is, when the temperature value detected by any thermistor in the sampling circuit (corresponding to PTC-1 and PTC-2) and fed back to the controller 100 falls within the preset temperature value range or is greater than the temperature range (or the critical range of the IGBT temperature), the controller 100 processes the fed-back temperature signal, and outputs a low-level signal for controlling a rear-stage circuit (such as a field effect transistor) to stop, so that the IGBT module stops working immediately, and the IGBT module can work in a safer environment, thereby improving the safety of the operation of the IGBT module.
At least one field effect transistor (MOS-1 and MOS-2) has switching and signal amplification functions.
Specifically, the gates of the field effect transistors (MOS-1 and MOS-2) are respectively connected to the signal output terminals (corresponding to terminals A or B) of the controller 110.
The field effect transistors are a first field effect transistor MOS-1 and a second field effect transistor MOS-2, and more specifically, a gate of the first field effect transistor MOS-1 is connected to a signal output terminal (corresponding to the terminal a) of the controller 110, a gate of the second field effect transistor MOS-2 is connected to a signal output terminal (corresponding to the terminal B) of the controller 110, and level signals output by the controller 110 are respectively output to the driver 120 through the first field effect transistor MOS-1 and the second field effect transistor MOS-2.
The driver 120 is a high-integration dual-channel driver, the interface is compatible with 3.3V-15V logic level signals, the grid driving voltage is +15V/-8V, the driving current is 8A, the single-channel output power is 1W, the driver can drive a 600A/1200V or 450A/1700V conventional IGBT module or a parallel IGBT module, and supports 3-level or multi-level topology. The circuit has the functions of short-circuit protection, overcurrent protection, power supply voltage monitoring and the like.
Specifically, the signal input terminals (corresponding to INA and INB terminals) of the driver 120 are connected to the drains of the field effect transistors (MOS-1 and MOS-2), respectively. More specifically, one signal input terminal (corresponding to INA terminal) of the driver 120 is connected to the drain of the first field effect transistor MOS-1, and the other signal input terminal (corresponding to INB terminal) of the driver 120 is connected to the drain of the second field effect transistor MOS-2.
The logic signal (i.e., high level or low level signal) or the pulse signal (i.e., PWM pulse signal) output by the controller 110 passes through the first field effect transistor MOS-1 and the second field effect transistor MOS-2, respectively, and then is input to the driver 120, and after being processed by the driver 120, is output to the IGBT module (corresponding to the IGBT-1 and the IGBT-2), so as to control the on/off of the IGBT module.
Specifically, the IGBT module is configured as a first IGBT-1 and a second IGBT-2, wherein gates of the first IGBT-1 and the second IGBT-2 are respectively connected to a signal output terminal (corresponding to the GH/GL terminal) of the driver 120 to control a working state of the IGBT module.
When the temperature signal fed back by the sampling circuit (corresponding to the PTC-1 and the PTC-2) is greater than or equal to the preset temperature value, the controller 100 outputs a low level to the field effect transistor (MOS-1 and MOS-2), and the low level is applied to the gate of the field effect transistor (MOS-1 and MOS-2) to make the field effect transistor (MOS-1 and MOS-2) lose the trigger voltage and switch from on to off, thereby controlling the driver 120 to stop outputting the PWM pulse signal, making the IGBT module (corresponding to the IGBT-1 and IGBT-2) lose the excitation pulse, and switching the IGBT module from on to off.
The temperature of the IGBT module is monitored by the sampling circuit (corresponding to the PTC-1 and the PTC-2) and fed back to the controller 100, and the controller 100 timely makes a response of stopping working, so that the running safety of the IGBT module is improved.
In some embodiments, to ensure the safety of the operation of the driver 120, at least one clamping circuit may be disposed in the circuit, wherein the clamping circuit is used to clamp the voltage input to the driver 120.
Specifically, the clamping circuit comprises a first clamping circuit and a second clamping circuit.
The first clamping circuit is formed by connecting a first diode D101 and a second diode D102, an anode of the first diode D101 and a cathode of the second diode D102 are respectively connected with a first signal input end (corresponding to an INA end) of the driver 120, a cathode of the first diode D101 is connected with a +15V power supply end, and an anode of the second diode D102 is connected with a circuit common end.
The second clamping circuit is formed by connecting a fourth diode D201 and a fifth diode D202, wherein an anode of the fourth diode D201 and a cathode of the fifth diode D202 are respectively connected to the second signal input terminal (corresponding to the INB terminal) of the driver 120. The cathode of the fourth diode D201 is connected to the +15V power supply terminal, and the anode of the fifth diode D202 is connected to the circuit common terminal.
The input voltage can be clamped at about +15V through the first clamping circuit and the second clamping circuit, so that the driver 120 and the IGBT module can work in a stable voltage range, and the safety of a rear-stage circuit is further improved.
In some embodiments, the field effect transistors include a first field effect transistor MOS-1 and a second field effect transistor MOS-2, which have the functions of switching and signal amplification.
Specifically, the drain of the first field effect transistor MOS-1 is connected to the anode of the first diode D101 and the cathode of the second diode D102, respectively, the gate of the first field effect transistor MOS-1 is connected to a signal output terminal (corresponding to the terminal a) of the controller 100, and the source of the first field effect transistor MOS-1 is connected to the common terminal.
The on/off of the first field effect transistor MOS-1 is controlled by the logic level output by the controller 100, and when the first field effect transistor MOS-1 is on, the controller 100 outputs a high level; when the first field effect transistor MOS-1 is turned off, the controller 100 outputs a low level.
Further, the drain of the second field effect transistor MOS-2 is connected to the anode of the fourth diode D201 and the cathode of the fifth diode D202, respectively, the gate of the second field effect transistor MOS-2 is connected to another signal output terminal (corresponding to terminal B) of the controller 100, and the source of the second field effect transistor MOS-2 is connected to the common terminal.
The on/off of the second field effect transistor MOS-2 is controlled by the logic level output by the controller 100, and when the second field effect transistor MOS-2 is switched on, the controller 100 outputs a high level; when the second field effect transistor MOS-2 is turned off, the controller 100 outputs a low level.
In some embodiments, in order to ensure the accuracy of the two-way signal interaction, a first transistor VT1, a second transistor VT2, a third diode D103 and a sixth diode D203 may be disposed in the circuit.
Wherein, the triode has the function of a switch.
The third diode D103 and the sixth diode D203 are zener diodes, and the zener value thereof is 3.3V.
Specifically, the base of the first transistor VT1 is connected to the anode of the third diode D103, the cathode of the third diode D103 is connected to the drain of the first field effect transistor MOS-1 through the fourth resistor R104, and the collector of the first transistor VT1 is connected to the first signal input terminal (corresponding to the INA terminal) of the driver 120.
Further, the base of the second transistor VT2 is connected to the anode of the sixth diode D203, the cathode of the sixth diode D203 is connected to the drain of the second field effect transistor MOS-2 through the fourteenth resistor R204, and the collector of the second transistor VT2 is connected to the second signal input terminal (corresponding to the INA terminal) of the driver 120.
The emitters of the first transistor VT1 and the second transistor VT2 are connected with the common end of the circuit.
Specifically, a circuit network formed by the first transistor VT1 and the second transistor VT2 mainly completes the interlocking of the two signals and the setting of the dead time, and the dead time of the two driving signals can be adjusted according to the regulated voltage values of the third diode D103 and the sixth diode D203.
In some embodiments, in order to improve the performance of the circuit, a first schmitt trigger (composed of U101A and U101B) and a second schmitt trigger (composed of U101C and U101E) can be arranged in the circuit, and have two stable states, wherein the schmitt trigger adopts a potential triggering mode, and the states of the schmitt trigger are maintained by the input signal potential; for input signals with two different changing directions of negative decreasing and positive increasing, the Schmitt trigger has different threshold voltages.
Specifically, an input terminal of the first schmitt trigger (corresponding to U101A) is coupled to the drain terminal of the first field effect transistor MOS-1, and an output terminal of the first schmitt trigger (corresponding to U101B) is connected to the first signal input terminal (corresponding to INA) of the driver 120; an input terminal of a second schmitt trigger (corresponding to U101C) is coupled to the drain of the second field effect transistor MOS-2, and an output terminal of the second schmitt trigger (corresponding to U101E) is connected to a second signal input terminal (corresponding to INB) of the driver 120.
That is, the logic level and PWM pulse signal outputted through the first field effect transistor MOS-1 and the second field effect transistor MOS-2 are outputted to the signal input terminal of the driver 120 through the first schmitt trigger and the second schmitt trigger, and the inputted signal is processed by the driver 120 and then used for controlling the operating state of the IGBT module.
Illustratively, the output end is an open collector gate circuit in a fault state, and a pull-up resistor is connected to the outside. When a fault (over-temperature or over-current of the IGBT) occurs, correspondingly outputting a low level; otherwise, a high level is output. If the power supply voltage is under-voltage, the driver is blocked and the two fault output ends send out alarm signals at the same time until the power supply voltage works normally.
When a secondary side fails (an IGBT over-temperature or an IGBT over-current is detected), an alarm signal is sent at a corresponding failure output terminal of the driver 120, and after a dead time elapses, the corresponding failure signal disappears. All fault states are reported to the controller 110 through the fault signal conditioning circuit.
Because the fault state output end is a collector open-circuit gate circuit, two fault output ends are directly short-circuited to realize NOR logic and serve as a fault alarm signal common end. When any of the above-mentioned faults occurs, the fault is reported to the controller 100 as a valid fault signal, and corresponding processing is performed, so that the circuit hardware design can be simplified, and the reliability of the driver 120 can be improved.
The embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention, and all of them fall within the protection scope of the present invention.
Claims (6)
1. An over-temperature detection circuit for an inverter circuit, comprising:
the sampling circuit is configured at the bottom of the IGBT substrate and is used for acquiring a temperature signal of the IGBT;
the detection end of the controller is coupled with the output end of the sampling circuit, and the controller is used for receiving the temperature signal and comparing the temperature signal with a preset value;
at least one field effect transistor, the grid of which is coupled with the signal output end of the controller;
the signal input end of the driver is connected with the drain electrode of the field effect transistor;
the signal output end of the driver is coupled to the grid of the IGBT;
if the temperature signal is greater than or equal to the preset value, the controller outputs a low level to the field effect transistor, and then the field effect transistor is closed, so that the driver is controlled to stop outputting the pulse signal.
2. The over-temperature detection circuit of an inverter circuit according to claim 1,
the clamping circuit is used for clamping the voltage input into the driver.
3. The over-temperature detection circuit of an inverter circuit according to claim 2,
the clamping circuit comprises a first clamping circuit and a second clamping circuit,
the first clamping circuit comprises a first diode and a second diode,
the anode of the first diode and the cathode of the second diode are respectively connected with the first signal input end of the driver,
the second clamping circuit comprises a fourth diode and a fifth diode,
and the anode of the fourth diode and the cathode of the fifth diode are respectively connected with the second signal input end of the driver.
4. The over-temperature detection circuit of an inverter circuit according to claim 3,
the field effect transistor comprises a first field effect transistor and a second field effect transistor,
the drain electrode of the first field effect transistor is respectively connected with the anode of the first diode and the cathode of the second diode;
and the drain electrode of the second field effect transistor is respectively connected with the anode of the fourth diode and the cathode of the fifth diode.
5. The over-temperature detection circuit of an inverter circuit according to claim 4,
also comprises a first triode and a second triode,
the base electrode of the first triode is connected with the drain electrode of the first field effect transistor through a fourth resistor, and the collector electrode of the first triode is connected with the first signal input end of the driver;
and the base electrode of the second triode is connected with the drain electrode of the second field effect transistor through a fourteenth resistor, and the collector electrode of the second triode is connected with the second signal input end of the driver.
6. The over-temperature detection circuit of an inverter circuit according to claim 5,
also comprises a first Schmitt trigger and a second Schmitt trigger,
the input end of the first Schmitt trigger is coupled to the drain electrode of the first field effect transistor, and the output end of the first Schmitt trigger is connected with the first signal input end of the driver;
the input end of the second Schmitt trigger is coupled to the drain electrode of the second field effect transistor, and the output end of the second Schmitt trigger is connected with the second signal input end of the driver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020543211.0U CN212031655U (en) | 2020-04-13 | 2020-04-13 | Over-temperature detection circuit of inverter circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020543211.0U CN212031655U (en) | 2020-04-13 | 2020-04-13 | Over-temperature detection circuit of inverter circuit |
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| Publication Number | Publication Date |
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| CN212031655U true CN212031655U (en) | 2020-11-27 |
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| CN202020543211.0U Active CN212031655U (en) | 2020-04-13 | 2020-04-13 | Over-temperature detection circuit of inverter circuit |
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