CN212012605U - Symmetrical and asymmetrical isolated drive signal transmission circuit - Google Patents

Abstract

The utility model provides a symmetry and asymmetric isolated drive signal transmission circuit, include: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the output circuit from the power supply and the ground of the output circuit; the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal; the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation. Compared with the conventional 2FSK modulation, the symmetrical and asymmetrical isolated drive signal transmission circuit has lower requirement on a carrier signal, does not influence the modulation and demodulation of the drive signal when the carrier frequency and the asymmetrical fluctuation are not large, reduces the difficulty of circuit design and improves the robustness of a product.

Description

Symmetrical and asymmetrical isolated drive signal transmission circuit

Technical Field

The utility model relates to an isolating circuit especially relates to isolated drive signal transmission circuit.

Background

The primary role of isolation is to separate one line from interference by another, for example by using an insulator (dielectric) to separate the two lines. It can also be said that two different voltage domains are isolated, for example, in a control system, a processor power supply is usually 5V low voltage, a load power supply is usually 220V high voltage, and if the two voltage domains are not isolated, the operation of the high voltage domain can cause serious interference to the low voltage domain, and even damage to devices in the low voltage domain. If the digital signal can be transmitted while being isolated, it is usually carried by a high frequency carrier. The medium which can not only isolate high voltage but also transmit signals is an inductor, a transformer, an optical coupler, a capacitor, an NVE magnetic switch, a GMR giant magnetoresistance and the like.

Isolation is applicable to the gate drive of MOS/IGBT's driving motors, which is a floating-ground architecture, the power supply of the two lines is not uniform with ground, and its non-uniformity also varies with Transient variations, thus creating a so-called Common Mode Transient Immunity (CMTI) performance index, which better represents the higher tolerance to Common Mode Transient Interference (CMTI), since this high frequency Transient Common Mode interference can disrupt the information transfer between the isolation dielectrics. It is therefore desirable to develop isolation techniques that are resistant to CMTI interference.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the main technical problem that a symmetry and asymmetric isolated drive signal transmission circuit is provided, the circuit design degree of difficulty has been reduced, the robustness of product has been improved.

In order to solve the technical problem, the utility model provides a symmetry and asymmetric isolated drive signal transmission circuit, include: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the input circuit from the power supply and the ground of the output circuit;

the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal;

the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation.

In a preferred embodiment: when the modulation signal is a symmetrical carrier signal, an output signal generated after carrier voltage conversion demodulation is a high level;

when the modulation signal is an asymmetric carrier signal, an output signal generated after carrier voltage conversion demodulation is at a low level.

In a preferred embodiment: the waveform of the output signal is the same as that of the input signal and has a certain time delay.

In a preferred embodiment: the demodulation circuit comprises a high-pass filter, a low-gain amplifier, a low-pass filter, a carrier voltage conversion circuit and a comparator;

the output end of the high-pass filter is connected with the input end of the low-gain amplifier; the output end of the low-voltage gain amplifier is connected to the comparator after passing through the low-pass filter and the carrier voltage conversion circuit.

In a preferred embodiment: the modulation circuit comprises a voltage-controlled oscillator, a logic processing circuit, a multiplexer and a first bias circuit; the first bias circuit provides bias voltage and bias current for the voltage-controlled vibrator, the logic processing circuit and the multiplexer.

In a preferred embodiment: the logic processing circuit comprises a trigger DFF1 and a trigger DFF 2; high-frequency oscillation signals generated by the voltage-controlled oscillator generate frequency division signals with phases different by half clock period through a trigger DFF1 and a trigger DFF2 respectively;

the symmetrical carrier 1 output by the trigger DFF1 generates a symmetrical carrier 2 and an asymmetrical carrier 1 through a logic processing circuit, wherein the symmetrical carrier 2 and the symmetrical carrier 1 have opposite phases; the frequency division signal output by the trigger DFF2 generates an asymmetric carrier 2 through a logic processing circuit;

and the symmetrical carrier 1, the symmetrical carrier 2, the asymmetrical carrier 1 and the asymmetrical carrier 2 are respectively input into a multiplexer.

In a preferred embodiment: the flip-flop DFF1 is triggered by rising edge, and the flip-flop DFF2 is triggered by falling edge.

In a preferred embodiment: the symmetrical carrier passes through a first delay unit, an inverter INV1, a NOR gate NOR1, an inverter INV2 and a NAND gate NAND1 to generate an asymmetrical carrier 1; the frequency-divided signal output by the flip-flop DFF2 passes through the second delay unit, the inverter INV3, the NOR gate NOR2, the inverter INV4, and the NAND gate NAND2, and generates the asymmetric carrier 2.

In a preferred embodiment: the duty ratio of the asymmetrical carrier 1 and the asymmetrical carrier 2 is determined by the delay time of the first delay unit and the second delay unit to be not more than 15%.

In a preferred embodiment: the multiplexer outputs a symmetric carrier 1 and a symmetric carrier 2 when the input signal is high level, and outputs an asymmetric carrier 1 and an asymmetric carrier 2 when the input signal is low level.

Compared with the prior art, the technical scheme of the utility model possess following beneficial effect:

1. the utility model provides a symmetry and asymmetric isolated drive signal transmission circuit changes voltage at the input line part with the carrier and modulates, compares with conventional 2FSK modulation, requires lowerly to carrier signal, and when carrier frequency and asymmetry fluctuate not much, does not influence drive signal's modulation and demodulation, has reduced the circuit design degree of difficulty, has improved the robustness of product.

2. The utility model provides a symmetry and asymmetric isolated drive signal transmission circuit, in output line's demodulation circuit, high pass filter directly adopts low gain amplifier at the back, rather than adopting the comparator, has avoided the change of signal rail to rail, compares this output signal range less with rail to rail signal, and to a great extent has reduced output signal's rising edge and decline along the time, has improved efficiency greatly when the drive power device.

Drawings

FIG. 1 is an overall frame diagram of a preferred embodiment of the present invention;

fig. 2 is a block diagram of a modulation module according to a preferred embodiment of the present invention;

FIG. 3 is a diagram of an example of a modulation circuit according to a preferred embodiment of the present invention

Fig. 4 is a diagram of an example of a voltage-controlled oscillator according to a preferred embodiment of the present invention;

fig. 5 is a block diagram of a demodulation circuit according to a preferred embodiment of the present invention;

fig. 6 is a waveform diagram of a modulation circuit node according to the preferred embodiment of the present invention;

fig. 7 is a waveform diagram of the whole line node according to the preferred embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further explained by the accompanying drawings and the specific embodiments.

Referring to fig. 1-7, a symmetrical and asymmetrical isolated drive signal transmission circuit includes: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the input circuit from the power supply and the ground of the output circuit;

the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal; the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation.

In this embodiment, when the modulation signal is a symmetric carrier signal, an output signal generated after carrier-to-voltage demodulation is a high level; when the modulation signal is an asymmetric carrier signal, an output signal generated after carrier voltage conversion demodulation is at a low level. The waveform of the output signal is the same as that of the input signal and has a certain time delay.

In order to generate a symmetric or asymmetric modulation signal after the voltage subcarrier modulation, in this embodiment, the input line includes a Voltage Controlled Oscillator (VCO), a LOGIC processing circuit (LOGIC), a multiplexer, a first driving circuit, and a first bias circuit for providing a bias voltage and a bias current to the input line; the voltage-controlled oscillator and the multiplexer respectively generate a symmetrical carrier and an asymmetrical carrier according to the high or low of an input signal to realize a modulation function. The drive circuit part receives the modulation signal and realizes the level shift function. The power and ground of the input lines are VDD1 and GND1, respectively.

Fig. 2 is a block diagram of a modulation circuit, which is composed of a Voltage Controlled Oscillator (VCO), a LOGIC processing circuit (LOGIC), a multiplexer, and a bias circuit for providing a bias voltage and a bias current to the multiplexer.

Fig. 3 is a specific embodiment of a modulation circuit: a Voltage Controlled Oscillator (VCO) generates a high frequency oscillation signal which is divided by a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF1 is a rising edge trigger, and a flip-flop DFF2 is a falling rising edge trigger, thereby generating divided signals at the output terminals of DFF1 and DFF2 which are out of phase by a half clock period. The output of the DFF1 is a symmetrical carrier 1, the symmetrical carrier 1 generates a symmetrical carrier 2 through an inverter INV5, and the phases of the symmetrical carrier 1 and the symmetrical carrier 2 are reversed, i.e. the phase difference is half a clock cycle; the output of the DFF1 passes through a delay unit, an inverter INV1, a NOR gate NOR1, an inverter INV2, and a NAND gate NAND1, generating an asymmetric carrier 1; the output of the flip-flop DFF2 passes through a delay unit, inverter INV3, NOR gate NOR2, inverter INV4, NAND gate NAND2, generating asymmetric carrier 2.

The symmetrical carrier 1, the symmetrical carrier 2, the asymmetrical carrier 1 and the asymmetrical carrier 2 are input into the multiplexer. The multiplexer outputs the symmetric carrier 1 and the symmetric carrier 2 when the input signal is high level, and outputs the asymmetric carrier 1 and the asymmetric carrier 2 when the input signal is low level. The delay time of the delay unit determines the duty ratio of the asymmetric carrier, and in order to ensure that the demodulation circuit can correctly demodulate an input signal, the duty ratio of the asymmetric carrier cannot be too large, and the simulation verification cannot exceed 15%. The voltage waveform diagram of each node of the modulation circuit is shown in fig. 6.

Fig. 4 shows an embodiment of a voltage controlled oscillator, which is used to provide a high frequency pulse signal for a carrier signal. The amplifier is composed of an amplifier, a RING oscillator (RING OSC), a frequency-to-voltage line (F to V), a level shift line (LEVEL SHIFT), an inverter INV6 and an inverter INV 7. The working principle is as follows: the amplifier, the RING oscillator (RING OSC), and the frequency-to-voltage line (F to V) form a negative feedback loop structure, the power supply voltage of the RING oscillator is adjusted by the output (point a) of the amplifier, and if the power supply voltage is high, the output frequency of the RING oscillator is high, and if the power supply voltage is low, the output frequency of the RING oscillator is low. The resistor R1, the MOS tube P1, the resistor R3 and the capacitor C1 form a frequency-to-voltage circuit. The working principle is as follows: the MOS transistor P4 and the capacitor C1 form a switched capacitor circuit, the capacitor C1 is equivalent to a variable resistor, the resistance value changes with the frequency change, namely the resistors R1, R3 and the capacitor C1 form a resistor divider, the resistance value of the capacitor C1 changes with the frequency change, and the voltage Vctr changes with the frequency change. The output of the inverter INV5 is the output of the ring oscillator, and by level shifting (LEVEL SHIFT), the inverter INV6 and the inverter INV7 output as clock signals of the high frequency carrier.

The isolation medium is composed of a high-voltage capacitor, and has the advantages of easy realization in process, high matching degree, small area, reduced cost and improved product competitiveness.

The output circuit comprises a high-pass filter (HPF), a low-gain amplifier, a low-pass filter (LPF), a carrier voltage conversion circuit, a comparator, a driving circuit and a second bias circuit for providing bias voltage and bias current for the whole output circuit. The high-voltage isolation capacitor, the filter and the low-gain amplifier, the low-pass filter (LPF), the carrier voltage conversion circuit and the comparator jointly form a demodulation circuit. If the high-voltage isolation capacitor receives symmetrical carrier signals, a high level is demodulated through the demodulation circuit, if the high-voltage isolation capacitor receives asymmetrical carrier signals (the pulse width is small, the duty ratio is 10 +/-5%), a low level is demodulated through the demodulation circuit, the drive circuit realizes level conversion, and finally the grid of the drive power device is output.

The overall structure of the demodulation circuit is shown in fig. 5: the high-pass filter, the low-gain amplifier, the low-pass filter, the carrier voltage conversion circuit and the comparator. The high-voltage isolation capacitor and the resistor Ra form a first-stage high-pass filter (HPF), the low-voltage capacitor C1 and the resistor R1 form a second-stage high-pass filter, the two-stage filter filters low-frequency interference of a modulation signal, and the high-frequency modulation signal passes through. The voltage amplitude after high-pass filtering is very small, so the output of the filter is connected with a dual-input dual-output amplifier, the amplifier adopts a low-gain dual-input dual-output amplifier, and the amplifier has two functions, namely, the amplitude of a voltage signal is amplified, and a proper common mode level is provided for the output voltage of the filter to be used as a comparison voltage of a subsequent comparator. A resistor R2 and a capacitor C2 form a Low Pass Filter (LPF) which performs low pass filtering on the output of the low gain amplifier, so that two voltage signals with different amplitudes are formed before and after the low pass filter, the amplitude of the voltage signal before the filter is larger than that after the filter, namely the amplitude of the voltage signal at the point A1 is larger than that at the point B1, the amplitude of the voltage signal at the point A2 is larger than that at the point B2, the voltage amplitudes at the points A1 and A2 are equal in amplitude and have a phase difference of half a clock cycle, and the voltage amplitudes at the points B1 and B2 are equal in phase difference of half a clock cycle; and signals before and after the low-pass filter are used as input signals of the carrier voltage conversion circuit. The carrier voltage conversion circuit consists of NMOS transistors N1, N2, N3 and N4, a resistor Roffset and a current source I1, and actually the devices form the structure of a source follower. The effect of the resistor Roffset is to generate a voltage drop of I1 × Roffset on the resistor Roffset, and the voltage drop is used as a hysteresis voltage of a subsequent comparator, so that when the modulation signal is an asymmetric carrier, the output of the comparator is prevented from being unstable. The working principle of the carrier voltage conversion circuit is as follows: when the modulation signal is a symmetric carrier, because the amplitudes of the voltage signals of a1 and a2 are higher than those of B1 and B2, and the phases of a1 and a2 are different by a half clock cycle, and the phases of B1 and B2 are different by a half clock cycle, the source voltages of N1 and N2 are always higher than those of N3 and N4, and the voltage drop of Roffset is properly set, so that the voltage of OUT1 is always higher than that of OUT2, and the voltages of OUT1 and OUT2 are respectively connected with the positive input terminal (INP) and the negative input terminal (INN) of the comparator, in this case, the comparator outputs a high level, the output of the comparator is input to the driving circuit part, and the driving circuit finally drives the gate of the power device through level shifting, so as to complete the demodulation function.

When the modulation signal is an asymmetric carrier, because the duty ratio of the asymmetric carrier is small, when the asymmetric carrier passes through a multi-stage high-pass filter and then passes through a low-gain amplifier, the influence of the high-level part of the asymmetric carrier can be ignored, and the amplitudes of the voltage signals before and after the low-pass filter (LPF) are basically consistent, that is, the amplitudes of the voltage signals at points a1, a2, B1 and B2 are basically equal, the source voltages of corresponding points N1, N2, N3 and N4 are equal, but because the hysteresis voltage I1 × Roffset exists, the voltage at the point OUT2 is higher than the voltage at the point OUT1, the point OUT1 and the point OUT2 are respectively connected with the positive input terminal (INP) and the negative input terminal (INN) of the comparator, and the comparator outputs a low level in this case. The output of the comparator is input to the driving circuit part, and the driving circuit finally drives the grid of the power device through level shift to complete the demodulation function.

Compared with the conventional 2FSK modulation, the symmetrical and asymmetrical isolated drive signal transmission circuit has lower requirement on a carrier signal, does not influence the modulation and demodulation of the drive signal when the carrier frequency and the asymmetrical fluctuation are not large, reduces the difficulty of circuit design and improves the robustness of a product.

In addition, in a demodulation circuit of an output circuit, a low-gain amplifier is directly adopted behind a high-pass filter instead of a comparator, so that the change of a signal rail to rail is avoided, the amplitude of an output signal is smaller compared with a rail to rail signal, the rising edge time and the falling edge time of the output signal are reduced to a great extent, and the efficiency is greatly improved when a power device is driven.

The above description is only a preferred embodiment of the present invention, and therefore the scope of the present invention should not be limited by this description, and all equivalent changes and modifications made within the scope and the specification of the present invention should be covered by the present invention.

Claims (10)

1. Symmetrical and asymmetrical isolated drive signal transmission circuit, characterized by comprising: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the input circuit from the power supply and the ground of the output circuit;

the input line generates a symmetrical or asymmetrical modulation signal to the isolation medium after voltage of the modulation circuit is converted into carrier wave for modulation according to the level condition of the input signal;

the output line receives the modulated signal passing through the isolation medium, and generates an output signal after the modulated signal passes through the carrier-to-voltage demodulation of the demodulation circuit.

2. The symmetric and asymmetric isolated drive signal transmission circuit of claim 1, wherein: when the modulation signal is a symmetrical carrier signal, an output signal generated after carrier voltage conversion demodulation is a high level;

when the modulation signal is an asymmetric carrier signal, an output signal generated after carrier voltage conversion demodulation is at a low level.

3. The symmetric and asymmetric isolated drive signal transmission circuit of claim 1, wherein: the waveform of the output signal is the same as that of the input signal and has a certain time delay.

4. The symmetric and asymmetric isolated drive signal transmission circuit according to any of claims 1-3, wherein: the demodulation circuit comprises a high-pass filter, a low-gain amplifier, a low-pass filter, a carrier voltage conversion circuit and a comparator;

the output end of the high-pass filter is connected with the input end of the low-gain amplifier; the output end of the low-voltage gain amplifier is connected to the comparator after passing through the low-pass filter and the carrier voltage conversion circuit.

5. The symmetric and asymmetric isolated drive signal transmission circuit of claim 4, wherein: the modulation circuit comprises a voltage-controlled oscillator, a logic processing circuit, a multiplexer and a first bias circuit; the first bias circuit provides bias voltage and bias current for the voltage-controlled vibrator, the logic processing circuit and the multiplexer.

6. The symmetric and asymmetric isolated drive signal transmission circuit of claim 5, wherein: the logic processing circuit comprises a trigger DFF1 and a trigger DFF 2; high-frequency oscillation signals generated by the voltage-controlled oscillator generate frequency division signals with phases different by half clock period through a trigger DFF1 and a trigger DFF2 respectively;

the symmetrical carrier 1 output by the trigger DFF1 generates a symmetrical carrier 2 and an asymmetrical carrier 1 through a logic processing circuit, wherein the symmetrical carrier 2 and the symmetrical carrier 1 have opposite phases; the frequency division signal output by the trigger DFF2 generates an asymmetric carrier 2 through a logic processing circuit;

and the symmetrical carrier 1, the symmetrical carrier 2, the asymmetrical carrier 1 and the asymmetrical carrier 2 are respectively input into a multiplexer.

7. The symmetric and asymmetric isolated drive signal transmission circuit of claim 6, wherein: the flip-flop DFF1 is triggered by rising edge, and the flip-flop DFF2 is triggered by falling edge.

8. The symmetric and asymmetric isolated drive signal transmission circuit of claim 7, wherein: the symmetrical carrier passes through a first delay unit, an inverter INV1, a NOR gate NOR1, an inverter INV2 and a NAND gate NAND1 to generate an asymmetrical carrier 1; the frequency-divided signal output by the flip-flop DFF2 passes through the second delay unit, the inverter INV3, the NOR gate NOR2, the inverter INV4, and the NAND gate NAND2, and generates the asymmetric carrier 2.

9. The symmetric and asymmetric isolated drive signal transmission circuit of claim 8, wherein: the duty ratio of the asymmetrical carrier 1 and the asymmetrical carrier 2 is determined by the delay time of the first delay unit and the second delay unit to be not more than 15%.

10. The symmetric and asymmetric isolated drive signal transmission circuit according to any of claims 7-9, wherein: the multiplexer outputs a symmetric carrier 1 and a symmetric carrier 2 when the input signal is high level, and outputs an asymmetric carrier 1 and an asymmetric carrier 2 when the input signal is low level.

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