CN111464176A - Symmetrical and asymmetrical isolated drive signal transmission circuit - Google Patents
Symmetrical and asymmetrical isolated drive signal transmission circuit Download PDFInfo
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- CN111464176A CN111464176A CN202010312155.4A CN202010312155A CN111464176A CN 111464176 A CN111464176 A CN 111464176A CN 202010312155 A CN202010312155 A CN 202010312155A CN 111464176 A CN111464176 A CN 111464176A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Abstract
The invention provides a symmetrical and asymmetrical isolated drive signal transmission circuit, which comprises: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the output circuit from the power supply and the ground of the output circuit; the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal; the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation. Compared with the conventional 2FSK modulation, the symmetrical and asymmetrical isolated drive signal transmission circuit has lower requirement on a carrier signal, does not influence the modulation and demodulation of the drive signal when the carrier frequency and the asymmetrical fluctuation are not large, reduces the difficulty of circuit design and improves the robustness of a product.
Description
Technical Field
The present invention relates to an isolation circuit, and more particularly, to an isolated driving signal transmission circuit.
Background
The primary role of isolation is to separate one line from interference by another, for example by using an insulator (dielectric) to separate the two lines. It can also be said that two different voltage domains are isolated, for example, in a control system, a processor power supply is usually 5V low voltage, a load power supply is usually 220V high voltage, and if the two voltage domains are not isolated, the operation of the high voltage domain can cause serious interference to the low voltage domain, and even damage to devices in the low voltage domain. If the digital signal can be transmitted while being isolated, it is usually carried by a high frequency carrier. The medium which can not only isolate high voltage but also transmit signals is an inductor, a transformer, an optical coupler, a capacitor, an NVE magnetic switch, a GMR giant magnetoresistance and the like.
Isolation is applicable to the gate drive of MOS/IGBT's driving motors, which is a floating-ground architecture, the power supply of the two lines is not uniform with ground, and its non-uniformity also varies with Transient variations, thus creating a so-called Common Mode Transient Immunity (CMTI) performance index, which better represents the higher tolerance to Common Mode Transient Interference (CMTI), since this high frequency Transient Common Mode interference can disrupt the information transfer between the isolation dielectrics. It is therefore desirable to develop isolation techniques that are resistant to CMTI interference.
Disclosure of Invention
The invention aims to provide a symmetrical and asymmetrical isolated drive signal transmission circuit, which reduces the circuit design difficulty and improves the robustness of a product.
In order to solve the above technical problem, the present invention provides a symmetric and asymmetric isolated driving signal transmission circuit, including: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the output circuit from the power supply and the ground of the output circuit;
the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal;
the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation.
In a preferred embodiment: when the modulation signal is a symmetrical carrier signal, an output signal generated after carrier voltage conversion demodulation is a high level;
when the modulation signal is an asymmetric carrier signal, an output signal generated after carrier voltage conversion demodulation is at a low level.
In a preferred embodiment: the waveform of the output signal is the same as that of the input signal and has a certain time delay.
In a preferred embodiment: the demodulation circuit comprises a high-pass filter, a low-gain amplifier, a low-pass filter, a carrier voltage conversion circuit and a comparator;
the output end of the high-pass filter is connected with the input end of the low-gain amplifier; the output end of the low gain amplifier is connected to the comparator after passing through the low pass filter and the carrier voltage conversion circuit.
In a preferred embodiment: the modulation circuit comprises a voltage-controlled oscillator, a logic processing circuit, a multiplexer and a first bias circuit; the first bias circuit provides bias voltage and bias current for the voltage-controlled vibrator, the logic processing circuit and the multiplexer.
In a preferred embodiment: the logic processing circuit comprises a trigger DFF1 and a trigger DFF 2; high-frequency oscillation signals generated by the voltage-controlled oscillator generate frequency division signals with phases different by half clock period through a trigger DFF1 and a trigger DFF2 respectively;
the symmetrical carrier 1 output by the trigger DFF1 generates a symmetrical carrier 2 and an asymmetrical carrier 1 through a logic processing circuit, wherein the symmetrical carrier 2 and the symmetrical carrier 1 have opposite phases; the carrier signal output by the trigger DFF2 generates an asymmetric carrier 2 through a logic processing circuit;
and the symmetrical carrier 1, the symmetrical carrier 2, the asymmetrical carrier 1 and the asymmetrical carrier 2 are respectively input into a multiplexer.
In a preferred embodiment: the flip-flop DFF1 is triggered by rising edge, and the flip-flop DFF2 is triggered by falling edge.
In a preferred embodiment: the symmetrical carrier passes through a first delay unit, an inverter INV1, a NOR gate NOR1, an inverter INV2 and a NAND gate NAND1 to generate an asymmetrical carrier 1; the frequency-divided signal output by the flip-flop DFF2 passes through the second delay unit, the inverter INV3, the NOR gate NOR2, the inverter INV4, and the NAND gate NAND2, and generates the asymmetric carrier 2.
In a preferred embodiment: the duty ratio of the asymmetrical carrier 1 and the asymmetrical carrier 2 is determined by the delay time of the first delay unit and the second delay unit to be not more than 15%.
In a preferred embodiment: the multiplexer outputs a symmetric carrier 1 and a symmetric carrier 2 when the input signal is high level, and outputs an asymmetric carrier 1 and an asymmetric carrier 2 when the input signal is low level.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the symmetrical and asymmetrical isolated drive signal transmission circuit, the input line part is modulated by converting carrier waves into voltage, compared with the conventional 2FSK modulation, the requirement on carrier signals is low, when the carrier frequency and the asymmetrical fluctuation are not large, the modulation and demodulation of the drive signals are not influenced, the circuit design difficulty is reduced, and the robustness of a product is improved.
2. In the demodulation circuit of the output circuit, the low-gain amplifier is directly adopted behind the high-pass filter instead of the comparator, so that the change of the signal rail to rail is avoided.
Drawings
FIG. 1 is an overall frame diagram of a preferred embodiment of the present invention;
FIG. 2 is a block diagram of a modulation module according to a preferred embodiment of the present invention;
FIG. 3 is a diagram of an exemplary modulation circuit according to a preferred embodiment of the present invention
Fig. 4 is a diagram of an example voltage controlled oscillator according to a preferred embodiment of the present invention;
FIG. 5 is a block diagram of a demodulation circuit according to a preferred embodiment of the present invention;
FIG. 6 is a waveform diagram of a modulation circuit node according to a preferred embodiment of the present invention;
fig. 7 is a waveform diagram of the overall line node of the preferred embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further explained by the accompanying drawings and the specific embodiments.
Referring to fig. 1-7, a symmetric and asymmetric isolated driving signal transmission circuit includes: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the output circuit from the power supply and the ground of the output circuit;
the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal; the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation.
In this embodiment, when the modulation signal is a symmetric carrier signal, an output signal generated after carrier-to-voltage demodulation is a high level; when the modulation signal is an asymmetric carrier signal, an output signal generated after carrier voltage conversion demodulation is at a low level. The waveform of the output signal is the same as that of the input signal and has a certain time delay.
In order to realize the above-mentioned generation of a symmetric or asymmetric modulation signal after voltage-to-carrier modulation, in this embodiment, the input line includes a Voltage Controlled Oscillator (VCO), a logic processing circuit (L OGIC), a multiplexer, a first driving circuit, and a first bias circuit for providing a bias voltage and a bias current to the input line, wherein the voltage controlled oscillator and the multiplexer respectively output a symmetric carrier and an asymmetric carrier according to the high or low of the input signal to realize a modulation function, the driving circuit partially receives the modulation signal to realize a level shift function, and the power supply and the ground of the input line are VDD1 and GND1, respectively.
Fig. 2 is a block diagram of a modulation circuit, which is composed of a Voltage Controlled Oscillator (VCO), a logic processing circuit (L OGIC), a multiplexer, and a bias circuit for providing a bias voltage and a bias current to the multiplexer.
Fig. 3 is a specific embodiment of a modulation circuit: a Voltage Controlled Oscillator (VCO) generates a high frequency oscillation signal which is divided by a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF1 is a rising edge trigger, and a flip-flop DFF2 is a falling rising edge trigger, thereby generating divided signals at the output terminals of DFF1 and DFF2 which are out of phase by a half clock period. The output of the DFF1 is a symmetrical carrier 1, the symmetrical carrier 1 generates a symmetrical carrier 2 through an inverter INV5, and the phases of the symmetrical carrier 1 and the symmetrical carrier 2 are reversed, i.e. the phase difference is half a clock cycle; the output of the DFF1 passes through a delay unit, an inverter INV1, a NOR gate NOR1, an inverter INV2, and a NAND gate NAND1, generating an asymmetric carrier 1; the output of the flip-flop DFF2 passes through a delay unit, inverter INV3, NOR gate NOR2, inverter INV4, NAND gate NAND2, generating asymmetric carrier 2.
The symmetrical carrier 1, the symmetrical carrier 2, the asymmetrical carrier 1 and the asymmetrical carrier 2 are input into the multiplexer. The multiplexer outputs the symmetric carrier 1 and the symmetric carrier 2 when the input signal is high level, and outputs the asymmetric carrier 1 and the asymmetric carrier 2 when the input signal is low level. The delay time of the delay unit determines the duty ratio of the asymmetric carrier, and in order to ensure that the demodulation circuit can correctly demodulate an input signal, the duty ratio of the asymmetric carrier cannot be too large, and the simulation verification cannot exceed 15%. The voltage waveform diagram of each node of the modulation circuit is shown in fig. 6.
FIG. 4 shows an embodiment of a voltage controlled oscillator, which is used to provide a high frequency pulse signal for a carrier signal, and comprises an amplifier, a RING oscillator (RING OSC), a frequency-to-voltage line (F to V), a level SHIFT line (L EVE L SHIFT), an inverter INV6, and an inverter INV 7. the operation principle is that the amplifier, the RING oscillator (RING OSC), and the frequency-to-voltage line (F to V) form a negative feedback loop structure, the RING oscillator power voltage is adjusted through the output (point A) of the amplifier, the RING oscillator power voltage is high if the power voltage is high, the RING oscillator power frequency is low if the power voltage is low, the resistor R1, the MOS transistor P1, the resistor R3, and the capacitor C1 form a frequency-to-voltage line, the MOS transistor P4 and the capacitor C1 form a switched capacitor circuit, the capacitor C1 is equivalent to a variable resistor whose resistance varies with the frequency, that the resistor R1, R638, the capacitor C1, and the capacitor C6326, the inverter, the output voltage is variable with the frequency of the RING oscillator signal, and the output of the inverter NV 9 is variable with the frequency of the frequency voltage divider INV 9, and the output of the inverter 369 is variable resistor and the output voltage is variable with the frequency of the high frequency SHIFT.
The isolation medium is composed of a high-voltage capacitor, and has the advantages of easy realization in process, high matching degree, small area, reduced cost and improved product competitiveness.
The output circuit comprises a high-pass filter (HPF), a low-gain amplifier, a low-pass filter (L PF), a carrier to voltage circuit, a comparator, a driving circuit and a second bias circuit for providing bias voltage and bias current for the whole output circuit, wherein a demodulation circuit is formed by the high-voltage isolation capacitor, the filter and low-gain amplifier, the low-pass filter (L PF), the carrier to voltage circuit and the comparator together.
The overall structure of the demodulation circuit is shown in fig. 5, the demodulation circuit comprises a high-pass filter, a low-gain amplifier, a low-pass filter, a carrier voltage-converting circuit and a comparator, wherein a high-voltage isolation capacitor and a resistor Ra form a first-stage high-pass filter (HPF), a low-voltage capacitor C and a resistor R form a second-stage high-pass filter, the two-stage filters filter low-frequency interference of modulation signals, and high-frequency modulation signals.
When the modulation signal is an asymmetric carrier, because the duty ratio of the asymmetric carrier is small, when the asymmetric carrier passes through a multi-stage high-pass filter and then passes through a low-gain amplifier, the influence of the high-level part of the asymmetric carrier can be ignored, the amplitudes of the voltage signals before and after the low-pass filter (L PF) are basically consistent, namely the amplitudes of the voltage signals at points A1, A2, B1 and B2 are basically equal, the source voltages of the corresponding points N1, N2, N3 and N4 are equal, but due to the existence of hysteresis voltage I1 × Roffset, the voltage at the point OUT2 is higher than the voltage at the point OUT1, and the OUT1 and OUT2 are respectively connected with the positive input end (INP) and the negative input end (INN) of the comparator, in this case, the output of the comparator is low level.
Compared with the conventional 2FSK modulation, the symmetrical and asymmetrical isolated drive signal transmission circuit has lower requirement on a carrier signal, does not influence the modulation and demodulation of the drive signal when the carrier frequency and the asymmetrical fluctuation are not large, reduces the difficulty of circuit design and improves the robustness of a product.
In addition, in a demodulation circuit of an output circuit, a low-gain amplifier is directly adopted behind a high-pass filter instead of a comparator, so that the change of a signal rail to rail is avoided, the amplitude of an output signal is smaller compared with a rail to rail signal, the rising edge time and the falling edge time of the output signal are reduced to a great extent, and the efficiency is greatly improved when a power device is driven.
The above description is only a preferred embodiment of the present invention, and therefore should not be taken as limiting the scope of the invention, which is defined by the appended claims and their equivalents.
Claims (10)
1. A symmetric and asymmetric isolated drive signal transmission circuit, comprising: an input line, an isolator and an output line; the isolator isolates the power supply and the ground of the output circuit from the power supply and the ground of the output circuit;
the input line generates a symmetrical or asymmetrical modulation signal to an isolation medium after voltage-to-carrier modulation according to the level condition of an input signal;
the output line receives the modulated signal passing through the isolation medium, and generates an output signal after carrier-to-voltage demodulation.
2. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 1, wherein: when the modulation signal is a symmetrical carrier signal, an output signal generated after carrier voltage conversion demodulation is a high level;
when the modulation signal is an asymmetric carrier signal, an output signal generated after carrier voltage conversion demodulation is at a low level.
3. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 1, wherein: the waveform of the output signal is the same as that of the input signal and has a certain time delay.
4. A symmetric and asymmetric isolated drive signal transmission circuit according to any of claims 1-3, characterized in that: the demodulation circuit comprises a high-pass filter, a low-gain amplifier, a low-pass filter, a carrier voltage conversion circuit and a comparator;
the output end of the high-pass filter is connected with the input end of the low-gain amplifier; the output end of the low gain amplifier is connected to the comparator after passing through the low pass filter and the carrier voltage conversion circuit.
5. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 4, wherein: the modulation circuit comprises a voltage-controlled oscillator, a logic processing circuit, a multiplexer and a first bias circuit; the first bias circuit provides bias voltage and bias current for the voltage-controlled vibrator, the logic processing circuit and the multiplexer.
6. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 5, wherein: the logic processing circuit comprises a trigger DFF1 and a trigger DFF 2; high-frequency oscillation signals generated by the voltage-controlled oscillator generate frequency division signals with phases different by half clock period through a trigger DFF1 and a trigger DFF2 respectively;
the symmetrical carrier 1 output by the trigger DFF1 generates a symmetrical carrier 2 and an asymmetrical carrier 1 through a logic processing circuit, wherein the symmetrical carrier 2 and the symmetrical carrier 1 have opposite phases; the carrier signal output by the trigger DFF2 generates an asymmetric carrier 2 through a logic processing circuit;
and the symmetrical carrier 1, the symmetrical carrier 2, the asymmetrical carrier 1 and the asymmetrical carrier 2 are respectively input into a multiplexer.
7. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 6, wherein: the flip-flop DFF1 is triggered by rising edge, and the flip-flop DFF2 is triggered by falling edge.
8. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 7, wherein: the symmetrical carrier passes through a first delay unit, an inverter INV1, a NOR gate NOR1, an inverter INV2 and a NAND gate NAND1 to generate an asymmetrical carrier 1; the frequency-divided signal output by the flip-flop DFF2 passes through the second delay unit, the inverter INV3, the NOR gate NOR2, the inverter INV4, and the NAND gate NAND2, and generates the asymmetric carrier 2.
9. The symmetric and asymmetric isolated drive signal transmission circuit according to claim 8, wherein: the duty ratio of the asymmetrical carrier 1 and the asymmetrical carrier 2 is determined by the delay time of the first delay unit and the second delay unit to be not more than 15%.
10. A symmetrical and asymmetrical isolated drive signal transmission circuit according to any one of claims 7 to 9 wherein: the multiplexer outputs a symmetric carrier 1 and a symmetric carrier 2 when the input signal is high level, and outputs an asymmetric carrier 1 and an asymmetric carrier 2 when the input signal is low level.
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| CN202010312155.4A CN111464176A (en) | 2020-04-20 | 2020-04-20 | Symmetrical and asymmetrical isolated drive signal transmission circuit |
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| CN202010312155.4A CN111464176A (en) | 2020-04-20 | 2020-04-20 | Symmetrical and asymmetrical isolated drive signal transmission circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113810068A (en) * | 2021-09-07 | 2021-12-17 | 杭州电子科技大学 | AIS-MOB radio frequency signal generating circuit |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113810068A (en) * | 2021-09-07 | 2021-12-17 | 杭州电子科技大学 | AIS-MOB radio frequency signal generating circuit |
| CN113810068B (en) * | 2021-09-07 | 2022-09-30 | 杭州电子科技大学 | AIS-MOB radio frequency signal generating circuit |
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