CN211930655U

CN211930655U - CAN bus interface circuit for traffic radar

Info

Publication number: CN211930655U
Application number: CN202020886161.6U
Authority: CN
Inventors: 王一民
Original assignee: Nanjing Hurys Intelligent Technology Co Ltd
Current assignee: Nanjing Hurys Intelligent Technology Co Ltd
Priority date: 2020-05-25
Filing date: 2020-05-25
Publication date: 2020-11-13
Anticipated expiration: 2030-05-25

Abstract

The utility model discloses a CAN bus interface circuit for traffic radar, the first pin of CAN bus terminal interface is connected with the CANL pin of high-speed CAN transceiver, and the second pin of CAN bus terminal interface is connected with the CANH pin of high-speed CAN transceiver; the TXD pin of the high-speed CAN transceiver is connected with the TXDAN pin of the CAN controller through a resistor R92; the RXD pin of the high-speed CAN transceiver is connected with the RXDAN pin of the CAN controller through a resistor R93; and a CS pin, an SCK pin, an SI pin and an SO pin of the CAN controller are respectively connected with a synchronous serial line of the singlechip and are used for synchronous serial communication. The utility model discloses the interference killing feature is strong, and protection bus ability is strong, has reduced radio frequency interference, has improved transmission rate.

Description

CAN bus interface circuit for traffic radar

Technical Field

The utility model relates to a CAN bus interface circuit for traffic radar belongs to the transmission technology field of millimeter wave radar sensor data.

Background

At present, with the continuous improvement of the technical requirements of the traffic radar on data volume and communication speed, although the transmission distance of the traditional RS485 bus is longer than that of the RS232 bus, the traditional RS485 bus can replace a field bus to be used as a data transmission bus in a simple field sometimes.

However, the RS485 bus does not have a complete data link layer protocol, only the transmission level form of the bus is defined, the interface form determines that the active multi-host operation cannot be completed, and the data transmission protocol needs to be defined by itself, which is inconvenient for communication system designers to design.

Therefore, the traffic radar also prevents the following problems while satisfying the data volume and the communication speed:

1. bus impedance matching;

the CAN bus impedance matching plays an important role and cannot be omitted. Otherwise, the reliability and the anti-interference performance of the bus data communication are greatly reduced, and even the communication cannot be realized.

2. Electromagnetic interference is reduced.

3. And (4) power supply isolation.

4. A pull-up resistor.

The above problems are urgently needed to be solved by the technical personnel in the field.

SUMMERY OF THE UTILITY MODEL

The purpose is as follows: in order to overcome the deficiencies in the prior art, the utility model provides a CAN bus interface circuit for traffic radar.

The technical scheme is as follows: in order to solve the technical problem, the utility model discloses a technical scheme does:

a CAN bus interface circuit for a traffic radar, comprising: CAN bus terminal interface, high-speed CAN transceiver, CAN controller, its characterized in that: a first pin of the CAN bus terminal interface is connected with a CANL pin of the high-speed CAN transceiver, a second pin of the CAN bus terminal interface is connected with a CANH pin of the high-speed CAN transceiver, an STB pin of the high-speed CAN transceiver is grounded through a resistor R91, and a SPLIT/Vio pin of the high-speed CAN transceiver is respectively connected with the CANL pin and the CANH pin of the high-speed CAN transceiver through a resistor R94 and a resistor R95 which are connected in parallel; the Vcc pin of the high-speed CAN transceiver is connected with a working power supply; the TXD pin of the high-speed CAN transceiver is connected with the TXDAN pin of the CAN controller through a resistor R92; the RXD pin of the high-speed CAN transceiver is connected with the RXDAN pin of the CAN controller through a resistor R93; the GND pin of the high-speed CAN transceiver is grounded; and a CS pin, an SCK pin, an SI pin and an SO pin of the CAN controller are respectively connected with a synchronous serial line of the singlechip and are used for synchronous serial communication.

Preferably, the high-speed CAN transceiver CANL pin and CANH pin are respectively connected in parallel with capacitors C71 and C72.

Preferably, the common connection point of the resistor R94 and the resistor R95 is connected in series with the capacitor C74 and then grounded.

Preferably, the TXCAN pin of the CAN controller is connected in parallel with a series circuit consisting of a working voltage, a pull-up resistor R42 and a light emitting diode D13.

Preferably, an RXCAN pin of the CAN controller is connected in parallel with a series circuit composed of a working voltage, a pull-up resistor R43 and a light emitting diode D14.

Preferably, the high-speed CAN transceiver is in a model of TJA 1042T.

Preferably, the model of the CAN controller adopts MCP 2515.

Preferably, a diode is connected in parallel between the CANL pin and the CANH pin of the high-speed CAN transceiver.

Has the advantages that: the utility model provides a pair of a CAN bus interface circuit for traffic radar, the interference killing feature is strong, and protection bus ability is strong, has reduced radio frequency interference, has improved transmission rate.

Drawings

Fig. 1 is a schematic structural view of the present invention;

FIG. 2 is a waveform diagram of the transceiver circuit test of the present circuit;

FIG. 3 is a waveform diagram of the circuit for receiving hysteresis test.

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

As shown in fig. 1, a CAN bus interface circuit for a traffic radar includes: the CAN bus terminal interface comprises a CAN bus terminal interface, a high-speed CAN transceiver and a CAN controller, wherein a first pin of the CAN bus terminal interface is connected with a CANL pin of the high-speed CAN transceiver, a second pin of the CAN bus terminal interface is connected with a CANH pin of the high-speed CAN transceiver, an STB pin of the high-speed CAN transceiver is grounded through a resistor R91, and an SPLIT/Vio pin of the high-speed CAN transceiver is respectively connected with the CANL pin and the CANH pin of the high-speed CAN transceiver through a resistor R94 and a resistor R95 which are connected in parallel; the Vcc pin of the high-speed CAN transceiver is connected with a working power supply; the TXD pin of the high-speed CAN transceiver is connected with the TXDAN pin of the CAN controller through a resistor R92; the RXD pin of the high-speed CAN transceiver is connected with the RXDAN pin of the CAN controller through a resistor R93; the GND pin of the high-speed CAN transceiver is grounded; and a CS pin, an SCK pin, an SI pin and an SO pin of the CAN controller are respectively connected with a synchronous serial line of the singlechip and are used for synchronous serial communication.

And the high-speed CAN transceiver CANL pin and the CANH pin are respectively connected with capacitors C71 and C72 in parallel.

The common connection point of the resistor R94 and the resistor R95 is connected in series with the capacitor C74 and then grounded.

And a TXCAN pin of the CAN controller is connected in parallel with a series circuit consisting of a working voltage, a pull-up resistor R42 and a light-emitting diode D13.

The RXCAN pin of the CAN controller is connected in parallel with a series circuit consisting of a working voltage, a pull-up resistor R43 and a light-emitting diode D14.

The model of the high-speed CAN transceiver adopts TJA 1042T.

The model of the CAN controller adopts MCP 2515.

Example 1:

the high-speed CAN transceiver provides an interface between a Controller Area Network (CAN) protocol controller and a physical two-wire CAN bus using TJA 1042T. Designed for high-speed CAN applications in the automotive industry, it provides differential transceiving capability with CAN protocol controllers.

The CAN controller adopts MCP2515 which is an independent CAN controller, and CAN simplify the application required to be connected with a CAN bus. The MCP2515 supports the standard data frame, extended data frame, and remote frame (standard and extended) defined in the can2.0b specification.

Example 2:

the utility model discloses the during operation, CAN controller MCP2515 uses as resetting, monitoring circuit, though increased circuit connection's complicacy and cost, has played very big effect to the stability and the reliability of circuit, is the indispensable part in the system. The operation of the MCP2515 is accomplished by synchronous serial communication over 4 serial lines CS, SCK, SI, and SO.

The SCK pin is used for an externally input synchronous clock signal. When modifying instructions or data for a chip, the clock leading edge inputs an SI pin signal; when reading data, a clock trailing edge outputs a data bit onto the SO pin. The data input/output is high order first. In the design, a CS pin is connected with the singlechip, and a pin SI, a pin SCK, a pin SO and a pin RST are respectively connected with related pins of the singlechip. And for the pins which are not used, the pins can be directly suspended and disconnected.

Example 3:

TJA1042T is used as a high-speed CAN transceiver, and a chip MCP2515 is used as a CAN controller monitoring and resetting circuit. In actual work, the following benefits are brought;

the interrupt request signal INT of the MCP2515 is transited to low level from high level when the interrupt is allowed and the interrupt occurs, so that the pin INT is directly connected with INT0 of the single chip microcomputer. The chip selection signal CS is connected with the I/O pin of the single chip microcomputer, when the CS is connected with a low level, the MCP2515 is selected, and the single chip microcomputer can read/write the MCP 2515. In order to enhance the anti-interference capability of the CAN bus node. The potential pulled up by the TXCAN pin and the RXCAN pin of the MCP2515 must be maintained at about 3.3V, otherwise the level logic required by the CAN protocol will not be formed.

2, a TXCAN pin and an RXCAN pin of the MCP2515 are directly connected with a TXD pin and an RXD pin of the TJA1042T, so that the stability and the safety of the node are improved, and the normal work of the high-speed CAN transceiver is protected.

3. The different working frequencies of the singlechip and the MCP2515 bring troubles to the design. Therefore, in the design, the clock signal of the CLOCKOUT of the MCP2515 is connected with the 8M crystal for clock input, so that the clock problem is solved.

4. In addition, a protection diode CAN be connected between the two CAN bus access ends and the ground. When the CAN bus has higher negative voltage, a certain overvoltage protection function CAN be realized through the short circuit of the diode, and a slope resistor is connected to the STB pin of the TJA 1042T. The size of the resistor can be properly adjusted to be generally between 16 and 140K omega according to the communication speed of the bus.

Example 4:

the CAN bus terminal interface is subjected to a transceiver circuit test, and the level characteristic of the bus driving of the transmitter circuit and the function of the receiver circuit (hysteresis comparator) are mainly verified. The sending circuit adopts a signal generator to excite the square wave of the circuit, the levels of CANH and CANL on a square wave frequency test bus are adjusted, and the test results of the sending circuit working at 1 Mbps and 2Mbps are shown in figure 2. CANH and CANL dominant state levels are 3.5V and 1.5V, respectively, and recessive state levels are both 2.5V. The highest working speed of the actual test result sending circuit can reach 2 Mbps.

Example 5:

the CAN bus terminal interface is subjected to a receiving hysteresis characteristic test, a receiving comparator also adopts a signal generator to excite the circuit, in order to detect a triangular wave with 2.5V of input level of a CANL end and 2.5-3.5V of input level of a CANH end, the test result is shown in figure 3, the hysteresis comparator changes states when CANH is 3.4V and 3.0V, namely, the hysteresis comparator receives dominant level when CANH-CANL >0.9V and receives recessive level when CANH-CANL < 0.5V.

In conclusion, the CAN receiving circuit using the design does not influence the receiving of CAN data, simultaneously ensures that the transmission rate of a CAN channel is equal to the receiving rate of a normal CAN interface circuit, not only improves the stability, but also does not influence the data transmission.

The above description is only a preferred embodiment of the present invention, and it should be noted that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A CAN bus interface circuit for a traffic radar, comprising: CAN bus terminal interface, high-speed CAN transceiver, CAN controller, its characterized in that: a first pin of the CAN bus terminal interface is connected with a CANL pin of the high-speed CAN transceiver, a second pin of the CAN bus terminal interface is connected with a CANH pin of the high-speed CAN transceiver, an STB pin of the high-speed CAN transceiver is grounded through a resistor R91, and a SPLIT/Vio pin of the high-speed CAN transceiver is respectively connected with the CANL pin and the CANH pin of the high-speed CAN transceiver through a resistor R94 and a resistor R95 which are connected in parallel; the Vcc pin of the high-speed CAN transceiver is connected with a working power supply; the TXD pin of the high-speed CAN transceiver is connected with the TXDAN pin of the CAN controller through a resistor R92; the RXD pin of the high-speed CAN transceiver is connected with the RXDAN pin of the CAN controller through a resistor R93; the GND pin of the high-speed CAN transceiver is grounded; and a CS pin, an SCK pin, an SI pin and an SO pin of the CAN controller are respectively connected with a synchronous serial line of the singlechip and are used for synchronous serial communication.

2. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: and the high-speed CAN transceiver CANL pin and the CANH pin are respectively connected with capacitors C71 and C72 in parallel.

3. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: the common connection point of the resistor R94 and the resistor R95 is connected in series with the capacitor C74 and then grounded.

4. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: and a TXCAN pin of the CAN controller is connected in parallel with a series circuit consisting of a working voltage, a pull-up resistor R42 and a light-emitting diode D13.

5. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: the RXCAN pin of the CAN controller is connected in parallel with a series circuit consisting of a working voltage, a pull-up resistor R43 and a light-emitting diode D14.

6. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: the model of the high-speed CAN transceiver adopts TJA 1042T.

7. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: the model of the CAN controller adopts MCP 2515.

8. The CAN bus interface circuit for a traffic radar according to claim 1, wherein: and a diode is connected in parallel between the CANL pin and the CANH pin of the high-speed CAN transceiver.