CN211908768U

CN211908768U - High-speed clock data recovery circuit

Info

Publication number: CN211908768U
Application number: CN202020390413.6U
Authority: CN
Inventors: 尹项托; 龚胜民
Original assignee: Zhongxing Lianhua Technology Beijing Co ltd
Current assignee: Zhongxing Lianhua Technology Beijing Co ltd
Priority date: 2020-03-24
Filing date: 2020-03-24
Publication date: 2020-11-10
Anticipated expiration: 2030-03-24

Abstract

The embodiment of the utility model discloses a high-speed clock data recovery circuit, which comprises a phase discriminator, at least two voltage-controlled oscillators and a DDS signal generator; the output end of the phase discriminator is connected with the input end of each voltage-controlled oscillator; the output end of each voltage-controlled oscillator is connected with the input end of the DDS signal generator. Adopt the utility model discloses can realize the recovery of high rate clock data, improve the clock signal quality who resumes to can realize wide frequency and cover.

Description

High-speed clock data recovery circuit

Technical Field

The utility model relates to an integrated circuit design field, concretely relates to high-speed clock data recovery circuit.

Background

With the continuous development of network communication technology, the transmission distance and transmission speed of the backbone network are also continuously improved. To ensure efficient transmission of network data, it becomes important how to recover clock signals and data signals.

At present, Recovery of the Clock signal and the Data signal is performed by using a CDR (Clock and Data Recovery) circuit. Specifically, the CDR circuit includes two parts, namely a Clock Recovery (CR) circuit and a Data Recovery (DR) circuit, and the DR circuit may be further divided into a Clock Data phase adjustment (phase alignment) circuit and a Data sampling decision circuit. In the case of long-distance high-speed communication, since an optical signal is greatly attenuated during transmission, data can be regenerated by the CDR circuits in the data regenerators of the respective stages that have passed through during signal transmission, thereby recovering the clock signal and the data signal. Thus, the phase jitter of the network signal is amplified after regeneration through the CDR circuit. Therefore, a high-speed clock data recovery circuit with large bandwidth and low jitter is needed.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a high-speed clock data recovery circuit, including phase discriminator, two at least voltage controlled oscillators, DDS signal generator;

the output end of the phase discriminator is connected with the input end of each voltage-controlled oscillator;

the output end of each voltage-controlled oscillator is connected with the input end of the DDS signal generator.

Optionally, the high-speed clock data recovery circuit further includes an analog switch;

the output end of the phase discriminator is connected with the input end of the analog switch, and the output end of the analog switch is connected with the input end of each voltage-controlled oscillator.

Optionally, the high-speed clock data recovery circuit further includes a radio frequency switch;

the output end of each voltage-controlled oscillator is connected with the input end of the radio frequency switch, and the output end of the radio frequency switch is connected with the input end of the DDS signal generator.

Optionally, the high-speed clock data recovery circuit further includes an adjustable low-pass filter unit; the adjustable low-pass filtering unit comprises a digital potentiometer and an active loop;

the input end of the digital potentiometer is connected with the input end of the active loop in parallel; and the output end of the digital potentiometer is connected with the output end of the active loop in parallel.

Optionally, the active loop includes an adjustable resistor and a capacitor.

Optionally, the high-speed clock data recovery circuit further includes a decision circuit;

and the output end of the radio frequency switch is connected with the input end of the judgment circuit.

According to the above technical scheme, the embodiment of the utility model provides a through connecting into high-speed clock recovery circuit by phase discriminator, two at least voltage controlled oscillator and DDS signal generator. Therefore, the DDS signal generator can realize high-resolution frequency stepping, fractional frequency division and stray output reduction, thereby realizing the recovery of high-speed clock data and improving the quality of recovered clock signals. Meanwhile, wide frequency coverage can be realized by adopting a plurality of voltage-controlled oscillators.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a high-speed clock recovery circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an adjustable low-pass filtering unit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an active circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a high-speed clock recovery circuit according to an embodiment of the present invention.

Detailed Description

The following describes the present invention with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

Fig. 1 shows a schematic structural diagram of a high-speed clock recovery circuit provided in this embodiment, including: the phase detector comprises a phase detector 1, at least two voltage-controlled oscillators 2 and a DDS signal generator 3.

Compared with a single voltage-controlled oscillator, the frequency coverage can be improved by adopting at least two voltage-controlled oscillators 2, namely a plurality of voltage-controlled oscillators 2, and wide frequency coverage is realized.

The output end of the phase discriminator 1 is connected with the input end of each voltage-controlled oscillator 2;

the output terminal of each voltage-controlled oscillator 2 is connected to the input terminal of the DDS signal generator 3. Fractional frequency division can be realized by adopting the DDS signal generator 3, thereby reducing stray output, improving signal quality and realizing high-resolution frequency stepping.

Further, the high-speed clock data recovery circuit further comprises an analog switch 4; the analog switch 4 may be a low impedance switch to reduce the impact on the active loop.

The output end of the phase discriminator 1 is connected with the input end of the analog switch 4, and the output end of the analog switch 4 is connected with the input end of each voltage-controlled oscillator 2.

Further, the high-speed clock data recovery circuit further comprises a radio frequency switch 5; the radio frequency switch 5 can realize high isolation among the voltage-controlled oscillators 2 and prevent mutual crosstalk among the voltage-controlled oscillators 2.

The output end of each voltage-controlled oscillator 2 is connected with the input end of the radio frequency switch 5, and the output end of the radio frequency switch 5 is connected with the input end of the DDS signal generator 3.

Further, the high-speed clock data recovery circuit further comprises an adjustable low-pass filtering unit 6. Referring to fig. 2, the adjustable low-pass filtering unit includes a digital potentiometer 601 and an active loop 602; the input of the digital potentiometer 601 is connected in parallel with the input of the active loop 602; the output of the digital potentiometer 601 is connected in parallel with the output of the active loop 602. By using the digital potentiometer 601 and the active loop 602, a bandwidth-adjustable low-pass filter, that is, an adjustable low-pass filter, can be realized, and a loop bandwidth adjusting function is realized, and the loop bandwidth is a cut-off frequency of the adjustable low-pass filter.

Further, referring to fig. 3, the active loop 602 includes an adjustable resistor 6011 and a capacitor 6012.

Further, the high-speed clock data recovery circuit further comprises a decision circuit 7;

the output end of the radio frequency switch 5 is connected with the input end of the decision circuit 7.

Referring to fig. 4, fig. 4 illustrates a schematic diagram of a high speed clock recovery circuit, which is provided by the present invention, taking 3 voltage controlled oscillators as an example. And it is right based on a high speed clock recovery circuit that figure 4 shows the utility model provides a high speed clock recovery circuit's concrete work flow explains, and is concrete: first, each VCO (voltage-controlled oscillator) may generate a periodic signal, and each VCO may compare the generated periodic signal with a reference signal. For each VCO, if the frequency of the periodic signal is different from the frequency of the reference signal, the aforementioned periodic signal may be delivered to the DDS signal generator via the radio frequency switch. The DDS signal generator is used for carrying out decimal frequency division processing on the periodic signal, the frequency stability and accuracy of the VCO are improved to the level the same as the frequency of the reference signal, and the adjusted signal is input into the phase discriminator. Then, the phase detector can adjust the voltage of the VOC to make the frequency of the VOC newly output periodic signal closer to the frequency of the reference signal according to the received adjusted signal. Before the phase discriminator adjusts the voltage of VOC, the output of the phase discriminator can be smoothed through the adjustable low-pass filtering unit, so that the system can tend to be stable when the phase discriminator performs small adjustment. Meanwhile, the analog switch arranged between the adjustable low-pass filtering unit and the VOC can reduce the influence of the VOC on the active loop, and further keep the system stable.

It should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A high-speed clock data recovery circuit is characterized by comprising a phase discriminator, at least two voltage-controlled oscillators and a DDS signal generator;

2. The high speed clock data recovery circuit of claim 1, further comprising an analog switch;

3. The high speed clock data recovery circuit of claim 1, wherein the high speed clock data recovery circuit further comprises a radio frequency switch;

4. The high-speed clock data recovery circuit of claim 1, further comprising an adjustable low-pass filtering unit; the adjustable low-pass filtering unit comprises a digital potentiometer and an active loop;

5. The high speed clock data recovery circuit of claim 4 wherein the active loop comprises an adjustable resistance and a capacitance.

6. The high speed clock data recovery circuit of claim 3, further comprising a decision circuit;