CN211906262U

CN211906262U - Memory test structure of mainboard

Info

Publication number: CN211906262U
Application number: CN202020452550.8U
Authority: CN
Inventors: 林正隆; 梁万栋
Original assignee: Senfu Technology Co ltd
Current assignee: EOREX CORP; Senfu Technology Co ltd
Priority date: 2020-04-01
Filing date: 2020-04-01
Publication date: 2020-11-10
Anticipated expiration: 2030-04-01

Abstract

A memory test structure of a mainboard comprises a test board body, a plurality of mainboard components and a test mechanism, wherein each mainboard component comprises a mainboard, a Central Processing Unit (CPU), a memory and a plurality of memory modules (DUTs) to be tested. Therefore, the problem that the speed measurement is limited due to the distance of the computer (PC) in the traditional mainboard test mode can be solved, the memory module to be tested is arranged on the back of the central processing unit in the creation, so that the distance between the central processing unit and the memory module to be tested is shortest, the specially-made mainboard can be effectively reduced, the test speed can achieve the highest test speed, the test area of the test mechanism in the working area can be tested by adopting the unit maximum detection quantity, the limit of the test area and the test speed is effectively broken through, the test efficiency and the test quantity are improved, and the frequency is higher.

Description

Memory test structure of mainboard

Technical Field

The utility model relates to a memory test structure of mainboard especially relates to a test structure who establishes the memory module that awaits measuring at the central processing unit back, especially indicates that test speed can reach the test at the highest speed to make the test mechanism can adopt the unit maximum detection quantity to test in the test area of work area the inside, effectively break through the restriction of test area and test speed, improve efficiency of software testing and quantity, thereby make the higher test structure of frequency.

Background

In the past, when a Dynamic Random Access Memory (DRAM) chip is tested on a computer Motherboard (PC Motherboard), the DRAM chip is implemented by using an existing product, in which a DRAM of a Device Under Test (DUT) and a Central Processing Unit (CPU) are disposed on the same side of the Motherboard, but the measurement speed is slow due to a large offset caused by a long line, so the Motherboard testing mode is limited by a bottleneck of speed, so that the execution speed is very slow, and the efficiency is very poor.

Because the conventional method has limited speed measurement due to the distance between the computers (PCs) and the computer, the conventional method cannot detect the over-frequency memories at all, and cannot efficiently know which memories have enough margin to exceed the performance range specified in the specification. Therefore, it is generally not suitable for the actual use of the user.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a main aim at, overcome the above-mentioned problem that the known art met, and provide the memory test structure of mainboard, the memory module that will await measuring is established at the central processing unit back, therefore central processing unit is just shortest with the memory module that awaits measuring, make this specially-made mainboard can effectively reduce, test speed just can reach the test of fast speed, and make the test area of accredited testing organization in the work area the inside can adopt the biggest detection quantity of unit to test, effectively break through the restriction of test area and test speed, improve efficiency of software testing and quantity, thereby make the frequency higher.

In order to achieve the above purpose, the utility model adopts the technical scheme that: a memory test structure of a mainboard comprises a test board body, a plurality of mainboard components and a test mechanism; the mainboard assembly is arranged on the test board body and comprises a mainboard, a central processing unit, a memory and a plurality of memory modules to be tested; the mainboard comprises a first surface and a second surface opposite to the first surface; the testing mechanism is connected with the testing plate body and used for screening each memory module to be tested of the mainboard assembly on the testing plate body; the method is characterized in that: the mainboard is horizontally arranged on the test board body, the second surface is arranged above the mainboard, and the first surface is arranged below the mainboard; the central processing unit is arranged on the first surface of the mainboard and is electrically connected to the mainboard; the memory is arranged on the first surface of the mainboard and is electrically connected to the mainboard and the central processing unit; the memory modules to be tested are arranged on the second surface of the mainboard and electrically connected to the mainboard and the central processing unit. By the components, when testing is carried out, each memory module to be tested on each mainboard is placed on the back of the central processing unit, the shortest distance is reserved between the central processing unit on each mainboard and each memory module to be tested, so that high-speed testing can be carried out, the testing mechanism is processed by using an optimization program to achieve optimized space utilization efficiency, the testing area of the testing mechanism in a working area can be tested by adopting the unit maximum detection quantity, and the limitation of the testing area and the testing speed is broken through.

In the above embodiments of the present invention, each of the memory modules to be tested may be a Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) chip.

In the above embodiments of the present invention, the testing mechanism is a robot (robot).

In the above embodiments of the present invention, the testing mechanism is provided with testing parameters, and the testing mechanism performs a screening process on each memory module to be tested according to the testing parameters.

In the above embodiments of the present invention, the test parameter is set according to the memory module that the user wants to screen out the specific speed, and the test parameter needs to be higher than the specific speed that is to be screened out.

Drawings

Fig. 1 is a general schematic diagram of the memory test structure of the motherboard of the present invention.

Fig. 2 is a schematic diagram of the main board assembly of the present invention.

Reference numbers refer to:

memory test structure 100 of mainboard

Test board body 1

Mainboard assembly 2

Main board 21

First side 211

Second side 212

Central processing unit 22

Memory 23

Memory module 24 to be tested

A testing mechanism 3.

Detailed Description

Please refer to fig. 1 and fig. 2, which are a schematic diagram of the whole memory testing structure of the main board and a schematic diagram of the main board assembly of the present invention, respectively. As shown in the figure: the utility model relates to a memory test structure 100 of mainboard, it includes that test plate body 1, several mainboard subassembly 2 and accredited testing organization 3 constitute. Of course, the memory test structure 100 of the motherboard may include a plurality of test boards 1, so that the test throughput can be increased. In the following, only the internal structure of a single test board 1 will be described.

The above-mentioned plurality of motherboard assemblies 2 are disposed on the test board 1. Each of the motherboard assemblies 2 includes a motherboard 21, a Central Processing Unit (CPU) 22, a memory 23, and a plurality of Device Under Test (DUT) modules 24. The main board 21 includes a first surface 211 and a second surface 212 opposite to the first surface 211, and the main board 21 is horizontally disposed on the test board 1 in a manner that the second surface 212 is on top and the first surface 211 is on bottom. The cpu 22 is disposed on the first surface 211 of the motherboard 21 and electrically connected to the motherboard 21. The memory 23 is disposed on the first surface 211 of the motherboard 21 and electrically connected to the motherboard 21 and the cpu 22. Each of the memory modules 24 to be tested is mounted on the second surface 212 of the motherboard 21 and electrically connected to the motherboard 21 and the cpu 22. Each of the memory modules 24 to be tested may be a Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) chip, which is a DRAM IC chip 1 to a DRAM IC chip N. In this way, the test can be performed using the customized motherboard 21.

The testing mechanism 3 is connected to the testing board 1 for screening each memory module 24 to be tested on the motherboard 21 of each motherboard component 2 on the testing board 1. Thus, the device disclosed above constitutes a completely new memory test structure 100 of the motherboard.

In one embodiment, the testing mechanism 3 provided by the present invention may be a robot (robot), a testing parameter is set in the testing mechanism 3, the testing mechanism 3 performs screening on each memory module 24 to be tested according to the testing parameter, the testing parameter may be set according to what speed the user wants to screen out, the testing parameter needs to be higher than the specific speed to be screened out, that is, the actual use may be slightly worse, the present invention sets the condition with the best signal, and the margin (margin) is added to determine that the testing parameter is not good enough when the testing mechanism is actually used. Assuming that the speed of the memory module to be screened is higher than 4000MHz, the set test parameters need to be higher than the speed to be screened, for example 4200MHz, so as to screen the memory module with a specific speed.

The memory test structure 100 of the motherboard formed by the above components can make each memory module 24 to be tested on each motherboard 21 be placed on the back of the cpu 22 when the actual test is performed, and the shortest path distance is provided between the cpu 22 on each motherboard 21 and each memory module 24 to be tested, so that the high-speed test can be performed, and the test mechanism 3 is processed by using an optimization program to achieve the optimized space utilization efficiency, so that the test area of the test mechanism 3 in the working area can be tested by adopting the maximum detection number per unit, thereby breaking through the limitations of the test area and the test speed.

The main effect of the creation lies in that the problem that the traditional mainboard test mode has limited speed measurement due to the distance of the computer (PC) in speed is solved, the memory module to be tested is arranged on the back of the central processing unit in the creation, so that the distance between the central processing unit and the memory module to be tested is shortest, the specially-made mainboard can be effectively reduced, the test speed can achieve the highest test speed, the test area of the test mechanism in a working area can be tested by adopting the unit maximum detection quantity, the limitation of the test area and the test speed is effectively broken through, the test efficiency and the test quantity are improved, and the frequency is higher.

To sum up, the utility model discloses a memory test structure of mainboard can effectively improve all kinds of shortcomings of prior art, the memory module that will await measuring is established at the central processing unit back, so central processing unit is just shortest with the distance of the memory module that awaits measuring, make this tailor-made mainboard effectively reduce, test speed just can reach the test of fast speed, and make the test area of accredited testing organization in the work area the inside can adopt the unit maximum detection quantity to test, effectively break through the restriction of test area and test speed, improve efficiency of software testing and quantity, thereby have the feasibility of higher frequency, and then make the utility model discloses can more progress, more practical, more accord with the user and must, the essential that has really accorded with novel patent application, the patent application is proposed according to the law.

However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention should not be limited thereto. Therefore, all the equivalent changes and modifications made in accordance with the claims of the present invention and the contents of the new specification should still fall within the scope covered by the present invention.

Claims

1. A memory test structure of a mainboard comprises a test board body, a plurality of mainboard components and a test mechanism; the mainboard assembly is arranged on the test board body and comprises a mainboard, a central processing unit, a memory and a plurality of memory modules to be tested; the mainboard comprises a first surface and a second surface opposite to the first surface; the testing mechanism is connected with the testing plate body and used for screening each memory module to be tested of the mainboard assembly on the testing plate body; the method is characterized in that:

the mainboard is horizontally arranged on the test board body, the second surface is arranged above the mainboard, and the first surface is arranged below the mainboard; the central processing unit is arranged on the first surface of the mainboard and is electrically connected to the mainboard; the memory is arranged on the first surface of the mainboard and is electrically connected to the mainboard and the central processing unit; the memory modules to be tested are arranged on the second surface of the mainboard and electrically connected to the mainboard and the central processing unit.

2. The main board memory test structure of claim 1, wherein each of the memory modules under test is a dynamic random access memory integrated circuit chip.

3. The main board memory test structure of claim 1, wherein the test mechanism is a robot.

4. The main board memory test structure according to claim 1, wherein the test mechanism has a test parameter, and the test mechanism performs a screening process on each memory module under test according to the test parameter.

5. The main board memory test structure of claim 4, wherein the test parameters are set according to the memory module to be screened out at a specific speed, and the test parameters need to be higher than the specific speed to be screened out.