CN211880321U

CN211880321U - Controllable logic circuit for H-bridge circuit and H-bridge circuit

Info

Publication number: CN211880321U
Application number: CN202020543964.1U
Authority: CN
Inventors: 彭林; 施芸; 杨晓艳; 雷刚
Original assignee: Sichuan Engineering Technical College
Current assignee: Sichuan Engineering Technical College
Priority date: 2020-04-14
Filing date: 2020-04-14
Publication date: 2020-11-06
Anticipated expiration: 2030-04-14

Abstract

The utility model discloses a controllable logic circuit and H bridge circuit for H bridge circuit, controllable logic circuit is provided with three input signal, through microcontroller or dedicated PWM module, the PWM signal of direct current motor speed governing usefulness that generates controls H bridge circuit through logic circuit, can be convenient realization carry out the speed governing control to direct current motor, can realize the positive and reverse output control of H bridge circuit through PWM signal all the way, effectively reduce the demand quantity to PWM signal or module circuit, reduce the microprocessor programming degree of difficulty; the direct short circuit above and below the H bridge is reliably avoided, and the reliable work of the circuit is ensured. Meanwhile, the output of the PWM signal is controlled by the H-bridge control direction control signal DIR or the enable signal EN, and the method can be widely suitable for different types of microcontrollers and types of H-bridge circuits by changing the connection mode of parts in the circuit, and has the characteristics of reliable control logic, convenience, high efficiency, wide application range and reliable function.

Description

Controllable logic circuit for H-bridge circuit and H-bridge circuit

Technical Field

The utility model relates to a circuit design technical field specifically is a controllable logic circuit and H bridge control circuit for H bridge circuit.

Background

The H-bridge circuit is widely applied to the drive control of the direct current motor, but due to the characteristics of the circuit structure, if control signals are not properly processed due to misoperation of designers in the using process, the situation that the upper driving tube and the lower driving tube of a single bridge arm are simultaneously conducted to cause circuit short circuit is easily caused in use. If this occurs, the drive tube in the H-bridge will burn out due to excessive power consumption.

In the control field, due to the programmable characteristic of the microcontroller, the direct current motor speed regulation is widely applied in the motor control field by utilizing the programmable characteristic. The microcontroller generates PWM signals to control the H-bridge circuit, so that the speed of the direct current motor can be conveniently regulated. However, in the application, the aforementioned problem of H-bridge short circuit also needs to be considered, and in addition, in the occasion of needing to perform speed regulation control on a plurality of motors at the same time, the number of the needed PWM signals is often large, which has high requirements on functions and pins of the microcontroller.

Disclosure of Invention

In view of this, the present invention provides a controllable logic circuit and an H-bridge control circuit for an H-bridge circuit, wherein the circuit is characterized in that the forward and backward output control of the H-bridge can be realized by one path of PWM signal, the required number of PWM signals is effectively reduced, and the programming difficulty of the microprocessor is reduced; simultaneously the utility model discloses can also reliably avoid the straight-through short circuit about the H bridge through the control logic of circuit, guarantee the reliable work of circuit.

In order to achieve the purpose, the invention provides the following technical scheme:

the utility model provides a controllable logic circuit for H bridge circuit, including input, first analog switch chip U1A, second analog switch chip U1B, first AND gate U3A and second AND gate U3B;

the input end is provided with three input signals which are an H-bridge output voltage direction control signal DIR, a PWM control signal PWM _ IN and an H-bridge control output enable signal EN respectively;

the PWM control signal PWM _ IN is respectively connected with the A ends of the first analog switch chip U1A and the second analog switch chip U1B;

the H-bridge output voltage direction control signal DIR is connected with the C end of the first analog switch chip U1A, and the H-bridge output voltage direction control signal DIR is reversely connected with the C end of the second analog switch chip U1B through a NOT gate U2A;

the H-bridge control output enable signal EN is connected to the input terminals of the first and gate U3A and the second and gate U3B after the PWM control signal PWM _ IN is blocked by the not gate U2B,

the other input end of the first AND gate U3A is connected with the output end of a first analog switch chip U1A;

the other input end of the second AND gate U3B is connected with the output end of a second analog switch chip U1B;

the output end of the first AND gate U3A is used for controlling a Control + Control end of the H-bridge circuit;

the output of the second and gate U3B is used to Control the Control terminal of the H-bridge circuit.

Further, the H-bridge output voltage direction control signal DIR is externally connected with a pull-up resistor R1, or the PWM control signal PWM _ IN is externally connected with a pull-down resistor R2, or the H-bridge control output enable signal EN is externally connected with a pull-up resistor R3, or the first analog switch chip U1A is externally connected with a pull-down resistor R4; or a pull-down resistor R5 is externally connected to the second analog switch chip U1B.

Further, the first analog switch chip U1A and the second analog switch chip U1B are analog electronic switches CD4066 or and gates.

Further, the controllable logic circuit also comprises a first triode Q1 and a second triode Q2,

the base electrode of the first triode Q1 is connected with the Control + Control end through a resistor R6, and the emitter electrode of the first triode Q1 and the collector electrode of the series resistor R7 are used as the Driver output end of the H-bridge circuit;

the base electrode of the second triode Q2 is connected with the Control-Control end through a resistor R8, and the emitter electrode of the second triode Q2 and the collector electrode of the series resistor R9 are used as the other output end of the Driver of the H-bridge circuit.

Further, the controllable logic circuit also comprises a third triode Q3 and a fourth triode Q4,

the Control + Control end is connected with the base electrode of a third triode Q3 through a resistor R10 after passing through a NOT gate U4A, the collector electrode of the third triode Q3 provides a Driver + Control signal for an H-bridge driving circuit through a resistor R12, the collector electrode of the third triode Q3 is connected with a voltage input signal through a resistor R11, and the emitter electrode of the third triode Q3 is connected with the ground;

the Control-Control end is connected with the base electrode of a fourth triode Q4 through a resistor R13 after passing through a NOT gate U4B, the collector electrode of the fourth triode Q4 provides a Driver-Control signal for the H-bridge driving circuit through a resistor R15, the collector electrode of the fourth triode Q4 is connected with a voltage input signal through a resistor R14, and the emitter electrode of the fourth triode Q4 is connected with the ground.

The utility model provides an H bridge circuit controlled by a controllable logic circuit, which comprises an H bridge driving circuit and a controllable logic circuit, wherein the H bridge driving circuit comprises an upper driving unit and a lower driving unit;

the upper driving unit comprises a first triode Q1, the base of the first triode Q1 is connected with the Control + Control end of the controllable logic circuit through a resistor R6, the collector and the emitter of the first triode Q1 are respectively connected with two transistors at the diagonal positions which are simultaneously conducted in the H bridge circuit, and the collector of the first triode Q1 is connected with the transistors in the H bridge circuit through a resistor R7;

the lower driving unit comprises a second triode Q2, the base of the second triode Q2 is connected with the Control-Control end of the controllable logic circuit through a resistor R8, the collector and emitter of the second triode Q2 are respectively connected with two transistors at the other diagonal position in the H-bridge circuit, and the collector of the second triode Q2 is connected with the transistors in the H-bridge circuit through a resistor R9.

the upper driving unit comprises a third triode Q3, a Control + Control end of the controllable logic circuit is connected with a base electrode of the third triode Q3 through a resistor R10 after passing through a NOT gate U4A, a collector electrode of the third triode Q3 provides a Driver + Control signal for the H-bridge driving circuit through a resistor R12, a collector electrode of the third triode Q3 is connected with a motor driving power supply through a resistor R11, and an emitter electrode of the third triode Q3 is connected with the ground;

the lower driving unit comprises a fourth triode Q4, a Control-Control end of the controllable logic circuit is connected with a base electrode of the fourth triode Q4 through a resistor R13 after passing through a NOT gate U4B, a collector electrode of the fourth triode Q4 provides a Driver-Control signal for the H-bridge driving circuit through a resistor R15, a collector electrode of the fourth triode Q4 is connected with a motor driving power supply through a resistor R14, and an emitter electrode of the fourth triode Q4 is connected with the ground;

the Driver + control signal is connected with the input end of the bridge arm at the same side in the H-bridge circuit;

the Driver-control signal is connected with the other input end of the bridge arm at the same side in the H-bridge circuit.

the Driver + control signal is connected with the input ends of two transistors at diagonal positions in the H-bridge circuit;

the Driver-control signal is connected with the input ends of two transistors at the other diagonal position in the H-bridge circuit.

Further, the transistors in the H-bridge circuit are any one of a triode, a darlington transistor, a field effect transistor, and an IGBT.

The beneficial effects of the utility model reside in that:

the utility model provides a control circuit passes through microcontroller or dedicated PWM module, and the PWM signal of the direct current motor speed governing usefulness of generation controls H bridge circuit through logic circuit, and realization that can be convenient carries out speed governing control to direct current motor. The circuit realizes forward and reverse output control of the H bridge through one path of PWM signal by the analog switch and the direction control signal DIR, thereby effectively reducing the required number of the PWM signal and reducing the programming difficulty of the microprocessor.

Meanwhile, the output of the PWM signal is controlled by the H-bridge control direction control signal DIR or the enable signal EN, so that the direct short circuit above and below the H-bridge is reliably avoided, and the reliable work of the circuit is ensured. Through the change of the connection mode of parts in the circuit, the method can be widely suitable for different types of microcontrollers and types of H-bridge circuits, and has the characteristics of reliable control logic, convenience, high efficiency, wide application range and reliable functions.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:

fig. 1 is a schematic diagram of two controllable logic circuits based on an analog switch chip.

Fig. 2 is a schematic diagram of a two-way controllable logic circuit based on an and gate.

FIG. 3 is a schematic diagram of a first embodiment of an H-bridge driving circuit.

FIG. 4 is a circuit diagram of a second embodiment of the H-bridge driving circuit.

Fig. 5 is a schematic diagram of a first implementation H-bridge circuit to which the present invention is applied.

Fig. 6 is a schematic diagram of a second embodiment H-bridge circuit to which the present invention is applied.

Fig. 7 is a schematic diagram of a third embodiment H-bridge circuit to which the present invention is applied.

Detailed Description

The present invention is further described with reference to the following drawings and specific examples so that those skilled in the art can better understand the present invention and can practice the present invention, but the examples are not intended to limit the present invention.

As shown in fig. 1, fig. 1 is a controllable logic circuit, and the H-bridge control circuit provided in this embodiment includes two controllable logic circuits and two H-bridge driving circuits,

the input end of the circuit is provided with three input signals, namely an H-bridge output voltage direction control signal DIR, a PWM control signal PWM _ IN and an H-bridge control output enable signal EN.

The analog switch chips U1A and U1B IN fig. 1 can use CD4066 as an option to transmit the PWM control signal PWM _ IN, and when the control terminal C is at high level, the signal connected to the terminal a is output through the terminal B.

IN fig. 1, one path of the H-bridge output voltage direction Control signal DIR is connected to the C-terminal of U1A, and the other path is connected to the C-terminal of U1B through the not-gate U2A IN a reverse direction, so as to ensure that only one path of the analog switch chips U1A and U1B gates the output PWM Control signal PWM _ IN at the same time, and the other path of the output is at a fixed level (low level) to ensure that the priority of the low voltage output from the Control + or Control-terminal is highest, thereby preventing the H-bridge from generating a through short circuit.

IN fig. 1, the H-bridge control output enable signal EN is an H-bridge control output enable signal, when the signal is invalid (high level), the PWM control signal PWM _ IN is blocked through the not gate U2B, at this time, the outputs of the and gates U3A and U3B are both low level, and the PWM control signal PWM _ IN is invalid; when the signal is effective (low level), two paths of analog switch signals can be output through the AND gates U3A and U3B, and the rear H-bridge driving circuit is controlled to work through a Control + or Control-end.

In fig. 1, the and gates (U3A, U3B) implement the functions of controlling signal output and blocking, ensuring that the priority of the low level of the H-bridge control signal output is highest, and when the output is low level, the corresponding H-bridge power switch tube is in an off state, thereby preventing the H-bridge circuit from direct connection and short circuit. The selection of the logic gate can be changed according to the H-bridge driving mode, for example, when the H-bridge power switch tube driving signal is turned off when being high, the logic gate is changed into an OR gate, and the highest high level priority is ensured.

IN fig. 1, the H-bridge output voltage direction control signal DIR is externally connected with a pull-up resistor R1, the PWM control signal PWM _ IN is externally connected with a pull-down resistor R2, and the resistors R1 and R2 are used for ensuring the fixed level of the control pins when the system is powered on, so as to prevent the H-bridge from being IN an unpredictable state due to uncertain output of the logic circuit.

IN the controllable logic circuit IN fig. 1, because only one of the analog switch chips U1A and U1B is gated, if U1A is IN a gated state, the PWM Control signal PWM _ IN is output through the B terminal thereof, and then output to Control + through the 3 pin of U3A, and at this time U1B is IN an off state, the 6 pin of U3B is at a low level, that is, Control-is at a low level, and at this time, the Control of the H-bridge circuit can be realized through Control + and Control-so that, for example, the H-bridges S1 and S4 IN fig. 3 operate, and S2 and S3 are turned off, and the motor is controlled to move IN one direction.

U2B ensures that the output is low when the EN end pin defaults to high level on the singlechip in figure 1, realizes H bridge control signal blockade, prevents that the H bridge from appearing unpredictable's action when the system is electrified. The NOT gate can be selectively added or cancelled according to the initial state of power-on of different control chips, for example, the initial state of an output signal EN of the microcontroller is low level, and the NOT gate can be cancelled.

In fig. 1, the resistors R1 and R3 are pull-up resistors, and the resistor R2 is a pull-down resistor, so that the control pin level is fixed when the system is powered on, and an unpredictable state of the H-bridge is prevented. Different connection modes can be selected or cancelled according to actual conditions. In the circuit, R4 and R5 are pull-down resistors, so that the output of the analog switch chip is ensured to be at a low level when the circuit is powered on, and the H bridge is prevented from being in an unpredictable state when the circuit is powered on. The resistance at the position can be changed into pull-up according to the working mode of the H bridge.

The control logic truth table of the control circuit provided by the embodiment is as follows:

when the H bridge driving signal is low, the corresponding power switch tube is disconnected; in the table, H — high level; l-low level; PWM-pulse width modulated signal; x-arbitrary state.

The analog electronic switch CD4066 in fig. 1 can select a suitable chip to match with according to the output signal characteristics of the microcontroller or PWM generating chip, and is not limited to CD 4066.

Fig. 2 shows another circuit structure of the controllable logic circuit, in which and gates U1A and U1B are used instead of the analog switch CD4066, so that the same control logic as in fig. 1 can be implemented. The direction control signal DIR controls one of the outputs of the and gates U1A and U1B to be at a low level at a time, thereby blocking the transmission of the PWM signal at the input terminal of the corresponding and gate.

The H-bridge driving circuit provided in this embodiment is divided into an upper driving unit and a lower driving unit, and input ends of the two driving units are respectively connected to two output ends Control +, Control-of the controllable logic circuit.

As shown in fig. 3, fig. 3 is a first embodiment of the H-bridge driving circuit, in which the upper driving unit circuit is controlled by the Control + signal, and two output terminals of the circuit are respectively connected to two transistors in the H-bridge circuit, which are located at diagonal positions and are turned on simultaneously, such as S1 and S4 in fig. 3. The lower driving unit circuit is controlled by a Control signal, and the output end of the lower driving unit circuit is connected with the other two transistors S2 and S3 which are positioned at diagonal positions in the H bridge.

Taking fig. 3 as an example, the H-bridge driving circuit provided in this embodiment is divided into an upper driving unit and a lower driving unit, input ends of the two driving units are respectively connected to two output ends Control +, Control + of the controllable logic circuit, and fig. 3 is a first implementation circuit of the H-bridge driving circuit, where the upper driving unit circuit is controlled by a Control + signal, a driving signal of the H-bridge circuit is provided through NPN triodes Q1 and Q2, and two output ends of the circuit are respectively connected to two transistors in the H-bridge circuit, which are located at diagonal positions and are turned on at the same time, such as S1 and S4 in fig. 5. The lower driving unit circuit is controlled by a Control signal, and the output end of the lower driving unit circuit is connected with the other two transistors S2 and S3 which are positioned at diagonal positions in the H bridge.

As shown in fig. 4, fig. 4 is a second implementation circuit of an H-bridge driving circuit, and the H-bridge driving circuit provided in this embodiment includes an H-bridge circuit formed by two H-bridge driving signals Driver + and Driver-provided by the input terminals Control + and Control-of an upper driving unit circuit and a lower driving unit circuit respectively provided to the MOS transistors shown in fig. 6 and 7 after passing through the not gate and the NPN triodes Q3 and Q4.

As shown in fig. 5, fig. 5 is a first embodiment of the H-bridge driving circuit, in this embodiment, the collector of S1 is connected to the collector of S2 and to one end of the motor, and the collector of S3 is connected to the collector of S4 and to the other end of the motor, where S1 and S3 are PNP transistors, S2 and S4 are NPN transistors. In operation, the bases of S1 and S4 are controlled by one H-bridge drive unit circuit, and S2 and S3 are controlled by another H-bridge drive unit circuit. Due to the function of the front control logic circuit, two groups of triodes of S1, S4, S2 and S3 cannot be conducted simultaneously, so that the problem of direct short circuit of the H bridge can be effectively avoided, and the normal work of the H bridge is ensured.

As shown in fig. 6, fig. 6 is a second implementation H-bridge driving circuit, in which S11 and S13 are P-channel MOS transistors, S12 and S14 are N-channel MOS transistors, the drain of S11 is connected to the drain of S12 and to one end of the motor, the drain of S13 is connected to the drain of S14 and to the other end of the motor, and the motor is connected to the output terminal of the H-bridge circuit. When the H-bridge driving circuit works, two ports of the Driver + control signal and the Driver-control signal are connected with an input end in an H-bridge, the Driver + control signal is connected with an input end of a bridge arm at the same side in the H-bridge circuit, and gates of S11 and S12 are controlled by an H-bridge driving unit circuit; the Driver-control signal is connected with the other input end of the same-side bridge arm in the H-bridge circuit, and S13 and S14 are controlled by the other H-bridge driving unit circuit, so that two groups of MOS (metal oxide semiconductor) transistors S11 and S14, S12 and S13 are not conducted at the same time, and the H-bridge is ensured to work normally.

As shown in fig. 7, fig. 7 shows an H-bridge driving circuit according to the third embodiment, in which S21-S24 are all N-channel MOS transistors. The source of S21 is connected to the drain of S22 and to one end of the motor, and the source of S23 is connected to the drain of S24 and to the other end of the motor. When the Driver + control circuit works, the Driver + control signals are connected with the input ends of two transistors at diagonal positions in an H bridge circuit, and the gates of S21 and S24 are controlled by an H bridge driving unit circuit; the Driver-control signal is connected with the input ends of two transistors at the other diagonal position in the H-bridge circuit, and S22 and S23 are controlled by the other H-bridge driving unit circuit, so that two groups of MOS (metal oxide semiconductor) transistors S21 and S24, S22 and S23 are not conducted at the same time, and the normal work of the H-bridge is ensured.

The power driving tube in the H-bridge provided by this embodiment may be formed in various forms such as a triode, a darlington tube, a field effect tube, and an IGBT. To different H bridge circuit, all can get control through this control logic circuit to make the circuit possess only need single-channel PWM control signal PWM _ IN just can realize the speed governing of two direction of rotation of direct current motor, accessible direction control signal controls motor direction IN a flexible way, accessible enable signal EN realizes the blockade to H bridge input signal when special demand, with the motor control signal who cuts off H bridge circuit.

The controllable logic circuit provided by the embodiment can drive different H-bridge circuits, and can adapt to the H-bridge working in different voltage ranges through the improvement of the controllable logic circuit.

The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.

Claims

1. A controllable logic circuit for an H-bridge circuit, characterized by: the analog switch circuit comprises an input end, a first analog switch chip U1A, a second analog switch chip U1B, a first AND gate U3A and a second AND gate U3B;

2. The controllable logic circuit of claim 1, wherein: the H-bridge output voltage direction control signal DIR is externally connected with a pull-up resistor R1, or the PWM control signal PWM _ IN is externally connected with a pull-down resistor R2, or the H-bridge control output enable signal EN is externally connected with a pull-up resistor R3, or a pull-down resistor R4 is externally connected at the position of a first analog switch chip U1A; or a pull-down resistor R5 is externally connected to the second analog switch chip U1B.

3. The controllable logic circuit of claim 1, wherein: the first analog switch chip U1A and the second analog switch chip U1B are analog electronic switches CD4066 or any one of AND gates.

4. The controllable logic circuit of claim 1, wherein: the controllable logic circuit also includes a first transistor Q1 and a second transistor Q2,

5. The controllable logic circuit of claim 1, wherein: the controllable logic circuit also includes a third transistor Q3 and a fourth transistor Q4,

the Control + Control end is connected with the base electrode of a third triode Q3 through a resistor R10 after passing through a NOT gate U4A, the collector electrode of the third triode Q3 provides a Driver + Control signal for an H-bridge driving circuit through a resistor R12, the collector electrode of the third triode Q3 is connected with a motor driving power supply through a resistor R11, and the emitter electrode of the third triode Q3 is connected with the ground;

the Control-Control end is connected with the base electrode of a fourth triode Q4 through a resistor R13 after passing through a NOT gate U4B, the collector electrode of the fourth triode Q4 provides a Driver-Control signal for the H-bridge driving circuit through a resistor R15, the collector electrode of the fourth triode Q4 is connected with a motor driving power supply through a resistor R14, and the emitter electrode of the fourth triode Q4 is connected with the ground.

6. An H-bridge circuit formed using the controllable logic circuit of any one of claims 1-5, wherein: the H-bridge driving circuit comprises an upper driving unit and a lower driving unit;

7. An H-bridge circuit formed using the controllable logic circuit of any of claims 1-5, wherein: the H-bridge driving circuit comprises an upper driving unit and a lower driving unit;

8. An H-bridge circuit formed using the controllable logic circuit of any of claims 1-5, wherein: the H-bridge driving circuit comprises an upper driving unit and a lower driving unit;

the upper driving unit comprises a third triode Q3, a Control + Control end of the controllable logic circuit is connected with a base electrode of the third triode Q3 through a resistor R10 after passing through a NOT gate U4A, a collector electrode of the third triode Q3 provides a Driver + Control signal for the H-bridge driving circuit through a resistor R12, a collector electrode of the third triode Q3 is connected with a voltage input signal through a resistor R11, and an emitter electrode of the third triode Q3 is connected with the ground;

the lower driving unit comprises a fourth triode Q4, a Control-Control end of the controllable logic circuit is connected with a base electrode of the fourth triode Q4 through a resistor R13 after passing through a NOT gate U4B, a collector electrode of the fourth triode Q4 provides a Driver-Control signal for the H-bridge driving circuit through a resistor R15, a collector electrode of the fourth triode Q4 is connected with a voltage input signal through a resistor R14, and an emitter electrode of the fourth triode Q4 is connected with the ground;