CN211860063U

CN211860063U - Ultra-bandwidth dual-frequency combiner

Info

Publication number: CN211860063U
Application number: CN202020595022.8U
Authority: CN
Inventors: 王忠良; 陈习希; 骆艳
Original assignee: Guangdong Xiongmai Communication Technology Co ltd
Current assignee: Guangdong Xiongmai Communication Technology Co ltd
Priority date: 2020-04-20
Filing date: 2020-04-20
Publication date: 2020-11-03
Anticipated expiration: 2030-04-20

Abstract

The utility model discloses a super bandwidth dual-frenquency combiner, which comprises a substrate, the upper end of base plate is equipped with lumped parameter circuit, distributed parameter circuit, low frequency port LF, high frequency port HF and common port COM, and lumped parameter circuit and distributed parameter circuit integration are in 1 upper ends of base plate, and one side at the base plate is installed to low frequency port LF and high frequency port HF symmetry, and the opposite side at the base plate is installed to common port COM. This super bandwidth dual-frenquency combiner adopts the low pass transmission line mode to replace the realization mode of traditional metal cavity filter to can realize that low frequency 380MHz reaches the super broadband design of high frequency 2700MHz, the big return loss of time delay of having solved traditional combiner super bandwidth and can not reach the problem, whole volume diminishes, weight reduction, insertion loss is less than 0.3db, high low frequency mutual isolation is greater than 100db, fine solution 2G,3G,4G, the full coverage of 5G frequency channel.

Description

Ultra-bandwidth dual-frequency combiner

Technical Field

The utility model relates to a combiner technical field specifically is a super bandwidth dual-frenquency combiner.

Background

At present, most of known radio frequency signal combiners adopt a band-pass filter mode, are generally expensive, heavy, large in size, large in insertion loss and low in high-low frequency mutual isolation, and can not combine radio frequency signals (2G, 3G,4G and 5G frequency bands) of most of the current civil mobile communication systems into a single-path signal.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a super bandwidth dual-frenquency combiner, it is small to have, and light in weight realizes the advantage of the super broadband of low frequency 380MHz to high frequency 2700MHz, has solved the problem that the big return loss of traditional combiner super bandwidth time delay can not reach.

In order to achieve the above object, the utility model provides a following technical scheme: the ultra-bandwidth dual-frequency combiner comprises a substrate, wherein a lumped parameter circuit, a distributed parameter circuit, a low-frequency port LF, a high-frequency port HF and a common port COM are arranged at the upper end of the substrate, the lumped parameter circuit and the distributed parameter circuit are integrated at the upper end of the substrate 1, the low-frequency port LF and the high-frequency port HF are symmetrically arranged on one side of the substrate, and the common port COM is arranged on the other side of the substrate.

Preferably, the total parameter circuit comprises a low-pass transmission line ML1, a chip-shaped air-wound inductor L1, a chip-shaped air-wound inductor L2, a chip-shaped high-Q capacitor C1-a chip-shaped high-Q capacitor C8; an input end of the low-pass transmission line ML1 is electrically connected with an output end of the low-frequency port LF, an input end of the low-pass transmission line ML1 is electrically connected with an input end of the chip-shaped air-core wound inductor L1, an output end of the chip-shaped air-core wound inductor L1 is electrically connected with an input end of the chip-shaped air-core wound inductor L2, an output end of the chip-shaped air-core wound inductor L2 is electrically connected with an input end of the chip-shaped high-Q-value capacitor C1, the chip-shaped high-Q-value capacitor C1, the chip-shaped high-Q-value capacitor C2, the chip-shaped high-Q-value capacitor C3, the chip-shaped high-Q-value capacitor C4, the chip-shaped high-Q-value capacitor C5, the chip-shaped high-Q-value capacitor C6, the chip-shaped high-Q-value.

Preferably, the distributed parameter circuit comprises an open-circuit microstrip capacitor MC1, an interdigital capacitor FC1 and a microstrip transmission line ML2, wherein an input end of the microstrip transmission line ML2 is electrically connected with an output end of the low-frequency port LF, an output end of the microstrip transmission line ML2 is electrically connected with an input end of the microstrip capacitor MC1, an output end of the microstrip capacitor MC1 is electrically connected with an input end of the interdigital capacitor FC1, an output end of the interdigital capacitor FC1 is connected to an input end of the common port COM, and the common port COM is connected with the signal output.

Preferably, the substrate is mounted with a low frequency end connection bar, and the chip-type high-Q capacitor C1-the chip-type high-Q capacitor C8, the chip-type air-wound inductor L1, and the chip-type air-wound inductor L2 are mounted on the low frequency end connection bar.

Preferably, the substrate is provided with a high frequency terminal connection bar, and the open-circuit microstrip capacitor MC1 and the interdigital capacitor FC1 are provided on the high frequency terminal connection bar.

Compared with the prior art, the beneficial effects of the utility model are as follows:

this super bandwidth dual-frenquency combiner adopts the low pass transmission line mode to replace the realization mode of traditional metal cavity filter to can realize that low frequency 380MHz reaches the super broadband design of high frequency 2700MHz, the big return loss of time delay of having solved traditional combiner super bandwidth and can not reach the problem, whole volume diminishes, weight reduction, insertion loss is less than 0.3db, high low frequency mutual isolation is greater than 100db, fine solution 2G,3G,4G, the full coverage of 5G frequency channel.

Drawings

Fig. 1 is a schematic view of the overall structure of the present invention;

FIG. 2 is a schematic view of the structure of the low frequency end connecting rod of the present invention;

FIG. 3 is a schematic view of the structure of the high-frequency end connecting rod of the present invention;

FIG. 4 is a diagram of the lumped parameter circuit and distributed parameter circuit of the present invention;

fig. 5 is a circuit diagram of the lumped parameter circuit and distributed parameter connection circuit of the present invention.

In the figure: 1. a substrate; 2. a lumped parameter circuit; 3. a distributed parameter circuit; 4. a low frequency port LF; 5. a high frequency port HF; 6. a common port COM; 7. a low frequency end connecting rod; 8. high frequency end connecting rod.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-3, an ultra-wideband dual-band combiner includes a substrate 1, a lumped parameter circuit 2, a distributed parameter circuit 3, a low frequency port LF4, a high frequency port HF5, and a common port COM6 are disposed at an upper end of the substrate 1, the lumped parameter circuit 2 and the distributed parameter circuit 3 are integrated at the upper end of the substrate 1, a low frequency port LF4 and the high frequency port HF5 are symmetrically mounted at one side of the substrate 1, the common port COM6 is mounted at the other side of the substrate 1, the substrate 1 is mounted with the low frequency end connection rod 7, a chip high-Q capacitor C1, a chip high-Q capacitor C8, a chip hollow wound inductor L1, and a chip hollow wound inductor L2 are mounted on the low frequency end connection rod 7, the substrate 1 is mounted with the high frequency end connection rod 8, and an open-circuit microstrip capacitor MC1 and an interdigital capacitor FC1 are mounted on the high frequency end connection rod 8.

Referring to fig. 4-5, the lumped parameter circuit 2 includes a low-pass transmission line ML1, a chip air-wound inductor L1, a chip air-wound inductor L2, a chip high-Q capacitor C1-a chip high-Q capacitor C8; the input end of the low-pass transmission line ML1 is electrically connected with the output end of the low-frequency port LF4, the input end of the low-pass transmission line ML1 is electrically connected with the input end of the sheet-shaped hollow wound inductor L1, the output end of the sheet-shaped hollow wound inductor L1 is electrically connected with the input end of the sheet-shaped hollow wound inductor L2, the output end of the sheet-shaped hollow wound inductor L2 is electrically connected with the input end of the sheet-shaped high-Q-value capacitor C1, the sheet-shaped high-Q-value capacitor C1, the sheet-shaped high-Q-value capacitor C2, the sheet-shaped high-Q-value capacitor C3, the sheet-shaped high-Q-value capacitor C4, the sheet-shaped high-Q-value capacitor C5, the sheet-shaped high-Q-value capacitor C6, the sheet-shaped high-Q-value capacitor C7 and the sheet-shaped high-Q.

Referring to fig. 4-5, the distributed parameter circuit 3 includes an open-circuit microstrip capacitor MC1, an interdigital capacitor FC1, and a microstrip transmission line ML2, wherein an input terminal of the microstrip transmission line ML2 is electrically connected to an output terminal of the low frequency port LF4, an output terminal of the microstrip transmission line ML2 is electrically connected to an input terminal of a microstrip capacitor MC1, an output terminal of the microstrip capacitor MC1 is electrically connected to an input terminal of the interdigital capacitor FC1, an output terminal of the interdigital capacitor FC1 is connected to an input terminal of the common port COM6, and the common port COM6 is connected to the signal output.

This super broadband dual-frenquency combiner adopts the low pass transmission line mode to replace the implementation of traditional metal cavity filter to can realize that low frequency 380MHz reaches the super broadband design of high frequency 2700MHz, solve the big return loss of super broadband time delay of traditional combiner and can not reach the problem, concrete principle is as follows: the low-pass transmission line ML1 is matched with 50 ohms so that the integral return loss of a 2320MHz bandwidth in a 380MHz-2700MHz frequency band reaches more than 24db, the micro-strip transmission line ML2 is matched with 50 ohms so that the integral return loss of a 700MHz bandwidth in a 3300MHz-4G frequency band reaches more than 100db, a low-frequency signal and a high-frequency signal are synthesized into a single-path signal and then are connected out from a common port COM6, the integral volume is reduced, the weight is reduced, the insertion loss is less than 0.3db, the high-frequency and low-frequency mutual isolation is more than 100db, and the full coverage of the 2G,3G,4G and 5G frequency bands is well solved.

In summary, the following steps: this super bandwidth dual-frenquency combiner adopts the low pass transmission line mode to replace the realization mode of traditional metal cavity filter to can realize that low frequency 380MHz reaches the super broadband design of high frequency 2700MHz, the big return loss of time delay of having solved traditional combiner super bandwidth and can not reach the problem, whole volume diminishes, weight reduction, insertion loss is less than 0.3db, high low frequency mutual isolation is greater than 100db, fine solution 2G,3G,4G, the full coverage of 5G frequency channel.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The utility model provides a super broadband dual-frenquency combiner, includes base plate (1), its characterized in that: the integrated circuit is characterized in that the upper end of the substrate (1) is provided with a lumped parameter circuit (2), a distributed parameter circuit (3), a low-frequency port LF (4), a high-frequency port HF (5) and a common port COM (6), the lumped parameter circuit (2) and the distributed parameter circuit (3) are integrated on the upper end of the substrate (1), the low-frequency port LF (4) and the high-frequency port HF (5) are symmetrically installed on one side of the substrate (1), and the common port COM (6) is installed on the other side of the substrate (1).

2. The ultra-wideband dual-frequency combiner of claim 1, wherein: the lumped parameter circuit (2) comprises a low-pass transmission line ML1, a chip-shaped air-core wound inductor L1, a chip-shaped air-core wound inductor L2, a chip-shaped high-Q-value capacitor C1 and a chip-shaped high-Q-value capacitor C8; an input end of the low-pass transmission line ML1 is electrically connected with an output end of the low-frequency port LF (4), an input end of the low-pass transmission line ML1 is electrically connected with an input end of the chip-shaped air-wound inductor L1, an output end of the chip-shaped air-wound inductor L1 is electrically connected with an input end of the chip-shaped air-wound inductor L2, an output end of the chip-shaped air-wound inductor L2 is electrically connected with an input end of the chip-shaped high-Q-value capacitor C1, the chip-shaped high-Q-value capacitor C1, the chip-shaped high-Q-value capacitor C2, the chip-shaped high-Q-value capacitor C3, the chip-shaped high-Q-value capacitor C4, the chip-shaped high-Q-value capacitor C5, the chip-shaped high-Q-value capacitor C6, the chip-shaped high-Q-value capacitor C7 and the chip-shaped high-.

3. The ultra-wideband dual-frequency combiner of claim 1, wherein: the distributed parameter circuit (3) comprises an open-circuit microstrip capacitor MC1, an interdigital capacitor FC1 and a microstrip transmission line ML2, wherein the input end of the microstrip transmission line ML2 is electrically connected with the output end of the low-frequency port LF (4), the output end of the microstrip transmission line ML2 is electrically connected with the input end of the microstrip capacitor MC1, the output end of the microstrip capacitor MC1 is electrically connected with the input end of the interdigital capacitor FC1, the output end of the interdigital capacitor FC1 is connected to the input end of a common port COM (6), and the common port COM (6) is connected with signal output.

4. The ultra-wideband dual-frequency combiner of claim 1, wherein: the low-frequency end connecting rod (7) is assembled on the substrate (1), and the chip-shaped high-Q capacitor C1-the chip-shaped high-Q capacitor C8, the chip-shaped hollow wound inductor L1 and the chip-shaped hollow wound inductor L2 are assembled on the low-frequency end connecting rod (7).

5. The ultra-wideband dual-frequency combiner of claim 1, wherein: and a high-frequency end connecting rod (8) is assembled on the substrate (1), and the open-circuit microstrip capacitor MC1 and the interdigital capacitor FC1 are assembled on the high-frequency end connecting rod (8).