CN211830735U - Signal switching circuit and device - Google Patents
Signal switching circuit and device Download PDFInfo
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- CN211830735U CN211830735U CN202020719575.XU CN202020719575U CN211830735U CN 211830735 U CN211830735 U CN 211830735U CN 202020719575 U CN202020719575 U CN 202020719575U CN 211830735 U CN211830735 U CN 211830735U
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Abstract
The utility model discloses a signal switching circuit and a device, wherein the circuit comprises a control chip, a first switch chip and a second switch chip, the control chip is used for outputting at most one of a first enabling signal, a second enabling signal or a third enabling signal; the first switch chip is used for receiving a first signal and outputting the first signal when the first enable end receives the first enable signal; the second switch chip is used for respectively receiving a second signal and a third signal, and outputting the second signal when the second enable terminal receives the second enable signal; outputting the third signal when the third enable terminal receives the third enable signal. The utility model discloses can realize three routes input signal's signal switching to need not receive the restriction of the pin function definition of switch chip itself, thereby reduced the components and parts requirement of circuit, reduced the device cost, realized the pluralism of device lectotype.
Description
Technical Field
The utility model relates to a circuit electron field especially relates to signal switching circuit and device.
Background
During the signal switching process of the switch circuit, the number of input signals and the number of signal channels of each input signal are limited by the number of pins of the switching chip implementing the switching logic. Therefore, when designing the switching function of the input signal, there is usually a certain requirement on the number of pins and the number of channels of the switching chip, i.e., there is a limit to the model of the switching chip. In addition, the conventional switch circuit is generally a dual-logic switch circuit, and is generally used for controlling signal switching of two groups of input signals, but signal switching of multiple input signals cannot be realized.
SUMMERY OF THE UTILITY MODEL
A primary object of the present invention is to provide a signal switching circuit and device, which can solve the problem of the prior signal switching circuit that can not realize the switching of multiple signals.
In order to achieve the above object, the present invention provides a signal switching circuit, including:
the control chip is used for outputting at most one of the first enabling signal, the second enabling signal or the third enabling signal;
the first enabling end of the first switch chip is connected with the control chip;
the second enabling end and the third enabling end of the second switch chip are respectively connected with the control chip;
the first signal output end of the first switch chip is respectively connected with the second signal output end of the second switch chip and the third signal output end of the second switch chip;
the first switch chip is used for receiving a first signal and outputting the first signal when the first enable end receives the first enable signal;
the second switch chip is used for respectively receiving a second signal and a third signal, and outputting the second signal when the second enable terminal receives the second enable signal; outputting the third signal when the third enable terminal receives the third enable signal.
Optionally, the signal switching circuit further comprises a first pull-up circuit and a second pull-up circuit;
the first pull-up circuit comprises a first input control end and a first output control end, the first input control end is connected with the control chip, and the first output control end is connected with the first enabling end;
the second pull-up circuit comprises a second input control end, a second output control end, a third input control end and a third output control end, the second input control end is connected with the control chip, the third input control end is connected with the control chip, the second output control end is connected with the second enabling end, and the third output control end is connected with the third enabling end.
Optionally, the first pull-up circuit comprises a first resistor and a first capacitor;
the first end of the first resistor is connected with a high level, the second end of the first resistor is connected with the control chip, the first end of the first capacitor is connected with the second end of the first resistor, the second end of the first capacitor is grounded, and the second end of the first resistor is also connected with the first enabling end.
Optionally, the first pull-up circuit further comprises a second resistor;
the second end of the first resistor is connected with the first enabling end through the second resistor.
Optionally, the second pull-up circuit comprises a third resistor, a fourth resistor, a second capacitor and a third capacitor;
a first end of the third resistor is connected with a high level, a second end of the third resistor is connected with the control chip, a first end of the second capacitor is connected with a second end of the third resistor, a second end of the second capacitor is grounded, and a second end of the third resistor is also connected with the second enable end;
the first end of the fourth resistor is connected with a high level, the second end of the fourth resistor is connected with the control chip, the first end of the third capacitor is connected with the second end of the fourth resistor, the second end of the third capacitor is grounded, and the second end of the fourth resistor is also connected with the third enabling end.
Optionally, the second pull-up circuit further comprises a fifth resistor and a sixth resistor;
the second end of the third resistor is connected with the second enabling end through the third resistor;
and the second end of the fourth resistor is connected with the third enabling end through the fourth resistor.
Optionally, the signal switching circuit further includes a seventh resistor and a fourth capacitor;
the power supply end of the first switch chip is connected with the first end of the fourth capacitor, the second end of the fourth capacitor is connected with the grounding end of the first switch chip, the grounding end of the first switch chip is grounded, and the first end of the fourth capacitor is further connected with a high level through the seventh resistor.
Optionally, the signal switching circuit further includes an eighth resistor and a fifth capacitor;
the power supply end of the second switch chip is connected with the first end of the fifth capacitor, the second end of the fifth capacitor is connected with the grounding end of the second switch chip, the grounding end of the second switch chip is grounded, and the first end of the fifth capacitor is further connected with a high level through the eighth resistor.
Optionally, the first switch chip and the second switch chip are 74LVC244 type buffers.
Further, in order to achieve the above object, the present invention also provides a signal switching apparatus including a signal switching circuit configured as the signal switching circuit described above.
The utility model discloses a first switch chip and second switch chip acquire first signal, second signal and third signal to when receiving the enabling signal of difference, the signal path that the control corresponds feeds through, and breaks off the data path of other two way signals, can realize three routes input signal's signal switching promptly. In the selection process of the switch chip, only the second switch chip is required to have two data paths, and the two enable terminals can be used for gating respectively without being limited by the pin function definition of the switch chip, so that the component requirement of the circuit is reduced, the component cost is reduced, and the diversification of the component selection is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a signal switching circuit according to an embodiment of the present invention.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
The reference numbers illustrate:
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a signal switching circuit, this signal switching circuit can receive the input of three routes signal to realize the signal switching of three routes signal through received enable signal.
Referring to fig. 1, in an embodiment, the signal switching circuit includes a control chip MCU, a first switch chip U1 and a second switch chip U2. The control chip MCU may output at most one of the first enable signal, the second enable signal, or the third enable signal. The first enabling end of the first switch chip U1 is connected with the control chip MCU, and the second enabling end and the third enabling end of the second switch chip U2 are also connected with the control chip MCU respectively. The control chip MCU may output the first enable signal to the first enable terminal, the second enable signal to the second enable terminal, or the third enable signal to the third enable terminal. The first switch chip U1 may also receive the first signal S1, and the second switch chip U2 may also receive the second signal S2 and the third signal S3, respectively. The first switch chip U1 may gate the signal path of the first signal S1 to output the first signal S1 through the first signal output terminal when the first enable terminal receives the first enable signal output by the control chip MCU, and at this time, the data paths of the second signal S2 and the third signal S3 of the second switch chip U2 are disconnected, i.e., the second signal S2 and the third signal S3 are not output. Similarly, when the second enable terminal of the second switch chip U2 receives the second enable signal output by the control chip MCU, the signal path of the second signal S2 may be gated to output the second signal S2 through the second signal output terminal, and at this time, the data paths of the first signal S1 of the first switch chip U1 and the third signal S3 of the second switch chip U2 are disconnected, i.e., the first signal S1 and the third signal S3 are not output; when the third enable terminal of the second switch chip U2 receives the third enable signal output by the control chip MCU, the signal path of the third signal S3 may be gated to output the third signal S3 through the third signal output terminal, and at this time, the data paths of the first signal S1 of the first switch chip U1 and the second signal S2 of the second switch chip U2 are disconnected, i.e., the first signal S1 and the second signal S2 are not output. The first signal output end of the first switch chip U1 is connected to the second signal output end of the second switch chip U2 and the third signal output end of the second switch chip U2, respectively. That is, the first and second switch chips U1 and U2 may implement three-to-one paths of the first, second, and third signals S1, S2, and S3.
It is understood that the control chip MCU may be configured to output at most one of the first enable signal, the second enable signal or the third enable signal only. That is, the first switch chip U1 and the second switch chip U2 may be configured to output only one of the first signal S1, the second signal S2, and the third signal S3 at the same time to avoid mutual interference between the signals.
In this embodiment, one of the first enable signal, the second enable signal, and the third enable signal is obtained through the first switch chip U1 and the second switch chip U2, and when different enable signals are received, the corresponding signal path is controlled to be connected, and the data paths of the other two paths of signals are disconnected, so that one-out-of-three output of the three paths of input signals can be realized. In the selection process of the switch chip, the second switch chip U2 is only required to have two paths of data paths, the two enabling ends can be used for gating respectively, and the limitation of pin function definition of the switch chip is not required, so that the component requirement of the circuit is reduced, the component cost is reduced, and the diversification of component type selection is realized.
Furthermore, the signal switching circuit may further include a first pull-up circuit 10 and a second pull-up circuit 20, and the enable terminals of the first switch chip U1 and the second switch chip U2 may be set to be turned off when the control path is at a high level and turned on when the control path is at a low level. The first pull-up circuit 10 may include a first input control terminal connected to the control chip MCU and a first output control terminal connected to the first enable terminal. The second pull-up circuit 20 may include a second input control terminal, a second output control terminal, a third input control terminal and a third output control terminal, the second input control terminal is connected to the control chip MCU, the third input control terminal is connected to the control chip MCU, the second output control terminal is connected to the second enable terminal, and the third output control terminal is connected to the third enable terminal. The three output ends of the control chip MCU are respectively connected to the first input control end, the second input control end and the third input control end to respectively output a first enable signal to the first switch chip U1, a second enable signal to the second switch chip U2 or a third enable signal to the second switch chip.
The first pull-up circuit 10 and the second pull-up circuit 20 are used for adding a bias level between the signal output terminal and the enable terminal of the switch chip, so that the three enable terminals of the first switch chip U1 and the second switch chip U2 all receive a high level by default and are in a non-gating state, so as to avoid signal crosstalk.
The first pull-up circuit 10 may include a first resistor R1, a first capacitor C1, and a second resistor R2. The first end of the first resistor R1 is connected with a high level, the second end of the first resistor R1 is connected with the control chip MCU, the first end of the first capacitor C1 is connected with the second end of the first resistor R1, the second end of the first capacitor C1 is grounded, and the second end of the first resistor R1 is connected with the first enabling end through the second resistor R2.
The second pull-up circuit 20 may include a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second capacitor C2, and a third capacitor C3. The first end of the third resistor R3 is connected with a high level, the second end of the third resistor R3 is connected with the control chip MCU, the first end of the second capacitor C2 is connected with the second end of the third resistor R3, the second end of the second capacitor C2 is grounded, and the second end of the third resistor R3 is connected with the second enable end through the third resistor R3. The first end of the fourth resistor R4 is connected with a high level, the second end of the fourth resistor R4 is connected with the control chip MCU, the first end of the third capacitor C3 is connected with the second end of the fourth resistor R4, the second end of the third capacitor C3 is grounded, and the second end of the fourth resistor R4 is connected with the third enabling end through the fourth resistor R4.
In the above embodiment, the three enable terminals of the first switch chip U1 and the second switch chip U2 are turned on at low level, and at most one of the three enable signals respectively output by the control chip MCU may be set to be a low level signal. That is, when the first enable signal output by the control chip MCU is a low level signal, the second enable signal and the third enable signal are high level signals. At this time, the signal received by the first enable terminal of the first switch chip U1 is converted from a high-level signal to a low-level signal, and the first switch chip U1 may control the signal path on which the first enable signal is located to be gated, so as to output the first signal S1. Similarly, when the second switch chip U2 receives that the second enable signal is a low-level signal or the third enable signal is a low-level signal, it may control the signal path of the second enable signal or the third enable signal to be gated to output the second signal S2 or the third signal S3. The signal path gating corresponding to the path signal can be realized by controlling one path of the first enable signal, the second enable signal and the third enable signal to output the low level signal, and the signal switching of the three paths of signals can be realized by switching and outputting the low level signal through the first enable signal, the second enable signal and the third enable signal.
Furthermore, the signal switching circuit may further include a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, and a fifth capacitor C5, wherein a power supply terminal of the first switch chip U1 is connected to a first terminal of the fourth capacitor C4, a second terminal of the fourth capacitor C4 is connected to a ground terminal of the first switch chip U1, the ground terminal of the first switch chip U1 is grounded, a first terminal of the fourth capacitor C4 is further connected to a high level through the seventh resistor R7, a power supply terminal of the second switch chip U2 is connected to a first terminal of the fifth capacitor C5, a second terminal of the fifth capacitor C5 is connected to a ground terminal of the second switch chip U2, the ground terminal of the second switch chip U2 is grounded, and a first terminal of the fifth capacitor C5 is further connected to the high level through the eighth resistor R8. Through the parallel connection of the capacitor between the power supply end and the grounding end of the switch chip, noise waves and alternating current parts in current can be filtered.
Further, the first switch chip U1 and the second switch chip U2 may be 74LVC244 type buffers. The 74LVC244 type buffer has two enabling ends and 8 signal channels, and each enabling end can control the connection or disconnection of 4 signal channels. The second switch chip U2 can receive the second signal S2 and the third signal S3 of the 4 input signals, and the first switch chip U1 can receive the first signal S1 of at most 8 input signals, and in actual use, the number of channels used can be flexibly adjusted according to needs.
It should be noted that, when the 74LVC244 type buffer is adopted, the input level amplitudes of the input first signal S1, second signal S2 and third signal S3 need to be lower than the 74LVC244 operating voltage. Preferably, the first resistor R1, the third resistor R3 and the fourth resistor R4 are 10k Ω, the second resistor R2, the fifth resistor R5 and the sixth resistor R6 are 1k Ω, the seventh resistor R7 and the eighth resistor R8 are 4.7 Ω, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are 1 μ F, and the high level VDD may be 3.3V.
In the above embodiment, the two switch chips may also be set such that each switch chip corresponds to two paths of signals, that is, the two switch chips implement signal switching of four paths of signals. It can be understood that the gating switching function of the multi-path input signals can be realized by arranging a plurality of switch chips and arranging corresponding multi-path enable signals.
The utility model also provides a signal switching device, this signal switching device include signal switching circuit. The structure of the signal switching circuit can refer to the above embodiments, and is not described herein again. It should be understood that, since the signal switching device of the present embodiment adopts the technical solution of the signal switching circuit, the signal switching device has all the beneficial effects of the signal switching circuit.
The above is only the optional embodiment of the present invention, and not therefore the scope of the present invention is limited, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the same way in the protection scope of the present invention.
Claims (10)
1. A signal switching circuit, comprising:
the control chip is used for outputting at most one of the first enabling signal, the second enabling signal or the third enabling signal;
the first enabling end of the first switch chip is connected with the control chip;
the second enabling end and the third enabling end of the second switch chip are respectively connected with the control chip;
the first signal output end of the first switch chip is respectively connected with the second signal output end of the second switch chip and the third signal output end of the second switch chip;
the first switch chip is used for receiving a first signal and outputting the first signal when the first enable end receives the first enable signal;
the second switch chip is used for respectively receiving a second signal and a third signal, and outputting the second signal when the second enable terminal receives the second enable signal; outputting the third signal when the third enable terminal receives the third enable signal.
2. The signal switching circuit of claim 1, wherein the signal switching circuit further comprises a first pull-up circuit and a second pull-up circuit;
the first pull-up circuit comprises a first input control end and a first output control end, the first input control end is connected with the control chip, and the first output control end is connected with the first enabling end;
the second pull-up circuit comprises a second input control end, a second output control end, a third input control end and a third output control end, the second input control end is connected with the control chip, the third input control end is connected with the control chip, the second output control end is connected with the second enabling end, and the third output control end is connected with the third enabling end.
3. The signal switching circuit of claim 2, wherein the first pull-up circuit comprises a first resistor and a first capacitor;
the first end of the first resistor is connected with a high level, the second end of the first resistor is connected with the control chip, the first end of the first capacitor is connected with the second end of the first resistor, the second end of the first capacitor is grounded, and the second end of the first resistor is also connected with the first enabling end.
4. The signal switching circuit of claim 3, wherein the first pull-up circuit further comprises a second resistor;
the second end of the first resistor is connected with the first enabling end through the second resistor.
5. The signal switching circuit of claim 2, wherein the second pull-up circuit comprises a third resistor, a fourth resistor, a second capacitor, and a third capacitor;
a first end of the third resistor is connected with a high level, a second end of the third resistor is connected with the control chip, a first end of the second capacitor is connected with a second end of the third resistor, a second end of the second capacitor is grounded, and a second end of the third resistor is also connected with the second enable end;
the first end of the fourth resistor is connected with a high level, the second end of the fourth resistor is connected with the control chip, the first end of the third capacitor is connected with the second end of the fourth resistor, the second end of the third capacitor is grounded, and the second end of the fourth resistor is also connected with the third enabling end.
6. The signal switching circuit of claim 5, wherein the second pull-up circuit further comprises a fifth resistor and a sixth resistor;
the second end of the third resistor is connected with the second enabling end through the third resistor;
and the second end of the fourth resistor is connected with the third enabling end through the fourth resistor.
7. The signal switching circuit of claim 1, further comprising a seventh resistor and a fourth capacitor;
the power supply end of the first switch chip is connected with the first end of the fourth capacitor, the second end of the fourth capacitor is connected with the grounding end of the first switch chip, the grounding end of the first switch chip is grounded, and the first end of the fourth capacitor is further connected with a high level through the seventh resistor.
8. The signal switching circuit of claim 1, further comprising an eighth resistor and a fifth capacitor;
the power supply end of the second switch chip is connected with the first end of the fifth capacitor, the second end of the fifth capacitor is connected with the grounding end of the second switch chip, the grounding end of the second switch chip is grounded, and the first end of the fifth capacitor is further connected with a high level through the eighth resistor.
9. The signal switching circuit according to any one of claims 1 to 8, wherein the first switch chip and the second switch chip are 74LVC244 type buffers.
10. A signal switching apparatus, characterized in that the signal switching apparatus comprises a signal switching circuit configured as the signal switching circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020719575.XU CN211830735U (en) | 2020-04-30 | 2020-04-30 | Signal switching circuit and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020719575.XU CN211830735U (en) | 2020-04-30 | 2020-04-30 | Signal switching circuit and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211830735U true CN211830735U (en) | 2020-10-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020719575.XU Active CN211830735U (en) | 2020-04-30 | 2020-04-30 | Signal switching circuit and device |
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|---|---|
| CN (1) | CN211830735U (en) |
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2020
- 2020-04-30 CN CN202020719575.XU patent/CN211830735U/en active Active
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Address after: 516006 community 37, Zhongkai high tech Zone, Huizhou, Guangdong Patentee after: Tongli Technology Co.,Ltd. Address before: 516006 Zhongkai high tech Zone 37, Huizhou, Guangdong Patentee before: TONLY ELECTRONICS HOLDINGS Ltd. |
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