CN211827190U - Low power consumption circuit and circuit system for microprocessor - Google Patents
Low power consumption circuit and circuit system for microprocessor Download PDFInfo
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- CN211827190U CN211827190U CN201921914557.0U CN201921914557U CN211827190U CN 211827190 U CN211827190 U CN 211827190U CN 201921914557 U CN201921914557 U CN 201921914557U CN 211827190 U CN211827190 U CN 211827190U
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Abstract
The present application relates to low power consumption circuits and circuitry for microprocessors. According to the low-power-consumption circuit of the microprocessor, the data which needs to be frequently accessed by the microprocessor in the low-power-consumption standby state is mapped into the RAM, and the flash memory is completely powered off in the standby state, so that the power consumption of the flash memory can be reduced to zero in the standby state, the overall power consumption of the microprocessor circuit is reduced, and the aim of prolonging the standby time of the microprocessor circuit is fulfilled.
Description
Technical Field
The present application relates to the field of chips, and more particularly, to a low power consumption circuit and circuit system for a microprocessor.
Background
With the application fields of the internet of things becoming more and more extensive, many of the application fields require the collection and transmission of low-speed and low-density data information, and most of implementation schemes of such applications require the participation of a microprocessor (MCU for short), in these application scenarios, a circuit in which the microprocessor is located not only needs to provide rich interfaces and sufficient storage space, but also needs to meet the requirements of low power consumption as much as possible in a standby state to realize independent power supply of a battery and ultra-long-time standby. However, in the current low-power-consumption circuit associated with the microprocessor, the flash memory associated with the microprocessor is usually controlled in a standby mode with lower power consumption, but at present, more and more applications have very strict requirements on power consumption, the standby power consumption of the circuit in which the microprocessor is located is required to be several microamps or even less than one microamp, and the power consumption of the flash memory in the standby mode cannot meet the requirements; and as long as the MCU has the requirement of program access, the flash memory can be in a read-write state, the frequency of accessing the flash memory is increased, and the current consumption in the read-write process of the flash memory also increases the overall power consumption of the MCU.
In the related art, an effective solution is not provided at present for the problem that the standby power consumption of a circuit in which a microprocessor is located cannot meet the strict power consumption requirement in some application scenarios.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is desirable to provide a low power consumption circuit and circuit system for a microprocessor.
In order to achieve the above object, according to one aspect of the present invention, there is provided a low power consumption circuit of a microprocessor, including a microprocessor, a flash memory, a RAM random access memory, and a flash memory control circuit; the flash memory is electrically connected with the microprocessor through a bus, the RAM is electrically connected with the microprocessor through the bus, the flash memory control circuit is respectively electrically connected with the microprocessor, the flash memory and the RAM, and the flash memory control circuit maps data in the flash memory into the RAM.
In one embodiment, the circuit further includes a power switch, the power switch is respectively connected to the flash memory control circuit and the flash memory, and the power switch controls power-on and power-off of the flash memory.
In one embodiment, when the microprocessor is in a standby state, the microprocessor controls the flash memory control circuit to send a first instruction to the power switch, and the power switch cuts off the power supply of the flash memory when receiving the first instruction.
In one embodiment, when the microprocessor is in a full-speed operation state, the microprocessor controls the flash memory control circuit to send a second instruction to the power switch, and the power switch turns on the flash memory to supply power when receiving the second instruction.
In one embodiment, when the microprocessor finishes the full-speed running state, the microprocessor controls the flash memory control circuit to send a first instruction to the power switch, and the power switch cuts off the power supply of the flash memory when receiving the first instruction.
In one embodiment, when the low-power-consumption circuit of the microprocessor is powered on for the first time, the power switch turns on the flash memory to supply power.
According to another aspect of the present invention, there is also provided a low power consumption circuit system of a microprocessor, comprising a microprocessor, a flash memory, a RAM random access memory, a flash memory control circuit, and a server; the flash memory is electrically connected with the microprocessor through a bus, the server is electrically connected with the microprocessor through the bus, the RAM is electrically connected with the microprocessor through the bus, the flash memory control circuit is respectively electrically connected with the microprocessor, the flash memory and the RAM, and the flash memory control circuit maps data in the flash memory into the RAM.
In one embodiment, the circuit system further includes a power switch, the power switch is respectively connected to the flash memory control circuit and the flash memory, and the power switch controls power-on and power-off of the flash memory.
According to another aspect of the present invention, there is also provided a low power consumption circuit system of a microprocessor, comprising a microprocessor, a flash memory, a RAM, a flash memory control circuit and an external device; the flash memory is electrically connected with the microprocessor through a bus, the external device is electrically connected with the microprocessor through the bus, the RAM is electrically connected with the microprocessor through the bus, the flash memory control circuit is respectively electrically connected with the microprocessor, the flash memory and the RAM, and the flash memory control circuit maps data in the flash memory into the RAM.
In one embodiment, the circuit system further includes a power switch, the power switch is respectively connected to the flash memory control circuit and the flash memory, and the power switch controls power-on and power-off of the flash memory.
According to the low-power-consumption circuit of the microprocessor, the data which needs to be frequently accessed by the microprocessor in the low-power-consumption standby state is mapped into the RAM, and the flash memory is completely powered off in the standby state, so that the power consumption of the flash memory can be reduced to zero in the standby state, the overall power consumption of the microprocessor circuit is reduced, and the aim of prolonging the standby time of the microprocessor circuit is fulfilled.
Drawings
Fig. 1 is a diagram of an application scenario of a low power consumption circuit of a microprocessor according to an embodiment of the present invention;
fig. 2 is a first schematic diagram illustrating a low power consumption circuit of a microprocessor according to an embodiment of the present invention;
fig. 3 is a second schematic diagram of a low power consumption circuit of a microprocessor according to an embodiment of the present invention;
fig. 4 is a diagram illustrating an embodiment of a low power circuit application of a microprocessor according to an embodiment of the present invention;
fig. 5 is a first schematic diagram illustrating low power circuitry of a microprocessor according to an embodiment of the present invention;
fig. 6 is a second schematic diagram of a low power circuitry of a microprocessor according to an embodiment of the present invention;
fig. 7 is a first schematic diagram illustrating low power circuitry of a microprocessor according to another embodiment of the present invention;
fig. 8 is a second schematic diagram of low power circuitry of a microprocessor according to another embodiment of the present invention.
Detailed Description
In order to make the objects, structures and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The utility model provides a microprocessor's low-power consumption circuit can be applied to the field like the low-speed low-density data information acquisition and transmission in the thing networking. Most of the implementation schemes in this kind of application fields all need to have the participation of microprocessor, fig. 1 is according to the utility model discloses an embodiment's microprocessor's low-power consumption circuit's application scene graph, microprocessor's low-power consumption circuit can be arranged in as shown in fig. 1 microcontroller, the controller includes microprocessor 10, flash memory 20, RAM30, system circuit 60 and external device 70, flash memory 20 passes through bus and microprocessor 10 electric connection, RAM30 passes through bus and microprocessor 10 electric connection, system circuit 60 passes through bus and microprocessor 10 electric connection, external device 70 passes through bus and microprocessor 10 electric connection.
In one embodiment, fig. 2 is a first schematic diagram illustrating a low power circuit of a microprocessor according to an embodiment of the present invention, as shown in fig. 2, in which the low power circuit of the microprocessor includes a microprocessor 10, a flash memory 20, a RAM30 and a flash memory control circuit 40:
the flash memory 20 is electrically connected to the microprocessor 10 via a bus, the RAM30 is electrically connected to the microprocessor 10 via a bus, and the flash memory control circuit 40 is electrically connected to the microprocessor 10, the flash memory 20, and the RAM30, respectively.
The microprocessor 10 moves or maps the general data of the flash memory 20 into the RAM30 through the flash control circuit 40. After the mapping is completed, the data exchange is performed in the RAM30, the flash memory 20 does not need to continue to work, and the microprocessor 10 turns off the power supply of the flash memory 20 through the flash memory control circuit 40. By using such a low power consumption circuit, part of the normal data is transferred or mapped to the RAM30, and the program and data are exchanged in the RAM30, so that the standby power consumption of the flash memory 20 can be reduced to zero, thereby reducing the power consumption of the circuit.
In an embodiment, fig. 3 is a schematic structural diagram of a low power consumption circuit of a microprocessor according to an embodiment of the present invention, as shown in fig. 3, in this embodiment, the low power consumption circuit of the microprocessor includes a microprocessor 10, a flash memory 20, a RAM30, a flash memory control circuit 40, and a power switch 50, the power switch 50 connects the flash memory control circuit 40 and the flash memory 20, and the power switch 50 controls power-on and power-off of the flash memory 20. When the program and data exchange are both performed in the RAM30, the microprocessor 10 controls the power switch 50 to turn off the power supply of the flash memory 20 through the flash memory control circuit 40 without the flash memory 20 continuing to operate. The direct control of the flash memory 20 by the flash memory control circuit 40 affects the stability of the flash memory control circuit 40 itself, so that a power switch 50 specially controlling the flash memory 20 is added, and the power switch 50 switches on or off the power supply of the flash memory 20 under the command of the flash memory control circuit 40. By such a low power consumption control system, the power supply of the flash memory 20 can be flexibly controlled, and the power consumption of the circuit can be reduced.
In one embodiment, when the microprocessor 10 enters the standby state, the microprocessor 10 controls the flash memory control circuit 40 to send a first command to the power switch 50, and the power switch 50 cuts off the power supply to the flash memory 20 when receiving the first command. In this embodiment, the microprocessor 10 enters a standby state, and sends a signal corresponding to the state to the flash memory control circuit 40, the flash memory control circuit 40 sends a first instruction, i.e. a power-off instruction, to the power switch 50 after receiving the signal, and the power switch 50 cuts off power supply to the flash memory 20 according to the power-off instruction.
In one embodiment, when the microprocessor 10 is in the full speed operation state, the microprocessor 10 controls the flash memory 20 control circuit to send a second command to the power switch 50, and the power switch 50 turns on the flash memory 20 to supply power when receiving the second command. In this embodiment, the microprocessor 10 enters a full-speed operating state, and sends a signal corresponding to the full-speed operating state to the flash memory control circuit 40, and the flash memory control circuit 40 sends a second instruction, i.e. a power-on instruction, to the power switch 50 after receiving the signal, and the power switch 50 switches on the power supply of the flash memory 20 according to the power-on instruction.
In one embodiment, at the end of the full speed operating state of the microprocessor 10, the microprocessor 10 controls the flash memory control circuit 40 to send a first command to the power switch 50, and the power switch 50 cuts off power to the flash memory 20 when receiving the first command. In this embodiment, the microprocessor 10 finishes the full-speed operation state, and sends a signal corresponding to the full-speed operation state to the flash memory control circuit 40, the flash memory control circuit 40 sends a first instruction, i.e. a power-off instruction, to the power switch 50 after receiving the signal, and the power switch 50 cuts off power supply to the flash memory 20 according to the power-off instruction.
In one embodiment, the power switch 50 turns on the flash memory 20 to supply power when the low power circuitry of the microprocessor 10 is first powered up. During the first power-on process, the program of the microcontroller 10 is loaded in the flash memory 20, and the microprocessor 10 completes the initialization process by reading the program instruction in the flash memory 20. After initialization is complete, microprocessor 10 moves or maps the usual data in flash memory 20 to RAM30 via flash control circuit 40. In this embodiment, the power switch 50 is powered on the flash memory 20 when the low power circuit of the microprocessor 10 is first powered up in order to complete the initialization process.
In a specific embodiment, fig. 4 is a schematic diagram of an embodiment of a low power circuit application of a microprocessor according to an embodiment of the present invention, as shown in fig. 4, during a first power-on process, a program in the microprocessor 10 is loaded in the flash memory 20, and the microprocessor 10 completes an initialization process by reading a program instruction in the flash memory 20. After initialization is complete, microprocessor 10 moves or maps the usual data in flash memory 20 memory to RAM30 via flash control circuit 40. After the mapping is completed, the subsequent program and data exchange in the standby state are performed in the RAM30, the memory of the flash memory 20 does not need to continue to work, and the microprocessor 10 controls the power switch 50 of the flash memory 20 through the flash memory control circuit 40 to turn off the power supply of the flash memory 20. With such a low power control circuit, the standby power consumption of the flash memory 20 is reduced to zero when the microprocessor 10 only needs to operate in a standby mode with lower power consumption.
The utility model relates to a pair of when low-power consumption control circuit of the microcontroller of innovation is used includes following step:
in the initial state of first power-on, the power switch 50 defaults to power on the flash memory 20, so that the microprocessor 10 completes program loading and other initialization processes through the flash memory 20 module;
after initialization is complete, microprocessor 10 unit may call flash control circuit 40 to map programs and data in flash memory 20 into RAM 30. After the mapping is completed, all program instruction operations and data exchanges of the microprocessor 10 in the standby state can be performed without the flash memory 20 module;
after the program and data in the flash memory 20 are mapped into the RAM30, the microprocessor 10 controls the flash memory control circuit 40 again to power down the flash memory 20 module through the power switch 50, and the microprocessor 10 may enter a low power standby mode.
The microprocessor 10 may perform normal detection and limited data configuration interaction by running a program in the RAM30 in the low power consumption standby mode, or may switch the microprocessor 10 into a lower sleep state and from the sleep state to the low power consumption standby state by state control, for further reducing power consumption.
When the microprocessor 10 is in the low power consumption standby mode, the microprocessor 10 needs to enter a full speed operation state by detecting the operation state or the external pin state, etc. to trigger that more data and programs need to be operated to process more complicated operations or processing requirements.
In the full speed operating state, the microprocessor 10 unit is first required to invoke the flash control circuit 40 to power up the flash memory 20 module again through the power switch 50. After the flash memory 20 is powered up again, the microprocessor 10 can call up all programs and data of the flash memory 20 to complete the processing of the service required in the full-speed operation state.
When the traffic processing is completed in the full speed operating state, the microprocessor 10 may again power down the flash memory 20 module through the power switch 50. And the MCU returns to the low-power consumption standby state again, so that the standby power consumption of the micro-control processor is saved.
With such a microcontroller low power control circuit, after the power-on loading of the memory of flash memory 20 is completed, the part of the program and data that needs to be accessed most frequently in the standby condition is mapped into RAM30 by flash control circuit 40. After the mapping is completed, the power of the flash memory 20 is powered down by the flash memory control circuit 40. Subsequent main operations in the standby state of the microprocessor 10 are performed in the RAM30, so that after the power down of the flash memory 20 is completed, the power consumption of the flash memory 20 can be further reduced to zero power consumption in the standby state, and only when the microprocessor 10 needs to run at full speed, the flash memory 20 needs to be powered up again and other data or programs in the memory of the flash memory 20 are run. This design can significantly reduce the overall power consumption of the microprocessor 10 to the target of extender standby time in applications where the low power standby time of the microprocessor 10 is much greater than the time for full speed operation.
According to another aspect of the present invention, there is provided a low power circuit system of a microprocessor, fig. 5 is a schematic structural diagram of the low power circuit system of the microprocessor according to an embodiment of the present invention, as shown in fig. 5, the system includes: microprocessor 10, flash memory 20, RAM30, flash control circuit 40, and server 80. Microprocessor 10 moves or maps the data normally in flash memory 20 to RAM30 memory through flash control circuit 40. After the mapping is completed, data exchange is performed in the RAM30, and when no data interaction exists between the server 80 and the microprocessor 10 or only the RAM30 is used for data interaction, the microprocessor 10 does not need to continue operating the flash memory 20, and the power supply of the flash memory 20 is turned off by the flash memory control circuit 40. By using the low power consumption circuit system, part of the common data in the flash memory 20 is moved or mapped to the RAM30, and data exchange is performed in the RAM30, so that the standby power consumption of the flash memory 20 can be reduced to zero, and the power consumption of the circuit can be reduced.
In an embodiment, fig. 6 is a schematic structural diagram of a low power circuit system of a microprocessor according to an embodiment of the present invention, as shown in fig. 6, a power switch 50 specially controlling the flash memory 20 is added to the low power circuit system of the microprocessor, and the power switch 50 switches on or off the power supply of the flash memory 20 under the command of the flash memory control circuit 40. By the low power consumption control circuit system, the power supply of the flash memory 20 can be flexibly controlled according to the interaction state between the server 80 and the microprocessor 10, and the power consumption of the circuit is reduced.
According to another aspect of the present invention, there is provided a low power circuit system of a microprocessor, fig. 7 is a schematic structural diagram of the low power circuit system of the microprocessor according to another embodiment of the present invention, as shown in fig. 7, the system includes: microprocessor 10, flash memory 20, RAM30, flash control circuit 40, and external device 70. Microprocessor 10 moves or maps the data normally in flash memory 20 to RAM30 memory through flash control circuit 40. After the mapping is completed, data exchange is performed in the RAM30, and when there is no data interaction between the external device 70 and the microprocessor 10 or the data interaction is performed only with the RAM30, the flash memory 20 does not need to continue to operate, and the microprocessor 10 turns off the power supply of the flash memory 20 through the flash memory control circuit 40. By using the low-power-consumption circuit system, part of the common data in the flash memory 20 is moved or mapped to the RAM30, and data exchange is only performed in the RAM30, so that the standby power consumption of the flash memory 20 can be reduced to zero, and the power consumption of the circuit can be reduced.
In an embodiment, fig. 8 is a schematic diagram of a second structure of the low power circuit system of the microprocessor according to another embodiment of the present invention, as shown in fig. 8, a power switch 50 specially controlling the flash memory 20 is added to the low power circuit system of the microprocessor, and the power switch 50 switches on or off the power supply of the flash memory 20 under the command of the flash memory control circuit 40. By the low power consumption control circuit system, the power supply of the flash memory 20 can be flexibly controlled according to the interaction state between the external device 80 and the microprocessor 10, and the power consumption of the circuit is reduced.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A low power consumption circuit of a microprocessor is characterized by comprising the microprocessor, a flash memory, a RAM random access memory and a flash memory control circuit; the flash memory is electrically connected with the microprocessor through a bus, the RAM is electrically connected with the microprocessor through the bus, the flash memory control circuit is respectively electrically connected with the microprocessor, the flash memory and the RAM, and the flash memory control circuit maps data in the flash memory into the RAM.
2. The low power consumption circuit of claim 1, further comprising a power switch, wherein the power switch is connected to the flash memory control circuit and the flash memory, respectively, and the power switch controls the flash memory to be powered on and off.
3. The low power consumption circuit of claim 2, wherein when the microprocessor is in a standby state, the microprocessor controls the flash memory control circuit to send a first command to the power switch, and the power switch cuts off power to the flash memory when receiving the first command.
4. The low power consumption circuit of claim 2, wherein when the microprocessor is in a full speed operating state, the microprocessor controls the flash control circuit to send a second command to the power switch, and the power switch turns on the flash power supply when receiving the second command.
5. The low power consumption circuit of claim 4, wherein when the microprocessor is at the end of a full speed operating state, the microprocessor controls the flash control circuit to send a first command to the power switch, and the power switch cuts off power to the flash memory when receiving the first command.
6. The low power consumption circuit of claim 2, wherein the power switch turns on the flash memory to supply power when the low power consumption circuit of the microprocessor is powered on for the first time.
7. A low-power circuit system of a microprocessor is characterized by comprising the microprocessor, a flash memory, a RAM random access memory, a flash memory control circuit and a server; the flash memory is electrically connected with the microprocessor through a bus, the server is electrically connected with the microprocessor through the bus, the RAM is electrically connected with the microprocessor through the bus, the flash memory control circuit is respectively electrically connected with the microprocessor, the flash memory and the RAM, and the flash memory control circuit maps data in the flash memory into the RAM.
8. The low power circuitry of claim 7, wherein said circuitry further comprises a power switch, said power switch being connected to said flash memory control circuit and said flash memory, respectively, said power switch controlling powering up and powering down of said flash memory.
9. A low-power consumption circuit system of a microprocessor is characterized by comprising the microprocessor, a flash memory, a RAM random access memory, a flash memory control circuit and an external device; the flash memory is electrically connected with the microprocessor through a bus, the external device is electrically connected with the microprocessor through the bus, the RAM is electrically connected with the microprocessor through the bus, the flash memory control circuit is respectively electrically connected with the microprocessor, the flash memory and the RAM, and the flash memory control circuit maps data in the flash memory into the RAM.
10. The low power circuitry of claim 9, wherein said circuitry further comprises a power switch, said power switch being connected to said flash memory control circuit and said flash memory, respectively, said power switch controlling powering up and powering down of said flash memory.
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| CN201921914557.0U CN211827190U (en) | 2019-11-07 | 2019-11-07 | Low power consumption circuit and circuit system for microprocessor |
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| CN201921914557.0U CN211827190U (en) | 2019-11-07 | 2019-11-07 | Low power consumption circuit and circuit system for microprocessor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114698072B (en) * | 2022-03-21 | 2024-04-26 | 沈阳中科奥维科技股份有限公司 | Low-power-consumption circuit of WIA-PA wireless vibration transmitter and control method |
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2019
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114698072B (en) * | 2022-03-21 | 2024-04-26 | 沈阳中科奥维科技股份有限公司 | Low-power-consumption circuit of WIA-PA wireless vibration transmitter and control method |
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