CN211791473U

CN211791473U - Integrator, touch capacitance detection circuit and intelligent device

Info

Publication number: CN211791473U
Application number: CN202020314166.1U
Authority: CN
Inventors: 吴红兵; 乔爱国
Original assignee: Chipsea Technologies Shenzhen Co Ltd
Current assignee: Chipsea Technologies Shenzhen Co Ltd
Priority date: 2020-03-13
Filing date: 2020-03-13
Publication date: 2020-10-27
Anticipated expiration: 2030-03-13

Abstract

The embodiment of the utility model provides an integrator, touch capacitance detection circuit and smart machine, the integrator includes integrating circuit, first switch electric capacity circuit and second switch electric capacity circuit; wherein the integrating circuit comprises an input end; one end of the first switched capacitor circuit is connected with the input end of the integrating circuit, the other end of the first switched capacitor circuit is used for receiving an input signal, the first switched capacitor circuit is also used for connecting a detection pin, and the first switched capacitor circuit and the integrating circuit form a first switched capacitor integrating circuit; and one end of the second switched capacitor circuit is connected with the input end of the integrating circuit, the other end of the second switched capacitor circuit is used for receiving an input signal, the second switched capacitor circuit and the integrating circuit form a second switched capacitor integrating circuit, and the integrating directions of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit are opposite. The utility model provides an integrator can carry out the multiple integral with the integral capacitance of less capacitance value, need not to increase off-chip electric capacity, reduce cost.

Description

Integrator, touch capacitance detection circuit and intelligent device

Technical Field

The utility model relates to a touch button technical field, concretely relates to integrator, touch electric capacity detection circuitry and smart machine.

Background

Through technical evolution and mass production inspection for many years, the touch key technology is mature day by day. Due to the advantages of convenience, fashion, low cost, and the like, more and more electronic products are turning from traditional mechanical keys to touch keys. The touch key judges the occurrence of a touch event by detecting the capacitance change on the key through the capacitance detection chip, and the capacitance change on the detection pin of the capacitance detection chip can be caused by the capacitance change of the key, so that the touch event is detected.

However, due to the influence of the inherent capacitance on the detection pins, when the capacitance on the detection pins changes, the integration frequency of the integral capacitance inside the capacitance detection chip is reduced, so that when the inherent capacitance on the detection pins is large, the small capacitance change is difficult to detect. However, the addition of off-chip capacitance increases the cost of the system accordingly, and thus, improvements in the prior art are needed.

SUMMERY OF THE UTILITY MODEL

In view of the above problem, the utility model provides a touch electric capacity detection circuitry and smart machine can carry out the integral many times with the integral capacitance of less electric capacity value to need not to increase off-chip electric capacity, reduce cost.

The embodiment of the utility model provides an adopt following technical scheme to realize:

an integrator comprises an integrating circuit, a first switch capacitor circuit and a second switch capacitor circuit; wherein the integrating circuit comprises an input end; one end of the first switched capacitor circuit is connected with the input end of the integrating circuit, the other end of the first switched capacitor circuit is used for receiving an input signal, the first switched capacitor circuit is also used for connecting a detection pin, and the first switched capacitor circuit and the integrating circuit form a first switched capacitor integrating circuit; and one end of the second switched capacitor circuit is connected with the input end of the integrating circuit, the other end of the second switched capacitor circuit is used for receiving an input signal, the second switched capacitor circuit and the integrating circuit form a second switched capacitor integrating circuit, and the integrating directions of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit are opposite.

In some embodiments, the input terminal includes a first input terminal and a second input terminal, the first switched capacitor circuit and the second switched capacitor circuit are connected to the first input terminal, and the second input terminal is connected to ground.

In some embodiments, the first switched capacitor circuit includes a first capacitor, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, a first end of the first capacitor receives an input signal through the first switch and the second switch which are sequentially connected in series, the first end of the first capacitor is further grounded through the third switch, a second end of the first capacitor is connected to the first input end of the integrating circuit through the fourth switch, the second end of the first capacitor is further grounded through the fifth switch, and a connection node of the first switch and the second switch is used for connecting the detection pin; the second switch capacitor circuit comprises a second capacitor, a sixth switch, a seventh switch, an eighth switch and a capacitor array, wherein the first end of the second capacitor receives an input signal through the fifth switch and the sixth switch which are sequentially connected in series, the second end of the second capacitor is connected with the first input end of the integrating circuit through the seventh switch, the first end of the capacitor array is connected between the sixth switch and the seventh switch, and the second end of the capacitor array is grounded.

In some embodiments, the input terminal comprises a first input terminal and a second input terminal, the first switched-capacitor circuit comprises a first sub-switched-capacitor circuit and a second sub-switched-capacitor circuit; the second switched capacitor circuit comprises a third sub-switched capacitor circuit, a fourth sub-switched capacitor circuit and a capacitor array; the integrator further comprises a first switch and a second switch; one end of the first sub-switched capacitor circuit is connected to the first input end, the other end of the first sub-switched capacitor circuit is connected to the fourth sub-switched capacitor circuit, and the other end of the fourth sub-switched capacitor circuit is connected to the second input end; the first connecting node of the first sub-switched capacitor circuit and the fourth sub-switched capacitor circuit is used for receiving an input signal through the first switch; the first connecting node is also used for connecting a detection pin; one end of the second sub-switched capacitor circuit is connected to the second input end, the other end of the second sub-switched capacitor circuit is connected to the third sub-switched capacitor circuit, and the other end of the third sub-switched capacitor circuit is connected to the first input end; a second connection node of the second sub-switched capacitor circuit and the third sub-switched capacitor circuit is used for receiving an input signal through a second switch; the second connecting node is also connected to one end of the capacitor array, and the other end of the capacitor array is grounded.

In some embodiments, the first switched-capacitance integrator circuit is an in-phase switched-capacitance integrator circuit and the second switched-capacitance integrator circuit is an inverting switched-capacitance integrator circuit; or the first switched-capacitor integrating circuit is an inverted switched-capacitor integrating circuit, and the second switched-capacitor integrating circuit is an in-phase switched-capacitor integrating circuit.

In some embodiments, the integrator further comprises a reset switch connected between the input and the output of the integration circuit.

In some embodiments, the capacitor array includes a plurality of capacitors connected in parallel with each other.

The utility model also provides a touch capacitance detection circuit, including the integrator as in any above, touch capacitance detection circuit still includes detection pin and excitation signal source; the detection pin is connected with the first switch capacitor circuit; the excitation signal source is connected with the first switch capacitor circuit and the second switch capacitor circuit and is used for outputting input signals.

In some embodiments, the touch capacitance detection circuit further includes a clock generation circuit, and the clock generation circuit is respectively connected to the first switched capacitance circuit and the second switched capacitance circuit.

The embodiment of the utility model provides a still provide an intelligent equipment, including sensor and as above-mentioned arbitrary touch capacitance detection circuit, wherein the sensor is connected with the detection pin.

Compared with the prior art, the embodiment of the utility model provides an integrator, touch electric capacity detection circuitry and smart machine, through setting up first switch capacitance volume integrating circuit and the second switch capacitance integrating circuit of integration opposite direction, eliminate because the influence of inherent electric capacity and the voltage of extra accumulation when integrating at every turn of integrating electric capacity, and then can carry out the multiple integration with the integrating electric capacity of less capacity value to effectively increase the integration number of times of integrating electric capacity under the condition that does not adopt the outer electric capacity of piece, reduce cost. Meanwhile, after the extra accumulated voltage of the integration capacitor during each integration is eliminated, the voltage accumulated by the integration capacitor each time is kept consistent, so that the signal-to-noise ratio of the system and the accuracy of capacitance detection are improved.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 shows a schematic diagram of a capacitance sensing system according to an embodiment of the present invention.

Fig. 2 shows a schematic circuit structure diagram of an integrator according to an embodiment of the present invention.

Fig. 3 is a schematic diagram illustrating another circuit structure of an integrator according to an embodiment of the present invention.

Fig. 4 is a schematic diagram illustrating signal waveforms of non-overlapping clock signals according to an embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating another circuit structure of an integrator according to an embodiment of the present invention.

Fig. 6 shows a schematic structural diagram of a touch capacitance detection circuit provided by an embodiment of the present invention.

Fig. 7 shows a schematic structural diagram of an intelligent device provided by an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

The existing capacitive touch technology can be classified into Self-Capacitance (Self-Capacitance) and Mutual-Capacitance (Mutual-Capacitance). The current self-contained detection technology mainly has two realization modes:

1. charging and discharging the capacitor by using a pull-up resistor or current, and realizing capacitor key detection according to the difference of system time constants;

2. based on the charge sharing principle, capacitance information is converted into a pull-up resistor or a pull-down resistor, and the obtained voltage or current signal is processed by a signal processing circuit.

However, due to the influence of the inherent capacitance on the detection pins, the integral frequency of the integral capacitance inside the capacitance detection chip is reduced, and when the inherent capacitance on the detection pins is large, the small capacitance change is difficult to detect.

In order to solve the above problem, the inventor has studied for a long time, provided the embodiment of the present invention provides an integrator, a touch capacitance detection circuit and a smart device, wherein the integrator, the touch capacitance detection circuit and the smart device are arranged in a first switch capacitance integration circuit and a second switch capacitance integration circuit which are opposite in integration direction, so that an extra accumulated voltage is eliminated when the integration capacitance is integrated at each time due to the influence of the inherent capacitance, and then the integration capacitance with a smaller capacitance value can be integrated for multiple times, thereby effectively increasing the integration times of the integration capacitance without adopting an off-chip capacitance, and reducing the circuit area and the cost. Meanwhile, after the extra accumulated voltage of the integration capacitor during each integration is eliminated, the voltage accumulated by the integration capacitor each time is kept consistent, so that the signal-to-noise ratio of the system and the accuracy of capacitance detection are improved.

In order to make the technical field person understand the scheme of the present invention better, the following will combine the drawings in the embodiments of the present invention to perform clear and complete description on the technical scheme in the embodiments of the present invention. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, fig. 1 schematically illustrates a capacitance sensing system 10 provided by an embodiment of the present invention. The system 10 includes an Excitation Source (Excitation Source)11, a Capacitor-to-Voltage Converter (CVC) unit 12, and an Analog Signal Process (ASP) unit 13, which are connected in sequence. The CVC unit 12 includes, among other things, a detection pin TK coupled to an external sensor 20, which sensor 20 may be a capacitive sensor. When a touch event occurs on the sensor 20, which causes a change in capacitance at the detection pin TK, the CVC unit 12 in turn receives an input signal Vin, which is in fact a capacitive signal. The CVC unit 12 converts the capacitance signal into a voltage signal and outputs a signal Vout, the ASP unit 13 quantizes the output signal Vout, and the ASP unit 13 is connected to an external determination circuit 30 so that the external determination circuit 30 determines the occurrence of the touch event based thereon. Specifically, when no touch event occurs, the ASP unit 13 outputs a reference signal, and the determination circuit 30 records the reference signal; the determination circuit 30 simultaneously detects the current signal output by the ASP unit, and determines whether a touch event occurs at the time according to a voltage difference between the current signal and the reference signal, for example, when the voltage difference between the current signal and the reference signal is higher than a preset threshold, it may be determined that the touch event occurs at the time. The embodiment of the utility model provides an in, the electric capacity variation volume that arouses on detecting pin TK is hereinafter referred to as touch electric capacity Ctk because of the touch event.

The ASP unit 13 may be, but is not limited to, an Analog-to-Digital Converter (ADC), a comparator, and a Voltage Controlled Oscillator (VCO). the ASP unit 13 may be selected based on the requirement of an Analog back-end circuit, and is not limited herein.

It should be noted that due to the capacitive coupling effect in the circuit, there is a coupled inherent capacitance Cpin on the detection pin TK, and the inherent capacitance Cpin may reduce the signal-to-noise ratio of the system and cause an influence in the signal conversion process of the CVC unit 12.

As shown in fig. 2, based on the capacitance sensing system 10, the embodiment of the invention provides an integrator 100, where the integrator 100 is specifically applied to the CVC unit, and is used to convert a capacitance signal into a voltage signal for output.

Integrator 100 includes a first switched-capacitor circuit 110, a second switched-capacitor circuit 120, and an integrating circuit 130. The integrating circuit 130 includes an input terminal and an output terminal. The first switched-capacitor circuit 110 has one end connected to the input end of the integrating circuit 130 and the other end for receiving an input signal, and the first switched-capacitor circuit 110 is further connected to an external detection pin TK and forms a first switched-capacitor integrating circuit with the integrating circuit 130. One end of the second switched-capacitor circuit 120 is connected to the input end of the integration circuit 130, and the other end is used for receiving an input signal, and the second switched-capacitor circuit 120 and the integration circuit 130 form a second switched-capacitor integration circuit. The integration directions of the first switched capacitor integration circuit and the second switched capacitor integration circuit are opposite.

In this embodiment, when the external sensor generates a touch event, the external detection pin TK generates a touch capacitance Ctk, and outputs a signal Vout at the output terminal of the integrating circuit 130 through the integrating action of the first switched-capacitor integrating circuit. Further, when the external sensor does not generate a touch event, the first switched capacitor integrating circuit integrates the inherent capacitance Cpin due to the inherent capacitance Cpin of the detection pin TK, so that the voltage is already accumulated in the integrating circuit 130 when the touch event does not occur, and the voltage accumulated in the integrating circuit 130 is limited, which results in reducing the number of times of integration of the first switched capacitor circuit 110 when the external sensor generates the touch event. When the first switched-capacitor integrating circuit integrates, the touch capacitor Ctk and the inherent capacitor Cpin are integrated at the same time, and at this time, the voltage accumulated by the integrating circuit 130 in a single period is greater than the voltage accumulated when only the touch capacitor Ctk is integrated, so that the integration frequency of the first switched-capacitor integrating circuit is further reduced, and meanwhile, the voltage difference between the two ends of the integrating circuit 130 and the integration frequency form a nonlinear relationship, and the signal-to-noise ratio of the system is reduced.

The embodiment of the utility model provides an integrator sets up first switch capacitance integrated circuit and the integrated circuit of second switch capacitance that integration direction is opposite, the phase place at integrated circuit 130 both ends accumulative voltage U2 when the integrated circuit of second switch capacitance is integrated with first switch capacitance integrated circuit when the phase place at integrated circuit 130 both ends accumulative voltage U1 is opposite, thereby offset because inherent electric capacity Cpin's influence and at the extra accumulated voltage in integrated circuit 130 both ends, can eliminate the influence that inherent electric capacity Cpin brought completely even. Then, under the same condition of the integrating circuit 130, the integrating times can be effectively increased, so that off-chip capacitance is not needed, and the cost is reduced. Meanwhile, after the influence of the inherent capacitance Cpin is eliminated, the voltages accumulated at the two ends of the integrating circuit 130 at each time are kept consistent, so that the linear relation between the voltage difference at the two ends of the integrating circuit 130 and the integration times is ensured, and the signal-to-noise ratio and the detection precision of the system are improved. In addition, in the embodiment, the first switched capacitor circuit and the second switched capacitor circuit are driven simultaneously by one input signal, so that the structure of a preceding stage circuit can be simplified, the circuit design cost is reduced, and the system loss is reduced.

Optionally, the first switched-capacitor integrator circuit is an in-phase switched-capacitor integrator circuit, and the second switched-capacitor integrator circuit is an anti-phase switched-capacitor integrator circuit. Or, the first switched-capacitor integrating circuit is an inverse-phase switched-capacitor integrating circuit, and the second switched-capacitor integrating circuit is an in-phase switched-capacitor integrating circuit.

Alternatively, the integrator 100 may detect the change in capacitance in a single-ended or differential detection manner. The integrator 100 generally has two input terminals, and the single-ended detection means that one input terminal of the integrating circuit 130 is connected to the first switched capacitor circuit 110 and the second switched capacitor circuit 120, and the other input terminal of the integrating circuit 130 is used for grounding or connecting to a preset reference voltage source. In contrast, differential detection means that both input terminals of the integrating circuit 130 are connected to the first switched-capacitor circuit 110 and the second switched-capacitor circuit 120 described above. Of course, the detection method is not limited to single-ended detection and differential detection, and it is understood that the present invention is not limited to the single-ended detection and the differential detection.

In some embodiments, the integrator 100 detects the change in capacitance in a single-ended detection manner. Specifically, the input terminal of the integrating circuit 130 includes a first input terminal and a second input terminal, the first switched-capacitor circuit 110 and the second switched-capacitor circuit 120 are connected to the first input terminal, and the second input terminal is grounded.

As an example of the single-ended detection method, as shown in fig. 2, the first switched capacitor circuit 110 includes a first capacitor C1, a first switch SA1, a second switch SA2, a third switch SA3, a fourth switch SA4, and a fifth switch SA5, a first end of the first capacitor C1 receives the input signal Vs through the first switch SA1 and the second switch SA2 which are sequentially connected in series, a first end of the first capacitor C1 is further grounded through the third switch SA3, a second end of the first capacitor C1 is connected to a first input terminal of the integrating circuit 130 through the fourth switch SA4, a second end of the first capacitor C1 is further grounded through the fifth switch SA5, and a connection node between the first switch SA1 and the second switch SA2 is used for connecting the detection pin TK. The second switched-capacitor circuit 120 includes a second capacitor C2, a sixth switch SA6, a seventh switch SA7, an eighth switch SA8, and a capacitor array Cref, a first end of the second capacitor C2 receives the input signal Vs through a sixth switch SA6 and a seventh switch SA7 which are sequentially connected in series, a second end of the second capacitor C2 is connected to a first input end of the integrating circuit 130 through a seventh switch SA7, a first end of the capacitor array Cref is connected between the sixth switch SA6 and the seventh switch SA7, and a second end of the capacitor array Cref is grounded. The integration circuit 130 includes a comparator a1 and an integration capacitor Cint connected between the input and output terminals of the comparator a 1.

The switches (SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8) are electronic switches, which may be, but not limited to, a triode, a MOS transistor, and a thyristor. The switches (SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8) are controlled by a set of external non-overlapping clock signals (Ph1, Ph2), i.e. the clock signal Ph1 and the clock signal Ph2 cannot be high at the same time.

In one embodiment, the first switched-capacitor integration circuit may be an in-phase switched-capacitor integration circuit and the second switched-capacitor integration circuit may be an inverted switched-capacitor integration circuit. Specifically, the second switch SA2, the third switch SA3, the fourth switch SA4, the seventh switch SA7, and the eighth switch SA8 are first phase switches; the first switch SA1, the fifth switch SA5, and the sixth switch SA6 are second phase switches, and the first phase switches and the second phase switches are alternately turned on in one period of the integration circuit 130. Wherein the first phase switch may be controlled by a clock signal Ph1 and the second phase switch may be controlled by a clock signal Ph 2. The voltage accumulated across the integrating capacitor Cint by the first switched-capacitor circuit 110 in a single clock cycle is positive by the non-overlapping clock signals (Ph1, Ph 2); the voltage accumulated across the integrating capacitor Cint by the second switched-capacitor circuit 120 during a single clock cycle is negative. Since the second switched-capacitor circuit 120 is opposite to the voltage accumulated across the integrating capacitor Cint by the first switched-capacitor circuit 110, the voltage additionally accumulated across the integrating capacitor Cint due to the influence of the inherent capacitance Cpin can be cancelled. Further, the capacitor array Cref in the second switched capacitor circuit 120 includes a plurality of capacitors connected in parallel, and the capacitors can be adapted to the inherent capacitor Cpin on the detection pin TK through the capacitors, so as to greatly offset the influence of the inherent capacitor Cpin, and under an ideal condition without considering system noise, the influence of the inherent capacitor Cpin can be completely eliminated, thereby effectively increasing the number of integration times, without using an off-chip capacitor, and achieving the same number of integration times with a smaller circuit area, thereby reducing the circuit area and lowering the cost. Meanwhile, after the influence of the inherent capacitance Cpin is eliminated, the voltages accumulated at the two ends of the integrating circuit 130 at each time are kept consistent, so that the linear relation between the voltage difference at the two ends of the integrating circuit 130 and the integration times is ensured, and the signal-to-noise ratio and the detection precision of the system are improved.

In another embodiment, the first switched-capacitor integration circuit may be an inverting switched-capacitor integration circuit and the second switched-capacitor integration circuit may be an non-inverting switched-capacitor integration circuit. Specifically, the integration directions of the first switched-capacitor integrating circuit and the second switched-capacitor integrating circuit can be changed by changing the phases of the clock signals controlled by the switches (SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA 8). In some embodiments, the structures of the first switched-capacitor circuit 110 and the second switched-capacitor circuit 120 may be exchanged to change the integration directions of the first switched-capacitor integration circuit and the second switched-capacitor integration circuit. For example, as shown in fig. 3, the first switched capacitor circuit 110 may include a first capacitor C1, a sixth switch SA6, a seventh switch SA7 and an eighth switch SA8, a first end of the first capacitor C1 sequentially receives the input signal Vs through a sixth switch SA6 and a seventh switch SA7 connected in series, a second end of the first capacitor C1 is connected to a first input end of the integrating circuit 130 through the eighth switch SA8, and a connection node of the sixth switch SA6 and the seventh switch SA7 is used for connecting the detection pin TK; the second switched capacitor circuit 120 includes a second capacitor C2, a first switch SA1, a second switch SA2, a third switch SA3, a fourth switch SA4, a fifth switch SA5, and a capacitor array Cref, a first end of the second capacitor C2 is connected to the first switch SA1 and the second switch SA2 in series in sequence and then receives the input signal Vs, a first end of the second capacitor C2 is further grounded through the third switch SA3, a second end of the second capacitor C2 is connected to the first input end of the integrating circuit 130 through the fourth switch SA4, a second end of the second capacitor C2 is further grounded through the fifth switch SA5, a first end of the capacitor array Cref is connected between the first switch SA1 and the second switch SA2, and a second end of the capacitor array SA Cref is grounded. The principle of using the first switched-capacitor integrating circuit as an inverse-phase switched-capacitor integrating circuit and the second switched-capacitor integrating circuit as an in-phase switched-capacitor integrating circuit is consistent with the principle of using the first switched-capacitor integrating circuit as an in-phase switched-capacitor integrating circuit and the second switched-capacitor integrating circuit as an inverse-phase switched-capacitor integrating circuit, and the description is omitted here for brevity.

Hereinafter, the principle of the embodiment of the present invention will be described in detail with reference to fig. 2 and 4 by taking the first switched-capacitor integrating circuit as the in-phase switched-capacitor integrating circuit and the second switched-capacitor integrating circuit as the reversed-phase switched-capacitor integrating circuit as examples. Fig. 4 is a schematic diagram of signal waveforms of the clock signal Ph1 and the clock signal Ph 2.

Clock signal Ph1 and clock signal Ph2 alternate high at different time periods within the same cycle. T0 to T2 are the first clock cycle T1 of the clock signals (Ph1, Ph2), and T2 to T4 are the second clock cycle T2 of the clock signals (Ph1, Ph 2). The clock signal Ph1 controls on and off of the second switch SA2, the third switch SA3, the fourth switch SA4, the seventh switch SA7 and the eighth switch SA 8. When the clock signal Ph1 is at a high level (t 0-t 1, t 2-t 3), the second switch SA2, the third switch SA3, the fourth switch SA4, the seventh switch SA7 and the eighth switch SA8 are turned on simultaneously; when the clock signal Ph1 is at a low level (t1 to t2, t3 to t4), the second switch SA2, the third switch SA3, the fourth switch SA4, the seventh switch SA7, and the eighth switch SA8 are turned off at the same time. The clock signal Ph2 controls on and off of the first switch SA1, the fifth switch SA5, and the sixth switch SA 6. When the clock signal Ph2 is at a high level (t 1-t 2, t 3-t 4), the first switch SA1, the fifth switch SA5 and the sixth switch SA6 are turned on simultaneously; when the clock signal Ph2 is at a low level (t0 to t1, t2 to t3), the first switch SA1, the fifth switch SA5, and the sixth switch SA6 are turned off at the same time.

The input signal Vs is an external signal and can be generated by an external excitation signal source. An external detection pin TK is connected between the first switch SA1 and the second switch SA2, and the external detection pin TK corresponds to an inherent capacitance Cpin connected with the detection pin TK.

When no touch event occurs, in the first clock period T1, the second switch SA2 is turned on and the first switch SA1 is turned off in the period from T0 to T1. The input signal Vs charges the inherent capacitance Cpin on the detection pin TK and the capacitance in the capacitor array Cref, so that the inherent capacitance Cpin and the capacitance in the capacitor array Cref accumulate charges. In the stage t 1-t 2, the second switch SA2 is turned off, the first switch SA1 is turned on, the third switch SA3 is turned off, the fifth switch SA5 is turned on, and the fourth switch SA4 is turned off. At this time, the inherent capacitance Cpin is connected to the first capacitance C1, and the inherent capacitance Cpin transfers part of the accumulated charges to the capacitance C1. Meanwhile, in the period from t0 to t1, the seventh switch SA7 and the eighth switch SA8 are turned on, and the sixth switch SA6 is turned off. The input signal Vs charges the capacitances in the capacitor array Cref. In the period from t1 to t2, the sixth switch SA6 is turned on, the seventh switch SA7 and the eighth switch SA8 are turned off, and the capacitor in the capacitor array Cref transfers charges to the second capacitor C2.

In the second clock period T2, during the period T2-T3, the second switch SA2 and the seventh switch SA7 are turned back on, the input signal Vs charges the inherent capacitor Cpin and the capacitor in the capacitor array Cref again, at the same time, the third switch SA3 and the fourth switch SA4 are turned on, the fifth switch SA5 is turned off, the first capacitor C1 is connected to the integrating capacitor Cint, and the charges accumulated in the period T1-T2 of the previous clock period T1 are transferred to the integrating capacitor Cint, so that the voltage is accumulated across the integrating capacitor Cint. At this time, even in the absence of a touch event, a voltage is accumulated across the integrating capacitor Cint due to the existence of the inherent capacitance Cpin. At this time, in a single period, the voltage V accumulated across the integrating capacitor Cint due to the influence of the inherent capacitance Cpin₁Comprises the following steps:

wherein, C₁Is the capacitance value of the first capacitance C1; c_intIs the capacitance value of the integrating capacitor Cint; c_pinIs the capacitance value of the intrinsic capacitance Cpin; v_sIs the voltage value of the input signal Vs.

Meanwhile, in the stage T2 to T3, the eighth switch SA8 is turned on, the sixth switch SA6 is turned off, the second capacitor C2 is connected to the integrating capacitor Cint, and the charges accumulated in the period T1 to T2 of the previous clock period T1 are transferred to the integrating capacitor Cint, so that the voltages are accumulated at the two ends of the integrating capacitor Cint. At this time, in a single period, the voltage V accumulated across the integrating capacitor Cint due to the capacitances in the capacitor array Cref₂Comprises the following steps:

wherein, C₂Is the capacitance value of the second capacitor C2; c_refIs the capacitance value adapted by the capacitance array Cref.

Then the total voltage av accumulated across the integrating capacitor Cint in a single clock cycle is V₁And V₂And (4) summing. That is to say

Therefore, as can be seen from the above equation, the voltage accumulated across the integrating capacitor Cint due to the influence of the inherent capacitor Cint is cancelled and reduced. In fact, the capacitance values of the first capacitor C1 and the second capacitor C3 are controllable when C is₁＝C₂＝C_iIn time, the above equation can be simplified as:

as can be seen from the above formula, when C_ref＝C_pinAt this time, the total voltage Δ V accumulated across the integration capacitor Cint is zero. That is, when there is no touch event, no voltage is accumulated across the integrating capacitor Cint, completely eliminating the influence of the inherent capacitor Cint. The capacitance value C of the inherent capacitance Cpin_pinCapacitance value C of the first capacitor C1 and the second capacitor C2_iVoltage V of input signal Vs_sAre controllable, so that in case the capacitor array Cref and the intrinsic capacitance Cpin are fully adapted, the voltage accumulated across the integrating capacitor due to the influence of the intrinsic capacitance Cint can be completely eliminated.

When a touch event occurs, a touch capacitance Ctk is generated on the detection pin TK, and the total voltage Δ V accumulated at the two ends of the integration capacitance Cint at this time can be derived according to the above principle as follows:

wherein, C_tkIs the capacitance value of the touch capacitance Ctk.

C is to be_ref＝C_pinSubstituting the above formula, one can obtain:

at this time, Δ V and C can be defined_tkThe functional relationship of (A) is as follows:

wherein F (x) is represented by Δ V; x is represented by C_tk(ii) a A is represented by C_pin(ii) a B is 2C_i。

Derivation of the above equation yields:

by derivation

Constant positive, i.e., F (x) is an increasing function. Indicating that the larger the touch capacitance Ctk, the more charge is accumulated on the integration capacitance Cint in a single cycle, and thus the more easily a touch event is detected.

Through the analysis above, the embodiment of the utility model provides an integrator can offset because inherent electric capacity Cpin's influence and at the extra accumulated voltage in integral capacitance Cint both ends, and then effectual increase integral number of times need not to adopt the off-chip electric capacity to can reach the same integral number of times with littleer circuit area, and then build reduction circuit area, reduce cost. Meanwhile, after the influence of the inherent capacitance Cpin is eliminated, the voltages accumulated at the two ends of the integrating circuit 130 at each time are kept consistent, so that the linear relation between the voltage difference at the two ends of the integrating circuit 130 and the integrating times is ensured, and the signal-to-noise ratio and the detection precision of the system are improved.

Whereas for a touch event, the presence of the inherent capacitance Cpin makes the touch event more difficult to detect, since the larger the inherent capacitance Cpin, the smaller the amount of capacitance change on the detection pin TK when the touch event causes a touch capacitance Ctk. For example, assuming that the touch capacitances Ctk are all 50 μ F, the amount of change Δ 1 of the output signal Vout when integrating by superimposing the touch capacitances Ctk on the basis of the specific capacitance of 100 μ F is smaller than the amount of change Δ 2 of the output signal Vout when integrating by superimposing the touch capacitances of the same magnitude on the basis of the specific capacitance of 50 μ F. The embodiment of the utility model provides an integrator 100 is because eliminated the influence of inherent electric capacity Cpin for when touch electric capacity Ctk produced, the relative variation is bigger, and touch electric capacity Ctk is big more, and the electric charge that accumulates on integral electric capacity Cint in single cycle is also more, therefore the touch event is detected more easily.

In some embodiments, the integrator 100 may detect the change in capacitance in a differential sense. As shown in fig. 5, the input terminals of the integrating circuit 130 include a first input terminal and a second input terminal; the first switched capacitor circuit comprises a first sub-switched capacitor circuit 111 and a second sub-switched capacitor circuit 112; the second switched-capacitor circuit comprises a third sub-switched-capacitor circuit 121, a fourth sub-switched-capacitor circuit 122 and a capacitor array Cref; the integrator 100 further includes a first switch SA1 and a second switch SA 2. One end of the first sub-switched capacitor circuit 111 is connected to the first input end of the integrating circuit 130, the other end is connected to the fourth sub-switched capacitor circuit 122, and the other end of the fourth sub-switched capacitor circuit 122 is connected to the second input end of the integrating circuit 130; a first connection node of the first sub-switched capacitor circuit 111 and the fourth sub-switched capacitor circuit 122 is configured to receive the input signal Vs through the first switch SA 1; the first connecting node is also used for connecting a detection pin TK; one end of the second sub-switched capacitor circuit 112 is connected to the second input end of the integrating circuit 130, the other end is connected to the third sub-switched capacitor circuit 121, and the other end of the third sub-switched capacitor circuit 121 is connected to the first input end of the integrating circuit 130; a second connection node between the second sub-switched-capacitor circuit 112 and the third sub-switched-capacitor circuit 121 is configured to receive the input signal Vs through the second switch SA 2; the second connection node is further connected to one end of the capacitor array Cref, and the other end of the capacitor array Cref is grounded.

Specifically, the first sub-switched capacitor circuit 111 includes a third switch SA3, a fourth switch SA4, a fifth switch SA5, a sixth switch SA6, and a first capacitor C1; a first end of the first capacitor C1 is connected to the first input end through a third switch SA3, a second end is connected to the fourth sub-switched capacitor circuit 122 through a fourth switch SA4, a first end of the first capacitor C1 is further grounded through a fifth switch SA5, and a second end is further grounded through a sixth switch SA 6; the second sub-switched capacitor circuit 112 includes a seventh switch SA7, an eighth switch SA8, a ninth switch SA9, a tenth switch SA10, and a second capacitor C2; a first end of a second capacitor C2 is connected to the second input end through a seventh switch SA7, a second end is connected to the third sub-switched capacitor circuit 121 through an eighth switch SA8, a first end of the second capacitor C2 is further grounded through a ninth switch SA9, and a second end is further grounded through a tenth switch SA 10; the third sub-switched capacitor circuit 121 includes an eleventh switch SA11, a twelfth switch SA12 and a third capacitor C3, a first end of the third capacitor C3 is connected to the first input end through the eleventh switch SA11, a second end of the third capacitor C3 is connected to the eighth switch SA8 through the twelfth switch SA12, a connection node between the twelfth switch SA12 and the eighth switch SA8 receives the input signal Vs through the second switch SA2, and a connection node between the twelfth switch SA12 and the eighth switch SA8 is further connected to the capacitor array Cref; the fourth sub-switched capacitor circuit 122 includes a thirteenth switch SA13, a fourteenth switch SA14 and a fourth capacitor C4, a first end of the fourth capacitor C4 is connected to the second input end through a tenth switch SA13, a second end of the fourth capacitor C4 is connected to a fourth switch SA4 through a fourteenth switch SA14, a connection node between the fourteenth switch SA14 and the fourth switch SA4 receives the input signal Vs through a first switch SA1, and a connection node between the fourteenth switch SA14 and the fourth switch SA4 is further used for connecting the detection pin TK.

Similar to the single-ended detection, in the differential detection mode, the first switched-capacitor integrator circuit may be an in-phase switched-capacitor integrator circuit, and the second switched-capacitor integrator circuit may be an inverting switched-capacitor integrator circuit. Specifically, the first sub-switched capacitor circuit and the integrating circuit form an in-phase switched capacitor integrating circuit by being connected with a first input end of the integrating circuit; the second sub-switched capacitor circuit and the integrating circuit form an in-phase switched capacitor integrating circuit by being connected with a second input end of the integrating circuit; the third sub-switched capacitor circuit and the integrating circuit form an inverse switched capacitor integrating circuit by being connected with the first input end of the integrating circuit; the fourth sub-switched capacitor circuit and the integrating circuit form an inverse switched capacitor integrating circuit by being connected with the second input end of the integrating circuit. Alternatively, the first switched-capacitor integrating circuit may be an inverse-phase switched-capacitor integrating circuit, and the second switched-capacitor integrating circuit may be an in-phase switched-capacitor integrating circuit, and the specific connection manner may refer to the foregoing description and is not described herein again. In addition, the principle of the differential detection is consistent with the single-ended detection, and is not described in detail.

In some embodiments, the integrator 100 further comprises a Reset switch Reset connected between the input and the output of the integration circuit 130. When the system is restarted, it can be Reset by the Reset switch Reset and clear the charge on the integrating capacitor Cint.

The embodiment of the utility model provides an integrator, through setting up the integrated circuit of first switched capacitor and the integrated circuit of second switched capacitor that the integral direction is opposite, eliminate because the influence of inherent electric capacity and extra accumulative voltage when integral capacitance is at every turn the integral, and then can carry out the integral many times with the integral capacitance of less appearance value to effectively increase integral capacitance's the integral number of times under the condition that does not adopt outer electric capacity of piece, reduce circuit area and reduce cost. Meanwhile, after the extra accumulated voltage of the integration capacitor during each integration is eliminated, the voltage accumulated by the integration capacitor each time is kept consistent, so that the signal-to-noise ratio of the system and the accuracy of capacitance detection are improved.

As shown in fig. 6, the embodiment of the present invention further provides a touch capacitance detection circuit 200, which is applied to the capacitance sensing system 10, and includes the integrator 100. The touch capacitance detection circuit 200 further includes a detection pin TK and an excitation signal source 210. The detection pin TK is connected with a first switch capacitor circuit; the driving signal source 210 is connected to the first switched capacitor circuit and the second switched capacitor circuit, and is configured to output an input signal Vs to the first switched capacitor circuit and the second switched capacitor circuit.

Further, the touch capacitance detecting circuit 200 further includes a clock generating circuit 220. The clock generating circuit 220 is connected to the first switched capacitor circuit and the second switched capacitor circuit, respectively. And the clock generation circuit 220 is operable to generate a set of non-overlapping clock signals (Ph1, Ph2) to act on the first switched-capacitor circuit and the second switched-capacitor circuit. Non-overlap indicates that clock signal Ph1 and clock signal Ph2 cannot be high at the same time.

Further, the touch capacitance detecting circuit 200 further includes a calibration circuit 230, and the calibration circuit 230 is connected to the excitation signal source 210. The calibration circuit 230 is used to calibrate the input signal Vs.

The embodiment of the utility model provides a touch electric capacity detection circuitry is provided with the integrator to set up integral circuit of first switch capacitance and second switch capacitance opposite direction, eliminate because inherent electric capacity's influence and the voltage of additional accumulation when integral capacitance is at every turn the integral, and then can carry out the multiple integral with the integral capacitance of less appearance value, thereby effectively increase integral capacitance's the integral number of times under the condition that does not adopt outer electric capacity of piece, reduce circuit area and reduce cost. Meanwhile, after the extra accumulated voltage of the integration capacitor during each integration is eliminated, the voltage accumulated by the integration capacitor each time is kept consistent, so that the signal-to-noise ratio of the system and the accuracy of capacitance detection are improved.

As shown in fig. 7, the embodiment of the present invention further provides a smart device 300, which includes a sensor 310 and the touch capacitance detection circuit 200. Wherein the sensor 310 is coupled to the detection pin TK. The sensor 310 may be a capacitive sensor, and when a touch event occurs, the sensor 310 may generate a capacitance change, which causes a capacitance change on the detection pin TK, thereby generating a touch capacitance Ctk.

In this embodiment, the smart device 300 includes, but is not limited to, a portable communication device, a wearable smart device, a home appliance, and the like.

The embodiment of the utility model provides an intelligent device is provided with touch electric capacity detection circuitry, through setting up integral opposite direction's first switch capacitance volume integrating circuit and second switch capacitance volume integrating circuit, eliminate because the influence of inherent electric capacity and the voltage of additional accumulation when integral capacitance is at every turn integrated, and then can carry out the multiple integration with the integral capacitance of less appearance value to effectively increase integral capacitance's the integral number of times under the condition that does not adopt off-chip electric capacity, reduce circuit area and reduce cost. Meanwhile, after the extra accumulated voltage of the integration capacitor during each integration is eliminated, the voltage accumulated by the integration capacitor each time is kept consistent, so that the signal-to-noise ratio of the system and the accuracy of capacitance detection are improved.

The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention has been disclosed by the preferred embodiment, it is not limited to the present invention, and any person skilled in the art can make modifications or changes equivalent to the equivalent embodiments by utilizing the above disclosed technical contents without departing from the technical scope of the present invention, but all the modifications, changes and changes of the technical spirit of the present invention made to the above embodiments are also within the scope of the technical solution of the present invention.

Claims

1. An integrator, comprising:

an integrating circuit comprising an input;

the first switched capacitor circuit is connected with the input end of the integrating circuit at one end, receives an input signal at the other end, is also connected with a detection pin and forms a first switched capacitor integrating circuit with the integrating circuit; and

and one end of the second switched capacitor circuit is connected with the input end of the integrating circuit, the other end of the second switched capacitor circuit is used for receiving the input signal, the second switched capacitor circuit and the integrating circuit form a second switched capacitor integrating circuit, and the integrating directions of the first switched capacitor integrating circuit and the second switched capacitor integrating circuit are opposite.

2. The integrator of claim 1, wherein the input terminals comprise a first input terminal and a second input terminal, the first switched-capacitor circuit and the second switched-capacitor circuit being connected to the first input terminal at the same time, the second input terminal being connected to ground.

3. The integrator of claim 2, wherein the first switched-capacitor circuit comprises a first capacitor, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, a first terminal of the first capacitor receives the input signal through the first switch and the second switch which are sequentially connected in series, a first terminal of the first capacitor is further grounded through the third switch, a second terminal of the first capacitor is connected with the first input terminal of the integrating circuit through the fourth switch, a second terminal of the first capacitor is further grounded through the fifth switch, and a connection node of the first switch and the second switch is used for connecting the detection pin;

the second switched capacitor circuit includes a second capacitor, a sixth switch, a seventh switch, an eighth switch, and a capacitor array, a first end of the second capacitor receives the input signal through the fifth switch and the sixth switch which are sequentially connected in series, a second end of the second capacitor is connected to the first input end of the integrating circuit through the seventh switch, a first end of the capacitor array is connected between the sixth switch and the seventh switch, and a second end of the capacitor array is grounded.

4. The integrator of claim 1, wherein the input terminals comprise a first input terminal and a second input terminal, the first switched-capacitor circuit comprises a first sub-switched-capacitor circuit and a second sub-switched-capacitor circuit; the second switched capacitor circuit comprises a third sub-switched capacitor circuit, a fourth sub-switched capacitor circuit and a capacitor array; the integrator further comprises a first switch and a second switch;

one end of the first sub-switched capacitor circuit is connected to the first input end, the other end of the first sub-switched capacitor circuit is connected to the fourth sub-switched capacitor circuit, and the other end of the fourth sub-switched capacitor circuit is connected to the second input end; a first connection node of the first sub-switched capacitor circuit and the fourth sub-switched capacitor circuit is used for receiving the input signal through the first switch; the first connecting node is also used for connecting the detection pin;

one end of the second sub-switched capacitor circuit is connected to the second input end, the other end of the second sub-switched capacitor circuit is connected to the third sub-switched capacitor circuit, and the other end of the third sub-switched capacitor circuit is connected to the first input end; a second connection node of the second sub-switched capacitor circuit and the third sub-switched capacitor circuit is used for receiving the input signal through the second switch; the second connection node is further connected to one end of the capacitor array, and the other end of the capacitor array is grounded.

5. The integrator of any one of claims 1 to 4, wherein the first switched-capacitor integrator circuit is an in-phase switched-capacitor integrator circuit and the second switched-capacitor integrator circuit is an inverted switched-capacitor integrator circuit; or, the first switched-capacitor integrating circuit is an inverse-phase switched-capacitor integrating circuit, and the second switched-capacitor integrating circuit is an in-phase switched-capacitor integrating circuit.

6. An integrator as claimed in any one of claims 1 to 4, further comprising a reset switch connected between the input and output of the integrating circuit.

7. An integrator as claimed in claim 3 or 4, wherein the capacitor array comprises a plurality of capacitors connected in parallel with each other.

8. A touch capacitance detection circuit comprising the integrator of any of claims 1 to 7, the touch capacitance detection circuit further comprising:

the detection pin is connected with the first switch capacitor circuit; and

and the excitation signal source is connected with the first switched capacitor circuit and the second switched capacitor circuit and is used for outputting the input signal.

9. The touch capacitance detection circuit of claim 8, further comprising a clock generation circuit coupled to the first switched-capacitance circuit and the second switched-capacitance circuit, respectively.

10. A smart device comprising a sensor and a touch capacitance detection circuit as claimed in claim 8 or 9, wherein the sensor is connected to the detection pin.