CN211697922U - 2FSK demodulation circuit for charger mainboard signal test - Google Patents

Abstract

The utility model provides a 2FSK demodulation circuit for charger mainboard signal test with low costs, integrated level height, stability well and that measuring accuracy is high. The circuit comprises a 2FSK modulation circuit (1), an inductive coupling coil (2), an analog adjustable load (3), a signal filtering circuit (4), an FPGA sampling unit (5) and an MCU data demodulation unit (6). The utility model is used for wireless charger test field.

Description

2FSK demodulation circuit for charger mainboard signal test

Technical Field

The utility model relates to a wireless charger test field especially relates to a 2FSK demodulation circuit for charger mainboard signal test.

Background

In the wireless charging device of QI standard, the communication signal transmitted from the energy transmitting end to the energy receiving end is transmitted by means of 2FSK (frequency shift keying), unlike the conventional FSK signal: according to the communication protocol of the QI standard, at different stages of the same system, the communication carrier frequency Fca and the modulation frequency Fmod are not fixed, and the frequency difference between Fca and Fmod is small. In the QI standard, a period difference between a carrier frequency Fca and a modulation frequency Fmod, namely 282ns at the maximum and 32ns at the minimum, is specified to ensure transmission energy stability. Meanwhile, because the signal received by the energy receiving end in the wireless charging system is the signal inductively coupled, the received signal is not a single-frequency sinusoidal signal, but may be doped with a large amount of high-frequency noise.

The traditional 2FSK demodulation method mainly comprises three modes of coherent demodulation, filtering non-coherent demodulation and orthogonal multiplication non-coherent demodulation. Due to the limitation of the QI standard communication protocol, the difference between the carrier frequency Fca and the modulation frequency Fmod is small, and the requirement on the demodulation circuit at the receiving end is very high.

Therefore, the traditional 2FSK demodulation method is difficult to meet the communication test requirements in the wireless charging field with higher and higher precision, for example, although the anti-noise performance of a coherent demodulation 2FSK system is superior to that of incoherent envelope detection, two coherent carrier circuits need to be inserted, and the whole circuit becomes complex. The non-coherent envelope detection does not require a coherent carrier, and thus the circuit is relatively simple. But the relative difference between coherent demodulation and filtered non-coherent demodulation is not significant when the signal-to-noise ratio r of the input signal is large. In addition, the conventional 2FSK demodulation method is not flexible enough, and 2FSK signal communication may occur at any energy signal frequency point, so that a specific demodulation circuit is required.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that overcome prior art not enough, provide a 2FSK demodulation circuit for charger mainboard signal test with low costs, the integrated level is high, stability is good and the measuring accuracy is high.

A technical scheme that 2FSK demodulation circuit for charger mainboard signal test adopted is: it comprises a 2FSK modulation circuit, an inductive coupling coil, an analog adjustable load, a signal filter circuit, an FPGA sampling unit and an MCU data demodulation unit,

the 2FSK modulation circuit carries out BMC coding on a charger mainboard signal generated in an analog mode, carries out 2FSK modulation on the BMC-coded signal and transmits the modulated signal to the inductive coupling coil;

the inductive coupling coil comprises a sending coil and a receiving coil, and the sending coil couples the modulated signal to the receiving coil end;

the analog adjustable load is used for simulating wireless charging charged equipment and adjusting the power of the receiving coil end in an analog mode so as to carry out 2FSK communication test on the charged equipment in different power states;

the signal filter circuit is used for carrying out DC removal, filtering, level matching and voltage division on the 2FSK signal, and then inputting the 2FSK signal into the FPGA sampling unit through a GPIO port;

the FPGA sampling unit samples the filtered 2FSK signal and transmits the sampled signal to the MCU data demodulation unit;

the MCU data demodulation unit is used for carrying out denoising processing, BMC recovery and BMC decoding on the signals sent by the FPGA sampling unit, enabling the BMC coded signals to be finally restored to original signals, completing demodulation of 2FSK signals, comparing whether the demodulated signals are consistent with the original signals of the charger mainboard or not, and further completing testing of 2FSK transmission signals from the sending coil to the receiving coil.

According to the scheme, after the wireless charger mainboard generates an analog signal, the signal is subjected to BMC coding through a 2FSK modulation circuit, the BMC-coded signal is subjected to 2FSK modulation, the modulated signal is transmitted to the inductive coupling coil, the inductive coupling coil is used for wirelessly transmitting the signal, wireless communication from a sending coil end to a receiving coil end is realized, a rectifying circuit is arranged at the receiving coil end, the signal is transmitted to an FPGA sampling unit through a signal filtering circuit to be collected, corresponding high or low level is output to an MCU data demodulation unit according to different signal frequencies, signal denoising, BMC recovery and BMC decoding processing are carried out through the MCU data demodulation unit, the BMC-coded signal is finally restored into an original signal, so that the analysis of the 2FSK demodulation signal is completed, and whether the demodulated signal is consistent with the original signal of the charger mainboard or not is compared, further completing 2FSK communication test from the sending coil end to the receiving coil end; in the process, the FPGA sampling unit and the MCU data demodulation unit jointly realize the demodulation function, the circuit is simple, the realization is easy, the expansion is convenient, the integration level is higher, the cost is relatively reduced, the sampling clock of the FPGA sampling unit can reach 125MHz, the signal error correction can be carried out, the stability is high, and the precision is high; the real coil of the product is used for simulating the Qi wireless charging process, wireless transmission of signals from the receiving coil end to the sending coil end is realized through specific inductive coupling, wireless transmission efficiency adjustment tests of different coupling coefficients can be realized by adjusting the distance between the two coils, so that the test requirements under different coupling coefficients are met, the coil of the product is used as a test carrier, and 2FSK communication tests are closer to the real condition, so that the test result is more suitable for practical application, and the test result is ensured to have higher precision; meanwhile, 2FSK demodulation can be stably carried out on different 2FSK communication coding rules through the arrangement of the demodulation circuit, so that the method can be applied to 2FSK communication tests of different wireless charging devices and has better applicability.

Further, the analog adjustable load comprises an analog load and a load adjusting MCU connected with the analog load, the analog load comprises a field effect transistor connected with the receiving coil, a comparator connected with a grid electrode of the field effect transistor and an amplifier connected with one input end of the comparator, the output end of the amplifier is connected with the load adjusting MCU through an ADC module, the other input end of the comparator is connected with the load adjusting MCU through a DAC module, the load adjusting MCU sets different analog load current values through the DAC module, the load adjusting MCU collects the voltage value and the current value of the receiving coil end through the ADC module, carries out amplitude adjustment on the signal of the transmitting coil, and carries out wireless charging 2FSK communication test under different amplitudes.

According to the scheme, different current values are set by the load adjusting MCU through the high-precision DAC module, meanwhile, the high-precision ADC module collects a voltage value Uout and a current value Iout of the wireless charging receiving coil end after rectification, the Uout reaches a value under the set power by adjusting the amplitude of a transmitting signal at the wireless charging transmitting coil end, the current Iout value of the analog load part is set to reach the set value, the set transmission power can be obtained, the 2FSK signal is tested at the moment, communication data under the power state are obtained, the 2FSK communication test of wireless charging under different transmission power states is achieved by adjusting the amplitudes of different transmitting signals, and the tested 2FSK communication data result meets the practical application.

Still further, a rectifier circuit is arranged at the end of the receiving coil, the rectifier circuit comprises a first capacitor, a second capacitor, a rectifier bridge, a third capacitor and a first resistor, the first capacitor is connected in series with the receiving coil, and the second capacitor, the rectifier bridge, the third capacitor and the first resistor are sequentially connected in parallel at two ends of the receiving coil. Therefore, the arrangement of the rectifier circuit formed by components such as the rectifier bridge ensures the fidelity rate of the signal output by the receiving coil end.

Still further, the signal filtering circuit comprises a direct current removing capacitor, a denoising filter, a surge removing device and a voltage dividing device, the direct current removing capacitor, the denoising filter, the surge removing device and the voltage dividing device are sequentially connected, the other end of the direct current removing capacitor is connected with the receiving coil end, and the voltage dividing device sends the filtered signal to the FPGA sampling unit. Therefore, direct current components are removed through the direct current removing capacitor, high and low frequency noise is removed through the denoising filter and the surge removing device, the voltage stabilizing effect is achieved, the voltage divider ensures level matching of the input FPGA acquisition unit, and the whole process ensures that signals are not distorted.

Still further, the MCU data demodulation unit comprises an MCU unit, a signal identification unit, a signal denoising unit, a BMC recovery unit and a BMC decoding unit, and the signal identification unit, the signal denoising unit, the BMC recovery unit and the BMC decoding unit are all connected with the MCU unit. Therefore, the MCU unit controls the whole FPGA acquisition unit, the signal identification unit identifies the received signal, and the signal denoising unit denoises the signal to improve the resolution and the fault tolerance; the BMC recovery unit recovers the denoised signal into a signal in a BMC form; the BMC decoding unit is mainly used for restoring the BMC signal into an original signal so as to finish the analysis of the ASK demodulation signal; the circuit has the advantages of high integration level, low cost, stable FPGA operation and reliable system, and the service life of the circuit is prolonged.

In addition, the model of the FPGA sampling unit 5 is ZYNQ7Z 020. Therefore, the FPGA sampling clock of the type can reach 125MHz, can carry out signal error correction, and has high stability and high precision.

Drawings

FIG. 1 is a schematic block diagram of the present invention;

fig. 2 is a simplified structural diagram of the inductive coupling coil;

FIG. 3 is a simplified schematic diagram of the simulated adjustable load;

FIG. 4 is a simplified schematic diagram of the signal filtering circuit;

FIG. 5 is a waveform diagram of signals collected by the FPGA sampling unit;

FIG. 6 is a schematic diagram of a demodulation waveform of the MCU data demodulation unit on a signal;

FIG. 7 is a diagram of a coding pattern of a BMC coding unit;

fig. 8 is a waveform diagram of a modulation signal of the 2FSK modulation circuit;

fig. 9 is a block diagram of a simple structure of the MCU data demodulation unit.

Detailed Description

The utility model discloses use BMC coding and 2FSK modulation. BMC coding is a short term for Biphase mark code, belongs to a phase modulation (phase modulation) coding method, and is a coding method in which a clock signal and a data signal are mixed and transmitted. As shown in fig. 7, in BMC encoding, the frequency of the clock signal is twice the data transmission bit rate. The BMC signal jumps on the rising edge of the clock signal; on the falling edge of the clock, whether the BMC toggles depends on the data signal, and when the data signal is high, the BMC toggles. When the data signal is low, the BMC does not hop. And digital frequency shift keying is the transmission of a digital message with the frequency of the carrier, i.e. the frequency of the carrier is controlled by the transmitted digital message. The 2FSK signal is a modulated waveform with the symbol "1" corresponding to the carrier frequency F0 and the symbol "0" corresponding to the carrier frequency F1 (another carrier frequency different from F0), and the change between F0 and F1 is accomplished instantaneously. In principle, digital frequency modulation can be realized by analog frequency modulation or by key control. The analog frequency modulation method is a method for realizing frequency modulation of a carrier wave by using a rectangular pulse sequence, and is early adopted in a frequency shift keying communication mode. The 2FSK keying law is the gating of two different independent frequency sources by a switching circuit controlled by a rectangular pulse sequence. The key control method has the characteristics of high conversion speed, good waveform, high stability, easy realization and wide application. In 2FSK, the frequency of the carrier varies with the binary baseband signal between two frequency bins f1 and f 2. As can be seen from fig. 8, the waveform of the 2FSK signal can be decomposed into a waveform F0 'and a waveform F1', that is, one 2FSK signal can be regarded as a superposition of two 2ASK signals of different carrier frequencies.

As shown in fig. 1 to fig. 6 and fig. 9, the utility model discloses a 2FSK modulation circuit 1, inductive coupling coil 2, simulation adjustable load 3, signal filter circuit 4, FPGA sampling unit 5 and MCU data demodulation unit 6. The 2FSK modulation circuit 1 performs BMC coding on data to be transmitted, performs 2FSK modulation on a BMC-coded signal, and transmits the modulated signal to the inductive coupling coil 2. The inductive coupling coil 2 comprises a transmitting coil TX and a receiving coil RX, the transmitting coil TX coupling the modulated signal to the receiving coil RX. The analog adjustable load 3 is used for simulating a wireless charged device to be charged and adjusting the power of the RX end of the receiving coil in an analog manner, so as to perform 2FSK communication test on the device to be charged in different power states. The signal filtering circuit 4 is used for carrying out operations of direct current removal, filtering, level matching and voltage division on the 2FSK signal, and then inputting the FSK signal into the FPGA sampling unit 5 through a GPIO port. The FPGA sampling unit 5 samples the filtered 2FSK signal and transmits the sampled signal to the MCU data demodulation unit 6. The MCU data demodulation unit 6 is used for performing denoising processing, BMC recovery and BMC decoding on the signal sent by the FPGA sampling unit 5, enabling the BMC coded signal to be finally restored to an original signal, completing demodulation of the 2FSK signal, comparing whether the demodulated signal is consistent with the original signal of the charger mainboard or not, and further completing testing of the 2FSK transmission signal from the sending coil to the receiving coil.

The receiving coil RX end is provided with a rectifying circuit, the rectifying circuit comprises a first capacitor C1, a second capacitor C2, a rectifying bridge B1, a third capacitor C3 and a first resistor R1, the first capacitor C1 is connected in series with the receiving coil RX, and the second capacitor C2, the rectifying bridge B1, the third capacitor C3 and the first resistor R1 are sequentially connected in parallel at two ends of the receiving coil RX. The signal filtering circuit 4 comprises a dc removing capacitor 41, a denoising filter 42 (with a band-pass frequency of 145Hz to 4.8 MHz), a surge removing device 43 and a voltage dividing device 44, the dc removing capacitor 41, the denoising filter 42, the surge removing device 43 and the voltage dividing device 44 are sequentially connected, the other end of the dc removing capacitor 41 is connected with the RX end of the receiving coil, and the voltage dividing device 44 sends the filtered signal to the FPGA sampling unit 5. The MCU data demodulation unit 6 includes an MCU unit 61, a signal identification unit 62, a signal denoising unit 63, a BMC recovery unit 64, and a BMC decoding unit 65, wherein the signal identification unit 62, the signal denoising unit 63, the BMC recovery unit 64, and the BMC decoding unit 65 are all connected to the MCU unit 61. The model of the FPGA sampling unit 5 is ZYNQ7Z 020.

The analog adjustable Load 3 comprises an analog Load E _ Load and a Load adjusting MCU7 connected with the analog Load E _ Load, the analog Load E _ Load includes a field effect transistor Q1 connected to the receiving coil RX, a comparator T1 connected to a gate of the field effect transistor Q1, and an amplifier T2 connected to one of input terminals of the comparator T1, the output terminal of the amplifier T2 is connected to the load regulation MCU7 through an ADC block 8, the other input of the comparator T1 is connected to the load regulation MCU7 through a DAC module 9, the load regulation MCU7 sets different values of analog load current through the DAC module 9, the load adjusting MCU7 collects the voltage value and the current value of the RX end of the receiving coil through the ADC module 8, and amplitude adjustment is carried out on the signal of the transmitting coil TX, and wireless charging 2FSK communication test is carried out under different amplitudes.

The wireless charging equipment of QI standard can transmit different powers through energy signals with different amplitudes in the normal working process, and the 2FSK signal communication can possibly occur in the energy signal transmission process with any amplitude. In the present embodiment, as shown in fig. 6, in the QI standard, the charged device converts power:

0.1C - Iout = 20mA, Uout = 5000mV；

1C - Iout = 50mA, Uout = 6000mV；

3C - Iout = 135mA, Uout t = 6000mV；

10C - Iout = 300mA, Uout = 10000mV。

the controllable constant-current load sets different current values through a high-precision DAC of the MCU, and the high-precision ADC collects a voltage value Uout and a current value Iout rectified at a wireless charging receiving end. The preset transmission power can be achieved by adjusting the amplitude of a sending signal of a wireless charging sending end to enable the Uout to reach a value under the preset power, and then setting the E _ load part current Iout to reach a preset value (for example, under 1C, Iout = 50mA and Uout = 6000 mV). And performing wireless charging 2FSK communication test by adjusting different transmission powers.

The method for testing the 2FSK signal of the charger mainboard by using the 2FSK demodulation circuit for testing the signal of the charger mainboard comprises the following steps:

a. the wireless charger mainboard generates a wireless charging test signal, the 2FSK modulation circuit 1 carries out BMC coding on data (binary data) to be transmitted and modulates a BMC coding signal through a 2FSK principle, and the frequency of a carrier wave changes between frequency points along with a binary baseband signal; the frequency points comprise a f1 frequency point and a f2 frequency point, the frequency of the f1 frequency point is 127.795KHz, and the frequency of the f2 frequency point is 126.984 KHz;

b. the inductive coupling coil 2 performs wireless signal transmission through inductive coupling, so as to realize wireless communication from the TX end of the transmitting coil to the RX end of the receiving coil;

c. the analog adjustable load 3 simulates wireless charging equipment to be charged, and simulates power adjustment of an RX end of a receiving coil so as to carry out 2FSK communication test on the equipment to be charged in different power states;

d. the signal filtering circuit 4 carries out filtering processing on the 2FSK signal, keeps the signal undistorted and inputs the signal into the FPGA sampling unit 5;

e. the FPGA sampling unit 5 samples signal data through a GPIO port and outputs a level signal to the MCU data demodulation unit 6 according to the acquired signal frequency;

f. the MCU data demodulation unit 6 identifies the received signals, performs denoising processing, BMC recovery and BMC decoding on the signals, finally restores the BMC coded signals to original signals, completes analysis of 2FSK demodulation signals, compares whether the demodulated signals are consistent with the original signals of the charger mainboard or not, and then completes 2FSK communication test from the sending coil end to the receiving coil end.

In the present invention, the 2FSK modulation circuit 1 encodes data (binary system) to be transmitted through the BMC encoding rule first, so as to improve the reliability of data transmission; and modulating the BMC encoded data by using a 2FSK principle, wherein the frequency of the carrier wave changes between two frequency points of f1 (127.795 KHz) and f2 (126.984 KHz) along with the binary baseband signal. The inductive coupling coil 2 realizes data wireless transmission through specific inductive coupling, thereby realizing wireless communication, inductive close-range coupling, and the adjustment of coupling distance can correspond to different coupling coefficients. The analog adjustable load 3 is mainly a charged device for analog wireless charging, and wireless communication from a charger to the charged device is actually carried out in the wireless charging process in a 2FSK modulation mode, so that 2FSK communication tests need to be carried out on the charged device under different powers, and the analog receiving unit can simulate and adjust the power of a receiving end. The signal filter circuit 4 mainly removes direct current components of 2FSK signals through a capacitor, removes high and low frequency noises through a filter (band-pass frequency is 145 Hz-4.8 MHz), divides the signals to be processed because the FPGA input needs level matching (+ -1V), and finally sends the signals to the FPGA GPIO of the MCU for data sampling, and the process needs to ensure that the signals are not distorted. The FPGA sampling unit 5 performs data sampling through a GPIO port, a sampling clock of the FPGA can reach 125MHz, the FPGA acquires signal data and calculates time (namely frequency) of each period, if the frequency is f1 (127.795 KHz), the output is high (1), and if the frequency is f2 (126.984 KHz), the output is low (0).

Compared with some existing testing devices, the system is high in precision, high in stability, small in size and low in cost, the 2FSK communication test is closer to the real situation due to the fact that the real coil is used for simulating the whole wireless charging process, and meanwhile 2FSK demodulation can be stably carried out on different 2FSK communication coding rules, so that the system can be applied to the 2FSK communication test of different wireless charging devices.

The utility model describes an utilize the wireless test equipment who charges of true coil simulation Qi, carry out wireless charging equipment's 2FSK communication test to describe in the scheme in not only the limit and the patent. Therefore, all equivalent changes or modifications made according to the structure, characteristics and principles described in the claims of the present invention should be included in the claims of the present invention.

Claims (6)

1. A2 FSK demodulation circuit for charger mainboard signal test is characterized in that: it comprises a 2FSK modulation circuit (1), an inductive coupling coil (2), an analog adjustable load (3), a signal filter circuit (4), an FPGA sampling unit (5) and an MCU data demodulation unit (6),

the 2FSK modulation circuit (1) carries out BMC coding on data to be transmitted, carries out 2FSK modulation on a signal subjected to BMC coding and transmits the modulated signal to the inductive coupling coil (2);

the inductive coupling coil (2) comprises a transmitting coil (TX) and a receiving coil (RX), the transmitting coil (TX) couples the modulated signal to the receiving coil (RX) end;

the analog adjustable load (3) is used for simulating a wireless charged device to be charged and adjusting the power of the receiving coil (RX) end in an analog mode so as to carry out 2FSK communication test on the charged device in different power states;

the signal filtering circuit (4) is used for carrying out DC removal, filtering, level matching and voltage division on the 2FSK signal, and then inputting the FSK signal into the FPGA sampling unit (5) through a GPIO port;

the FPGA sampling unit (5) samples the filtered 2FSK signal and transmits the sampled signal to the MCU data demodulation unit (6);

the MCU data demodulation unit (6) is used for carrying out denoising processing, BMC recovery and BMC decoding on the signals sent by the FPGA sampling unit (5), enabling the BMC coded signals to be finally restored to original signals, completing demodulation of 2FSK signals, comparing whether the demodulated signals are consistent with the original signals of the charger mainboard or not, and further completing testing of 2FSK transmission signals from the sending coil to the receiving coil.

2. The 2FSK demodulation circuit for testing signals on a main board of a charger according to claim 1, wherein: the analog adjustable Load (3) comprises an analog Load (E _ Load) and a Load adjusting MCU (7) connected with the analog Load (E _ Load), the analog Load (E _ Load) comprises a field effect transistor (Q1) connected with the receiving coil (RX), a comparator (T1) connected with the grid of the field effect transistor (Q1) and an amplifier (T2) connected with one input end of the comparator (T1), the output end of the amplifier (T2) is connected with the Load adjusting MCU (7) through an ADC module (8), the other input end of the comparator (T1) is connected with the Load adjusting MCU (7) through a DAC module (9), the Load adjusting MCU (7) sets different analog Load current values through the DAC module (9), and the Load adjusting MCU (7) acquires the voltage value and the current value of the receiving coil (RX) end through the ADC module (8), and amplitude adjustment is carried out on the signal of the transmitting coil (TX), and wireless charging 2FSK communication test is carried out under different amplitudes.

3. The 2FSK demodulation circuit for testing signals on a main board of a charger according to claim 2, wherein: the receiving coil (RX) end is provided with a rectifying circuit, the rectifying circuit comprises a first capacitor (C1), a second capacitor (C2), a rectifying bridge (B1), a third capacitor (C3) and a first resistor (R1), the first capacitor (C1) is connected on the receiving coil (RX) in series, and the second capacitor (C2), the rectifying bridge (B1), the third capacitor (C3) and the first resistor (R1) are connected at two ends of the receiving coil (RX) in parallel in sequence.

4. The 2FSK demodulation circuit for testing signals on a main board of a charger according to claim 1, wherein: the signal filtering circuit (4) comprises a direct current removing capacitor (41), a denoising filter (42), a surge removing device (43) and a voltage dividing device (44), the direct current removing capacitor (41), the denoising filter (42), the surge removing device (43) and the voltage dividing device (44) are sequentially connected, the other end of the direct current removing capacitor (41) is connected with the receiving coil (RX) end, and the voltage dividing device (44) sends filtered signals to the FPGA sampling unit (5).

5. The 2FSK demodulation circuit for testing signals on a main board of a charger according to claim 1, wherein: the MCU data demodulation unit (6) comprises an MCU unit (61), a signal identification unit (62), a signal denoising unit (63), a BMC recovery unit (64) and a BMC decoding unit (65), wherein the signal identification unit (62), the signal denoising unit (63), the BMC recovery unit (64) and the BMC decoding unit (65) are all connected with the MCU unit (61).

6. The 2FSK demodulation circuit for testing signals on a main board of a charger according to claim 1, wherein: the FPGA sampling unit (5) is ZYNQ7Z 020.

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