CN211557249U - Multi-path clock generating circuit - Google Patents
Multi-path clock generating circuit Download PDFInfo
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- CN211557249U CN211557249U CN201922256206.1U CN201922256206U CN211557249U CN 211557249 U CN211557249 U CN 211557249U CN 201922256206 U CN201922256206 U CN 201922256206U CN 211557249 U CN211557249 U CN 211557249U
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Abstract
The utility model discloses a multichannel clock generation circuit includes oscillator, frequency synthesizer and clock follower at least, multichannel clock generation circuit still includes clock processing module, the oscillator frequency synthesizer clock processing module with clock follower connects according to the mode that cascades in proper order, the initial clock signal transmission that the oscillator generated extremely frequency synthesizer, the differential clock signal transmission that frequency synthesizer generated extremely clock processing module, the target clock signal transmission that clock processing module generated extremely clock follower.
Description
Technical Field
The utility model relates to an electronic circuit field, in particular to multichannel clock generation circuit.
Background
In electronic circuitry, the stability of the clock is a critical factor affecting overall system performance. With the increasing integration and complexity of electronic chips, clock signals with different frequencies and phases are required to be provided for each functional module and peripheral circuits inside the electronic chip in most digital circuit systems. The stable output of clocks in multiple clock domains is an important issue in circuit design that must be addressed and addressed.
At present, a common method for generating multiple clocks is to use multiple clock sources capable of generating different frequencies, such as crystal oscillators or other clock chips, and when the number of clocks required in a system is too large, the number of clock chips used is also correspondingly increased, which inevitably leads to the problems of increased volume of clock modules and tense layout of circuit boards.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a multichannel clock generating circuit has only realized the formation of multichannel clock with less chip to clock module is bulky among the electronic system, problem with high costs has been solved.
For solving above technical problem, the technical scheme of the utility model for adopting a multichannel clock generation circuit, include oscillator, frequency synthesizer and clock follower at least, multichannel clock generation circuit still includes clock processing module, the oscillator frequency synthesizer clock processing module with clock follower connects according to the mode that cascades in proper order, wherein: in a case where the initial clock signal generated by the oscillator is transmitted to the frequency synthesizer to generate a differential clock signal and the differential clock signal is transmitted to the clock processing module, the target clock signal generated by the clock processing module is transmitted to the clock outputter.
Optionally, the clock processing module at least includes a clock selector and a clock manager, and the clock selector and the clock manager are connected in a cascade manner.
Optionally, the clock selector comprises at least a balun and a single-pole double-throw switch for converting differential signals, and the clock manager comprises at least a clock divider and a clock divider, wherein: the balun, the single-pole double-throw switch, the clock distributor and the clock frequency divider are connected in a cascade connection mode.
Optionally, the output end of the frequency synthesizer and the input end of the balun are in I/O connection with each other, and when the differential clock signal generated by the frequency synthesizer is transmitted to the balun, the single-ended clock signal generated by the balun based on the differential clock signal is transmitted to the single-pole double-throw switch.
Optionally, the multi-way clock generating circuit further includes a radio frequency connector for providing a reference clock signal, an output terminal of the radio frequency connector is connected to an input terminal of the single-pole double-throw switch, and an output terminal of the single-pole double-throw switch is connected to an input terminal of the clock distributor.
Optionally, in a case where the single-pole double-throw switch receives the single-ended clock signal and the reference clock signal, the single-ended clock signal or the reference clock signal is transmitted to the clock distributor.
Optionally, in a case where the clock distributor generates two paths of clock signals with fixed frequency based on the single-ended clock signal or the reference clock signal, one path of clock signal is transmitted to the clock divider, and the other path of clock signal is transmitted to the digital-to-analog converter.
Optionally, the output of the clock divider and the input of the clock follower are I/O connected to each other, and in case the clock follower generates 1/4 a target clock signal of the fixed frequency based on the clock signal of the frequency, the target clock signal is transmitted to the clock follower.
Optionally, the clock output device comprises at least one output terminal, and the output terminal of the clock output device can be connected with a digital-to-analog converter, an analog-to-digital converter, a semi-custom circuit and/or a digital signal processor in a communication manner.
Optionally, in the case that the multi-path clock generating circuit uses a single oscillator, the multi-path clock signal with low phase noise generated by the clock output device can be transmitted to a digital-to-analog converter, an analog-to-digital converter, a semi-custom circuit and/or a digital signal processor.
The utility model discloses a first improvement part is the multichannel clock generation circuit who provides, through the oscillator, frequency synthesizer, clock processing module and clock follower's cooperation setting, the initial clock signal who has realized the output of single oscillator passes through frequency synthesizer after, through the clock processing module processing back, carry out multichannel clock signal's output with target clock signal transmission to clock follower, avoided using a plurality of clock sources or clock chip to generate multichannel clock signal, thereby the overall arrangement space on the circuit board has been saved, and production cost is reduced.
Drawings
Fig. 1 is a simplified circuit diagram of the multi-way clock generating circuit of the present invention;
fig. 2 is a simplified circuit diagram of a frequency synthesizer of the present invention;
FIG. 3 is a simplified circuit diagram of the clock selector of the present invention;
FIG. 4 is a simplified circuit connection diagram of the clock manager of the present invention; and
fig. 5 is a simplified circuit diagram of the clock output device of the present invention.
List of reference numerals
1: an oscillator 2: the frequency synthesizer 3: clock output device
4: the clock processing module 5: the radio frequency connector 6: digital-to-analog converter
7: the analog-to-digital converter 8: semi-custom circuit 9: digital signal processor
41: the clock selector 42: the clock manager 43: balun (a Chinese character)
44: single-pole double-throw switch 45: the clock distributor 46: clock frequency divider
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the present invention will be further described in detail with reference to the specific embodiments.
A multi-way clock generating circuit, as shown in FIG. 1, includes at least an oscillator 1, a frequency synthesizer 2, a clock output 3, and a clock processing module 4. The oscillator 1, the frequency synthesizer 2, the clock processing module 4 and the clock output device 3 are connected in a cascade connection manner. Preferably, as shown in fig. 2, the frequency synthesizer 2 is capable of adjusting the frequency of the initial clock signal and generating a differential clock signal, which may be in the form of a clock chip ADF 4335-3. Preferably, the oscillator 1 may be one of a crystal oscillator, a voltage controlled crystal oscillator, or a temperature compensated crystal oscillator. Preferably, the clock output device 3 is capable of generating clocks required by a multi-path system, and the model of the clock output device can be a clock fan-out chip HMC 7043.
Preferably, in the case where the initial clock signal generated by the oscillator 1 is transmitted to the frequency synthesizer 2 to generate a differential clock signal and the differential clock signal is transmitted to the clock processing module 4, the target clock signal generated by the clock processing module 4 is transmitted to the clock outputter 3.
Preferably, the utility model discloses a set up single oscillator and less chip and realized the production of multichannel clock, avoided the great, nervous problem of circuit board overall arrangement of clock module volume to appear effectively, solved the higher problem of traditional multichannel clock generation circuit board manufacturing cost simultaneously.
According to a preferred embodiment, the clock processing module 4 comprises at least a clock selector 41 and a clock manager 42. As shown in fig. 3, the clock selector 41 includes at least a balun 43 for converting a differential signal and a single-pole double-throw switch 44. As shown in fig. 4, the clock manager 42 includes at least a clock divider 45 and a clock divider 46. The balun 43, the single-pole double-throw switch 44, the clock divider 45, and the clock divider 46 are connected in a cascade in this order. Preferably, the single pole double throw switch 44 may be a 1 of 2 clock chip model HMC 849A. Preferably, the clock divider 45 may be a 1/2 fan-out chip of the clock model ADCLK 925. Preferably, clock divider 46 may be a divide-by-4 static divider chip of type HMC 365.
Preferably, the oscillator 1 is connected to the input terminal of the frequency synthesizer 2 through an oscillator pin, the output terminal pin of the frequency synthesizer 2 and the input terminal pin of the balun 43 are I/O connected to each other, the output terminal pin of the balun 43 and the input terminal pin of the single-pole double-throw switch 44 are I/O connected to each other, the output terminal pin of the single-pole double-throw switch 44 and the input terminal pin of the clock divider 45 are I/O connected to each other, the output terminal pin of the clock divider 45 and the input terminal pin of the clock divider 46 are I/O connected to each other, and the output terminal pin of the clock divider 46 and the input terminal pin of the clock follower 3 are I/O connected to each other.
Preferably, the initial clock signal of fixed frequency generated by the oscillator 1 is transmitted to the frequency synthesizer 2 to generate a low-noise differential clock signal. Preferably, the differential clock signal is transmitted to the balun 43 and generates a single-ended clock signal. The single-pole double-throw switch 44 selects a single-ended clock signal or a reference clock signal generated by the balun 43 and transmits the selected single-ended clock signal or the reference clock signal to the clock distributor 45 to generate two paths of fixed-frequency clock signals, one path of the clock signals is transmitted to the time divider 46 to generate 1/4 a target clock signal with the fixed frequency, the other path of the clock signals with the fixed frequency is transmitted to the digital-to- analog converter 6, and 1/4 the target clock signal with the fixed frequency generated by the time divider 46 is transmitted to the clock output 3 to generate multiple paths of clock signals. Preferably, the standard frequency set by the single pole double throw switch 44 may be 4 GHz.
According to a preferred embodiment, as shown in fig. 5, the clock output 3 comprises at least one output, the output of the clock output 3 being capable of establishing a communication connection with the digital-to-analog converter 6, the analog-to-digital converter 7, the semi-custom circuit 8 and/or the digital signal processor 9. Preferably, the output end of the clock output device 3 is in communication connection with various converters, so that the functions of converting a digital signal into an analog signal, converting an analog signal into a digital signal, translating an analog signal back and the like can be realized. Preferably, the digital signal processor 9 may be a DSP chip microprocessor. Preferably, the digital-to-analog converter 6 may be a DAC converter provided with a parallel or serial interface. Preferably, the analog-to-digital converter 7 may be an indirect ADC converter and/or a direct ADC converter. Preferably, the semi-custom circuit 8 may be a field programmable gate array device.
Preferably, the utility model discloses a set up single oscillator 1, when having realized using 3 output multichannel clock signals of clock output ware, guaranteed to have lower phase difference between the single-channel clock signal, avoided the noise that higher phase difference produced between the clock signal, promoted the efficiency of collaborative work between the multiple converter.
It should be noted that the present invention relates to electronic devices such as the oscillator 1, the frequency synthesizer 2, and the clock output 3, including but not limited to the types described in the above embodiments.
The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the spirit and scope of the invention, and such modifications and enhancements are intended to be within the scope of the invention.
Claims (10)
1. A multi-way clock generation circuit comprising at least an oscillator (1), a frequency synthesizer (2) and a clock follower (3),
the multi-path clock generation circuit further comprises a clock processing module (4), the oscillator (1), the frequency synthesizer (2), the clock processing module (4) and the clock output device (3) are connected in a sequential cascade mode, wherein:
an initial clock signal generated by the oscillator (1) is transmitted to the frequency synthesizer (2), a differential clock signal generated by the frequency synthesizer (2) is transmitted to the clock processing module (4), and a target clock signal generated by the clock processing module (4) is transmitted to the clock output device (3).
2. The multiple clock generation circuit according to claim 1, wherein the clock processing module (4) comprises at least a clock selector (41) and a clock manager (42),
the clock selector (41) and the clock manager (42) are connected in a cascaded manner.
3. The multiple clock generation circuit of claim 2, wherein the clock selector (41) comprises at least a balun (43) and a single-pole-double-throw switch (44) for converting differential signals, and the clock manager (42) comprises at least a clock divider (45) and a clock divider (46), wherein:
the balun (43), the single-pole double-throw switch (44), the clock divider (45) and the clock divider (46) are connected in a cascade in this order.
4. The multiple clock generation circuit according to claim 3, wherein the output terminal of the frequency synthesizer (2) and the input terminal of the balun (43) are I/O connected to each other, and when the differential clock signal generated by the frequency synthesizer (2) is transmitted to the balun (43), the single-ended clock signal generated by the balun (43) based on the differential clock signal is transmitted to the single-pole double-throw switch (44).
5. The multiple clock generation circuit of claim 4, further comprising a radio frequency connector (5) for providing a reference clock signal,
the output end of the radio frequency connector (5) is connected with the input end of the single-pole double-throw switch (44), and the output end of the single-pole double-throw switch (44) is connected with the input end of the clock distributor (45).
6. The multiple clock generation circuit of claim 5, wherein the single-ended clock signal or the reference clock signal is transmitted to the clock distributor (45) if the single-pole double-throw switch (44) receives the single-ended clock signal and the reference clock signal.
7. The multiple clock generation circuit according to claim 6, wherein in the case where the clock divider (45) generates two fixed-frequency clock signals based on the single-ended clock signal or the reference clock signal, one clock signal is transmitted to the clock divider (46) and the other clock signal is transmitted to the digital-to-analog converter (6).
8. The multiple clock generation circuit according to claim 7, wherein the output terminal of the clock divider (46) and the input terminal of the clock follower (3) are I/O connected to each other, and in the case where the clock follower (3) generates 1/4 a target clock signal of the frequency based on the clock signal of the fixed frequency, the target clock signal is transmitted to the clock follower (3).
9. The multiple clock generation circuit of claim 1, wherein the clock output comprises at least one output, the output of the clock output being capable of establishing a communication connection with the digital-to-analog converter (6), the analog-to-digital converter (7), the semi-custom circuit (8) and/or the digital signal processor (9).
10. A multiple clock generation circuit according to claim 9, wherein, in the case of using a single oscillator (1), the clock output unit (3) can generate multiple clock signals with low phase noise, which can be transmitted to the digital-to-analog converter (6), the analog-to-digital converter (7), the semi-custom circuit (8) and/or the digital signal processor (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922256206.1U CN211557249U (en) | 2019-12-16 | 2019-12-16 | Multi-path clock generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922256206.1U CN211557249U (en) | 2019-12-16 | 2019-12-16 | Multi-path clock generating circuit |
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| CN211557249U true CN211557249U (en) | 2020-09-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253347A (en) * | 2022-01-21 | 2022-03-29 | 湖南航天捷诚电子装备有限责任公司 | Device and method for generating differential synchronous clock based on two-way Feiteng processor |
-
2019
- 2019-12-16 CN CN201922256206.1U patent/CN211557249U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253347A (en) * | 2022-01-21 | 2022-03-29 | 湖南航天捷诚电子装备有限责任公司 | Device and method for generating differential synchronous clock based on two-way Feiteng processor |
| CN114253347B (en) * | 2022-01-21 | 2023-11-10 | 湖南航天捷诚电子装备有限责任公司 | Differential synchronous clock generation device and method based on double-path Feiteng processor |
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