CN211555472U - Nonvolatile memory power supply circuit - Google Patents
Nonvolatile memory power supply circuit Download PDFInfo
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- CN211555472U CN211555472U CN202020013631.8U CN202020013631U CN211555472U CN 211555472 U CN211555472 U CN 211555472U CN 202020013631 U CN202020013631 U CN 202020013631U CN 211555472 U CN211555472 U CN 211555472U
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Abstract
The utility model discloses a nonvolatile memory power supply circuit, integrated in the integrated chip that has nonvolatile memory, including power input end and power output end, power input end is connected with integrated chip's power pin electricity for input first voltage, power output end are used for the power supply of nonvolatile memory. The nonvolatile memory power supply circuit further comprises a voltage detection module, a switch control module and a voltage recovery module, wherein the voltage detection module is used for detecting whether the first voltage is within a preset voltage range. The switch control module is used for conducting when the first voltage is within a preset voltage range, so that the power supply input end provides the first voltage to the power supply output end. The voltage recovery module is used for providing a second voltage to the power supply output end through an internal power supply of the integrated chip when the first voltage is not in a preset voltage range. Thus, the design can be simplified and the cost can be saved.
Description
Technical Field
The utility model relates to a power supply field especially relates to a nonvolatile memory power supply circuit.
Background
Non-Volatile Memory (NVM) is widely used in integrated circuit chips, and it is known that external power is required to read, write or erase data from or to the NVM, especially when data is written or erased within a certain voltage range, the NVM Memory is damaged due to too high voltage, and data is not written sufficiently due to too low voltage, both of which can reduce the data storage reliability of the NVM.
The existing technical solutions include two schemes of an internal charge pump circuit and an external power pin. The scheme of the built-in charge pump circuit is difficult to design and occupies a large chip area due to the fact that the structure of the charge pump is relatively complex, and has certain risks and extra cost. The external power supply pin scheme introduces an additional package pin and an additional external power supply, thereby reducing the competitiveness of the product.
SUMMERY OF THE UTILITY MODEL
In view of this, it is desirable to provide a power supply circuit for a nonvolatile memory, which provides voltages required for reading, writing, and erasing data for the nonvolatile memory in an integrated chip through the existing power pins and internal power source of the integrated chip, thereby simplifying the design and saving the cost.
The utility model discloses a reach the technical scheme that above-mentioned purpose proposed as follows:
a nonvolatile memory power supply circuit is integrated in an integrated chip with a nonvolatile memory, the nonvolatile memory power supply circuit comprises a power input end and a power output end, the power input end is electrically connected with a power pin of the integrated chip and used for inputting a first voltage, the power output end is electrically connected with the nonvolatile memory and used for supplying power to the nonvolatile memory, the nonvolatile memory power supply circuit further comprises a voltage detection module, a switch control module and a voltage recovery module, one end of the voltage detection module is electrically connected with the power input end, the other end of the voltage detection module is electrically connected with the switch control module and the voltage recovery module, the switch control module is electrically connected between the power input end and the power output end, and the voltage recovery module is also electrically connected with the power output end, the voltage detection module is used for detecting whether the first voltage is within a preset voltage range, the switch control module is used for controlling the power input end to provide the first voltage to the power output end when the first voltage is within the preset voltage range, and the voltage detection module is used for providing the second voltage to the power output end through the internal power supply of the integrated chip when the first voltage is not within the preset voltage range.
Further, the voltage detection module includes a nand gate, a first comparator, a second comparator, and first to fourth resistors, one end of the first resistor is electrically connected to the power input terminal, the other end of the first resistor is electrically connected to one end of the second resistor, a first node is formed between the first resistor and the second resistor, the other end of the second resistor is grounded, one end of the third resistor is electrically connected to the power input terminal, the other end of the third resistor is electrically connected to one end of the fourth resistor, a second node is formed between the third resistor and the fourth resistor, the other end of the fourth resistor is grounded, the inverting input terminal of the first comparator is electrically connected to the first node, the inverting input terminal of the second comparator is electrically connected to the second node, and the non-inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator are both electrically connected to a reference voltage, the output end of the first comparator and the output end of the second comparator are respectively and electrically connected with the first input end and the second input end of the NAND gate, and the output end of the NAND gate is electrically connected with the switch control module and the voltage recovery module.
Further, the switch control module includes a fifth resistor, a first current source, and first to fourth electronic switches, a first end of the first electronic switch is electrically connected to the output end of the nand gate, a second end of the first electronic switch is grounded, a third end of the first electronic switch is electrically connected to the first end of the second electronic switch, the first end of the second electronic switch is also electrically connected to the first end of the third electronic switch, the second end of the second electronic switch is grounded, the third end of the second electronic switch is electrically connected to the first end of the second electronic switch, the third end of the second electronic switch is also electrically connected to one end of the first current source, the other end of the first current source is electrically connected to the internal power supply of the integrated chip, the second end of the third electronic switch is grounded, and the third end of the third electronic switch is electrically connected to the power supply input end through the fifth resistor, the third end of the third electronic switch is also electrically connected with the first end of the fourth electronic switch, the second end of the fourth electronic switch is electrically connected with the power input end, and the third end of the fourth electronic switch is electrically connected with the power output end.
Further, the voltage recovery module includes a not gate, a second current source, a diode, and a fifth to seventh electronic switches, an input terminal of the not gate is electrically connected to an output terminal of the nand gate, an output terminal of the not gate is electrically connected to a first terminal of the fifth electronic switch, a second terminal of the fifth electronic switch is grounded, a third terminal of the fifth electronic switch is electrically connected to a first terminal of the sixth electronic switch, a first terminal of the sixth electronic switch is further electrically connected to a first terminal of the seventh electronic switch, a second terminal of the sixth electronic switch is grounded, a third terminal of the sixth electronic switch is electrically connected to a first terminal of the sixth electronic switch, a third terminal of the sixth electronic switch is further electrically connected to a terminal of the second current source, and another terminal of the second current source is electrically connected to the internal power supply of the integrated chip, the second end of the seventh electronic switch is grounded, the third end of the seventh electronic switch is electrically connected with the power output end, the anode of the diode is electrically connected with the internal power supply of the integrated chip, and the cathode of the diode is electrically connected with the power output end.
Furthermore, the first to third electronic switches and the fifth to seventh electronic switches are N-channel field effect transistors, first, second, and third ends of the first to third and fifth to seventh electronic switches respectively correspond to a gate, a source, and a drain of the N-channel field effect transistor, the fourth electronic switch is a P-channel field effect transistor, and first, second, and third ends of the fourth electronic switch respectively correspond to a gate, a source, and a drain of the P-channel field effect transistor.
Further, the preset voltage range is a voltage range required by the nonvolatile memory when data is written or erased.
The power supply circuit of the nonvolatile memory detects whether a first voltage provided by a power pin of an integrated chip to a power input end is within a preset voltage range through a voltage detection module, and controls the first voltage to a power output end through a switch control module when the detection result shows that the first voltage is within the preset voltage range, so that the function of writing or erasing data in the nonvolatile memory is realized. And when the detection result is that the first voltage is not in the preset voltage range, the voltage recovery module provides a second voltage to the power output end by using an internal power supply of the integrated chip so as to realize the data reading function of the nonvolatile memory. Therefore, the voltage required by reading, writing and erasing data can be provided for the nonvolatile memory in the integrated chip through the existing power supply pin of the integrated chip without an additional power supply circuit, the design is greatly simplified, and the cost is saved.
Drawings
Fig. 1 is a block diagram of a preferred embodiment of a non-volatile memory power supply circuit according to the present invention.
Fig. 2 is a circuit diagram of a preferred embodiment of the power supply circuit of the non-volatile memory according to the present invention.
Description of the main elements
Non-volatile memory power supply circuit 100
Switch control module 30
Power supply output terminal 50
Nodes P1, P2
Current sources IBIAS1, IBIAS2
Capacitor C1
Resistors R1-R5
Diode D1
Electronic switch Q1-Q7
Comparators COMP1, COMP2
NOT gate INV1
NAND1
The following detailed description of the invention will be further described in conjunction with the above-identified drawings.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the present invention provides a power supply circuit 100 for a non-volatile memory. The nonvolatile memory power supply circuit 100 includes a power input terminal 10, a voltage detection module 20, a switch control module 30, a voltage recovery module 40, and a power output terminal 50. In this embodiment, the nonvolatile memory power supply circuit 100 is integrated in an integrated chip to supply power to a nonvolatile memory (not shown) built in the integrated circuit.
In this embodiment, the power input terminal 10 is electrically connected to a power pin (not shown) of the integrated circuit. One end of the voltage detection module 20 is electrically connected to the power input terminal 10, and the other end of the voltage detection module 20 is electrically connected to the switch control module 30 and the voltage recovery module 40. The switch control module 30 is electrically connected between the power input terminal 10 and the power output terminal 50. The voltage recovery module 40 is also electrically connected to the power output 50. The power supply output 50 is electrically connected to the non-volatile memory.
The power input terminal 10 is used for inputting a first voltage. The voltage detection module 20 is configured to detect whether the first voltage is within a preset voltage range, and output a control signal to the switch control module 30 and the voltage recovery module 40 according to a detection result. In this embodiment, the preset voltage range is a voltage range required for writing or erasing data in the nonvolatile memory.
When the first voltage is within the preset voltage range, the voltage detection module 20 outputs a control signal of a first level to control the switch control module 30 to be turned on, so that the power input terminal 10 provides the first voltage to the power output terminal 50. The function of writing or erasing data in the nonvolatile memory can be realized.
When the first voltage is not within the preset voltage range, the voltage detection module 20 outputs a control signal of a second level to control the voltage recovery module 40 to provide a second voltage to the power output terminal 50 through the internal power supply of the integrated chip, where the second voltage output by the power output terminal 50 is unrelated to the first voltage input by the power input terminal 10. The function of reading data of the nonvolatile memory can be realized.
In this embodiment, the first level control signal is a low level control signal, and the second level control signal is a high level control signal.
Therefore, the existing power supply pin of the integrated chip is utilized, and an additional power supply circuit is not needed, so that the voltage required by reading, writing and erasing data can be provided for the nonvolatile memory in the integrated chip, the design is greatly simplified, and the cost is saved.
Referring to fig. 2, fig. 2 is a circuit diagram of a preferred embodiment of the present invention. In this embodiment, the power input terminal 10 is connected to a power pin of the integrated circuit, and inputs the first voltage VPP. The voltage detection module 20 comprises four resistors R1-R4, two comparators COMP1-COMP2 and a NAND gate NAND 1. One end of the resistor R1 is electrically connected to the power input terminal 10, the other end of the resistor R1 is electrically connected to one end of the resistor R2, and a node P1 is formed between the resistor R1 and the resistor R2. The other end of the resistor R2 is grounded. One end of the resistor R3 is electrically connected to the power input terminal 10, the other end of the resistor R3 is electrically connected to one end of the resistor R4, and a node P2 is formed between the resistor R3 and the resistor R4. The other end of the resistor R4 is grounded. An inverting input terminal of the comparator COMP1 is electrically connected to the node P1. An inverting input terminal of the comparator COMP2 is electrically connected to the node P2. The non-inverting input terminal of the comparator COMP1 and the non-inverting input terminal of the comparator COMP2 are both electrically connected to a reference voltage VREF, and in the present embodiment, the reference voltage VREF is generated by an internal power supply VDD of an integrated chip. An output end of the comparator COMP1 and an output end of the comparator COMP2 are electrically connected to a first input end and a second input end of the NAND gate NAND1, respectively. The output end of the NAND gate NAND1 is electrically connected to the switch control module 30 and the voltage recovery module 40.
The switch control module 30 includes a resistor R5, a current source IBIAS1, and four electronic switches Q1-Q4. The first end of the electronic switch Q1 is electrically connected with the output end of the NAND gate 1, the second end of the electronic switch Q1 is grounded, and the third end of the electronic switch Q1 is electrically connected with the first end of the electronic switch Q2. The first terminal of the electronic switch Q2 is further electrically connected to the first terminal of the electronic switch Q3, the second terminal of the electronic switch Q2 is grounded, the third terminal of the electronic switch Q2 is electrically connected to the first terminal of the electronic switch Q2, and the third terminal of the electronic switch Q2 is further electrically connected to one terminal of the current source IBIAS 1. The other terminal of the current source IBIAS1 is electrically connected to the internal power supply VDD of the integrated chip. The second terminal of the electronic switch Q3 is grounded, the third terminal of the electronic switch Q3 is electrically connected to the power input terminal 10 through the resistor R5, and the third terminal of the electronic switch Q3 is also electrically connected to the first terminal of the electronic switch Q4. The second terminal of the electronic switch Q4 is electrically connected to the power input terminal 10, and the third terminal of the electronic switch Q4 is electrically connected to the power output terminal 50.
The voltage recovery module 40 includes an inverter INV1, a current source IBIAS2, a diode D1, a capacitor C1, and three electronic switches Q5-Q7. The input end of the not gate INV1 is electrically connected with the output end of the NAND gate 1, and the output end of the not gate INV1 is electrically connected with the first end of the electronic switch Q5. The second terminal of the electronic switch Q5 is grounded, and the third terminal of the electronic switch Q5 is electrically connected to the first terminal of the electronic switch Q6. The first terminal of the electronic switch Q6 is further electrically connected to the first terminal of the electronic switch Q7, the second terminal of the electronic switch Q6 is grounded, the third terminal of the electronic switch Q6 is electrically connected to the first terminal of the electronic switch Q6, and the third terminal of the electronic switch Q6 is further electrically connected to one terminal of the current source IBIAS 2. The other terminal of the current source IBIAS2 is electrically connected to the internal power supply VDD of the integrated chip. The second terminal of the electronic switch Q7 is grounded, and the third terminal of the electronic switch Q7 is electrically connected to the power output terminal 50. The anode of the diode D1 is electrically connected to the internal power supply VDD of the integrated chip, and the cathode of the diode D1 is electrically connected to the power supply output terminal 50. One end of the capacitor C1 is electrically connected to the power output terminal 50, and the other end of the capacitor C1 is grounded.
When the circuit works, the resistor R1 and the resistor R2 divide the first voltage APP input by the power output terminal 10, so that the voltage at the inverting input terminal of the comparator COMP1 is V _ R1, wherein,
similarly, the resistor R3 and the resistor R4 divide the first voltage APP input by the power output terminal 10, so that the inverting input terminal of the comparator COMP2Is V _ R2, wherein,
when the first voltage VPP inputted from the power output terminal 10 satisfies the formula:
(1) when the NAND gate NAND1 outputs a low level control signal. At this time, the electronic switch Q1 is turned off, the reference current Iref generated by the current source IBIAS1 generates the bias voltage of the electronic switch Q2 and the electronic switch Q3 through the electronic switch Q2, and specifically, the electronic switch Q2 and the electronic switch Q3 constitute a current mirror circuit to mirror the current flowing through the electronic switch Q2 to the electronic switch Q3, and the current generates the bias voltage through R3, so as to control the electronic switch Q4 to be turned on. In this way, the output voltage of the output terminal 50 is equal to the first voltage VPP input from the power input terminal 10, thereby implementing the function of writing or erasing data in the nonvolatile memory.
When the first voltage VPP inputted from the power supply output terminal 10 does not satisfy the formula (1), the NAND gate NAND1 outputs a control signal of high level. At this time, the electronic switch Q1 is turned on, the current generated by the current source IBIAS1 passes through the electronic switch Q2 and is pulled down to the ground by the electronic switch Q1, the electronic switch Q3 cannot mirror the current of the electronic switch Q2, no current flows through the resistor R3, the voltage required by the electronic switch Q4 to turn on cannot be generated, the electronic switch Q4 is turned off, and the output voltage of the power output terminal 50 is unrelated to the first voltage VPP input by the power input terminal 10. At the same time, the electronic switch Q5 is turned off, and the reference current generated by the current source IBIAS2 generates the bias voltages of the electronic switch Q6 and the electronic switch Q7 through the electronic switch Q6, and specifically, the electronic switch Q6 and the electronic switch Q7 constitute a current mirror circuit to mirror the current flowing through the electronic switch Q6 onto the electronic switch Q7, so as to provide a pull-down current to the power output 50, and when the voltage of the power output 50 is pulled to a certain value, the diode D1 is turned on in the forward direction, so as to clamp the output voltage of the power output 50 to a second voltage slightly lower than the voltage value of the internal power VDD of the integrated chip. The capacitor C1 is a filter capacitor and is used for stabilizing the output voltage of the power output terminal. In this way, the function of reading data of the nonvolatile memory can be realized.
In this embodiment, the resistor R5 and the reference current Iref generated by the current source IBIAS1 are used to set the on-voltage VON of the electronic switch Q4, where VON — R5 × Iref.
In this embodiment, the electronic switches Q1-Q3 and Q5-Q7 are N-channel fets, and the first, second, and third terminals of the electronic switches Q1-Q3 and Q5-Q7 correspond to the gate, source, and drain of the N-channel fets, respectively. The electronic switch Q4 is a P-channel field effect transistor, and the first end, the second end and the third end of the electronic switch Q4 correspond to the grid electrode, the source electrode and the drain electrode of the P-channel field effect transistor respectively.
The nonvolatile memory power supply circuit detects whether a first voltage input to a power pin of an integrated chip is in a voltage range required by the nonvolatile memory when data is written or erased through the voltage detection module 20, and is turned on through the switch control module 30 when a detection result is that the first voltage is in the voltage range required by the nonvolatile memory when the data is written or erased so that the first voltage directly supplies power to the nonvolatile memory, and outputs a second voltage through a low-voltage power supply inside the integrated chip when the detection result is that the first voltage is not in the voltage range required by the nonvolatile memory when the data is written or erased through the voltage recovery module 40 so as to supply power to the nonvolatile memory. Therefore, the utility model discloses an existing power pin of integrated chip, and need not extra power supply circuit, can provide reading, write in and the required voltage when erasing of data for nonvolatile memory in the integrated chip, greatly simplify the design, practice thrift the cost.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (6)
1. A non-volatile memory power supply circuit is integrated in an integrated chip with a non-volatile memory, and comprises a power input end and a power output end, wherein the power input end is electrically connected with a power pin of the integrated chip and used for inputting a first voltage, the power output end is electrically connected with the non-volatile memory and used for supplying power to the non-volatile memory, the non-volatile memory power supply circuit is characterized by further comprising a voltage detection module, a switch control module and a voltage recovery module, one end of the voltage detection module is electrically connected with the power input end, the other end of the voltage detection module is electrically connected with the switch control module and the voltage recovery module, and the switch control module is electrically connected between the power input end and the power output end, the voltage recovery module is further electrically connected with the power output end, the voltage detection module is used for detecting whether the first voltage is in a preset voltage range, the switch control module is used for controlling the power input end to provide the first voltage to the power output end when the first voltage is in the preset voltage range, and the voltage detection module is used for providing the second voltage to the power output end through the internal power supply of the integrated chip when the first voltage is not in the preset voltage range.
2. The circuit of claim 1, wherein the voltage detection module comprises a NAND gate, a first comparator, a second comparator, and a first resistor to a fourth resistor, one end of the first resistor is electrically connected to the power input terminal, the other end of the first resistor is electrically connected to one end of the second resistor, a first node is formed between the first resistor and the second resistor, the other end of the second resistor is grounded, one end of the third resistor is electrically connected to the power input terminal, the other end of the third resistor is electrically connected to one end of the fourth resistor, a second node is formed between the third resistor and the fourth resistor, the other end of the fourth resistor is grounded, an inverting input terminal of the first comparator is electrically connected to the first node, and an inverting input terminal of the second comparator is electrically connected to the second node, the non-inverting input end of the first comparator and the non-inverting input end of the second comparator are both electrically connected to a reference voltage, the output end of the first comparator and the output end of the second comparator are respectively electrically connected with the first input end and the second input end of the NAND gate, and the output end of the NAND gate is electrically connected with the switch control module and the voltage recovery module.
3. The circuit of claim 2, wherein the switch control module comprises a fifth resistor, a first current source, and first to fourth electronic switches, a first terminal of the first electronic switch is electrically connected to the output terminal of the NAND gate, a second terminal of the first electronic switch is grounded, a third terminal of the first electronic switch is electrically connected to the first terminal of the second electronic switch, a first terminal of the second electronic switch is further electrically connected to the first terminal of the third electronic switch, a second terminal of the second electronic switch is grounded, a third terminal of the second electronic switch is electrically connected to the first terminal of the second electronic switch, a third terminal of the second electronic switch is further electrically connected to a terminal of the first current source, and another terminal of the first current source is electrically connected to the internal power supply of the integrated chip, the second terminal of the third electronic switch is grounded, the third terminal of the third electronic switch is electrically connected to the power input terminal through the fifth resistor, the third terminal of the third electronic switch is also electrically connected to the first terminal of the fourth electronic switch, the second terminal of the fourth electronic switch is electrically connected to the power input terminal, and the third terminal of the fourth electronic switch is electrically connected to the power output terminal.
4. The circuit of claim 3, wherein the voltage recovery module comprises a NOT gate, a second current source, a diode, and a fifth to seventh electronic switches, wherein an input of the NOT gate is electrically connected to an output of the NAND gate, an output of the NOT gate is electrically connected to a first terminal of the fifth electronic switch, a second terminal of the fifth electronic switch is grounded, a third terminal of the fifth electronic switch is electrically connected to a first terminal of the sixth electronic switch, the first terminal of the sixth electronic switch is further electrically connected to a first terminal of the seventh electronic switch, the second terminal of the sixth electronic switch is grounded, the third terminal of the sixth electronic switch is electrically connected to the first terminal of the sixth electronic switch, and the third terminal of the sixth electronic switch is further electrically connected to a terminal of the second current source, the other end of the second current source is electrically connected to an internal power supply of the integrated chip, the second end of the seventh electronic switch is grounded, the third end of the seventh electronic switch is electrically connected with the power supply output end, the anode of the diode is electrically connected with the internal power supply of the integrated chip, and the cathode of the diode is electrically connected with the power supply output end.
5. The circuit of claim 4, wherein the first to third electronic switches and the fifth to seventh electronic switches are N-channel FETs, first, second, and third ends of the first to third and fifth to seventh electronic switches respectively correspond to a gate, a source, and a drain of the N-channel FETs, the fourth electronic switch is a P-channel FET, and first, second, and third ends of the fourth electronic switch respectively correspond to a gate, a source, and a drain of the P-channel FETs.
6. The power supply circuit of claim 1, wherein the preset voltage range is a voltage range required for writing or erasing data in the nonvolatile memory.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020013631.8U CN211555472U (en) | 2020-01-03 | 2020-01-03 | Nonvolatile memory power supply circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020013631.8U CN211555472U (en) | 2020-01-03 | 2020-01-03 | Nonvolatile memory power supply circuit |
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| CN211555472U true CN211555472U (en) | 2020-09-22 |
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