CN111081291B - Nonvolatile memory power supply circuit and method thereof - Google Patents
Nonvolatile memory power supply circuit and method thereof Download PDFInfo
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- CN111081291B CN111081291B CN202010003751.4A CN202010003751A CN111081291B CN 111081291 B CN111081291 B CN 111081291B CN 202010003751 A CN202010003751 A CN 202010003751A CN 111081291 B CN111081291 B CN 111081291B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a nonvolatile memory power supply circuit which is integrated in an integrated chip with a nonvolatile memory and comprises a power input end and a power output end, wherein the power input end is electrically connected with a power pin of the integrated chip and is used for inputting a first voltage, and the power output end is used for supplying power to the nonvolatile memory. The nonvolatile memory power supply circuit further comprises a voltage detection module, a switch control module and a voltage recovery module, wherein the voltage detection module is used for detecting whether the first voltage is in a preset voltage range. The switch control module is used for being conducted when the first voltage is within a preset voltage range, so that the power input end provides the first voltage to the power output end. The voltage recovery module is used for providing a second voltage to the power output end when the first voltage is not in a preset voltage range. The invention also provides a power supply method of the nonvolatile memory. Thus, the design can be simplified and the cost can be saved.
Description
Technical Field
The present invention relates to the field of power supply, and in particular, to a power supply circuit for a nonvolatile memory and a method thereof.
Background
Nonvolatile Memory (NVM) is widely used in integrated circuit chips, and it is known that external power is required for reading, writing or erasing data from the NVM, and particularly, when writing or erasing data, the NVM Memory is damaged due to a high voltage, insufficient data writing is caused due to a low voltage, and the data storage reliability of the NVM is reduced in both cases.
The prior art solutions have two schemes of an internal charge pump circuit and an external power supply pin. The scheme of the built-in charge pump circuit is difficult to design and occupies a large chip area due to the relatively complex charge pump structure, and has certain risk and additional cost. And the external power supply pin scheme can introduce additional package pins and additional external power supply, thereby reducing the competitiveness of the product.
Disclosure of Invention
In view of this, it is necessary to provide a power supply circuit and method for a nonvolatile memory, which can provide the voltage required for reading, writing and erasing data for the nonvolatile memory in the integrated chip through the existing power pin and internal power supply of the integrated chip, thereby simplifying the design and saving the cost.
The technical scheme provided by the invention for achieving the purpose is as follows:
the nonvolatile memory power supply circuit is integrated in an integrated chip with a nonvolatile memory, and comprises a power input end and a power output end, wherein the power input end is electrically connected with a power pin of the integrated chip and is used for inputting first voltage, the power output end is electrically connected with the nonvolatile memory and is used for supplying power to the nonvolatile memory, the nonvolatile memory power supply circuit further comprises a voltage detection module, a switch control module and a voltage recovery module, one end of the voltage detection module is electrically connected with the power input end, the other end of the voltage detection module is electrically connected with the switch control module and the voltage recovery module, the switch control module is electrically connected between the power input end and the power output end, the voltage recovery module is also electrically connected with the power output end, and the voltage detection module is used for detecting whether the first voltage is in a preset voltage range and outputting a control signal to the switch control module and the voltage recovery module according to a detection result;
when the first voltage is within the preset voltage range, the voltage detection module outputs a control signal of a first level to control the switch control module to be conducted, so that the power input end provides the first voltage to the power output end;
when the first voltage is not in the preset voltage range, the voltage detection module outputs a control signal of a second level to control the voltage recovery module to provide the second voltage to the power output end through an internal power supply of the integrated chip.
Further, the voltage detection module comprises a nand gate, a first comparator, a second comparator and first to fourth resistors, one end of the first resistor is electrically connected with the power input end, the other end of the first resistor is electrically connected with one end of the second resistor, a first node is formed between the first resistor and the second resistor, the other end of the second resistor is grounded, one end of the third resistor is electrically connected with the power input end, the other end of the third resistor is electrically connected with one end of the fourth resistor, a second node is formed between the third resistor and the fourth resistor, the other end of the fourth resistor is grounded, the inverting input end of the first comparator is electrically connected with the first node, the inverting input end of the second comparator is electrically connected with the second node, the non-inverting input end of the first comparator and the non-inverting input end of the second comparator are electrically connected to a reference voltage, the output end of the first comparator and the output end of the second comparator are respectively electrically connected with the first input end of the second comparator and the nand gate, and the output end of the second comparator is electrically connected with the nand gate.
Further, the switch control module includes a fifth resistor, a first current source, and first to fourth electronic switches, where a first end of the first electronic switch is electrically connected to an output end of the nand gate, a second end of the first electronic switch is grounded, a third end of the first electronic switch is electrically connected to a first end of the second electronic switch, the first end of the second electronic switch is also electrically connected to a first end of the third electronic switch, a second end of the second electronic switch is grounded, a third end of the second electronic switch is electrically connected to a first end of the second electronic switch, a third end of the second electronic switch is also electrically connected to one end of the first current source, another end of the first current source is electrically connected to an internal power supply of the integrated chip, a second end of the third electronic switch is grounded, a third end of the third electronic switch is electrically connected to the power supply input end through the fifth resistor, a third end of the third electronic switch is also electrically connected to a third end of the fourth electronic switch, a third end of the third electronic switch is electrically connected to a fourth end of the fourth electronic switch, and a third end of the fourth electronic switch is electrically connected to the fourth end of the fourth electronic switch.
Further, the voltage recovery module includes a not gate, a second current source, a diode, and a fifth to seventh electronic switches, the input end of the not gate is electrically connected to the output end of the not gate, the output end of the not gate is electrically connected to the first end of the fifth electronic switch, the second end of the fifth electronic switch is grounded, the third end of the fifth electronic switch is electrically connected to the first end of the sixth electronic switch, the first end of the sixth electronic switch is further electrically connected to the first end of the seventh electronic switch, the second end of the sixth electronic switch is grounded, the third end of the sixth electronic switch is electrically connected to the first end of the sixth electronic switch, the third end of the sixth electronic switch is further electrically connected to one end of the second current source, the other end of the second current source is electrically connected to an internal power supply of the integrated chip, the second end of the seventh electronic switch is grounded, the third end of the seventh electronic switch is electrically connected to the power output end of the power supply, the second end of the diode is electrically connected to the internal power supply of the integrated chip, and the output end of the cathode is electrically connected to the diode.
Further, the first to third and fifth to seventh electronic switches are N-channel field effect transistors, the first to third and fifth to seventh electronic switches have first, second and third ends corresponding to the gate, source and drain of the N-channel field effect transistor, respectively, and the fourth electronic switch is a P-channel field effect transistor, and the first, second and third ends corresponding to the gate, source and drain of the P-channel field effect transistor, respectively.
Further, the control signal of the first level is a control signal of a low level, and the control signal of the second level is a control signal of a high level.
Further, the preset voltage range is a voltage range required by the nonvolatile memory when writing or erasing data.
A method of powering a non-volatile memory, comprising the steps of:
providing a first voltage through a power pin of the integrated chip;
detecting whether the first voltage is within a preset voltage range or not, and outputting a control signal according to a detection result;
when the first voltage is in the preset voltage range, outputting a control signal of a first level to control the first voltage to supply power for the nonvolatile memory;
and when the first voltage is not in the preset voltage range, outputting a control signal of a second level to control an internal power supply of the integrated chip to provide the second voltage so as to supply power for the nonvolatile memory.
Further, the preset voltage range is a voltage range required by the nonvolatile memory when writing or erasing data.
Further, the control signal of the first level is a control signal of a low level, and the control signal of the second level is a control signal of a high level.
The power supply circuit of the nonvolatile memory and the method thereof detect whether the first voltage provided by the power supply pin of the integrated chip to the power supply input end is in a preset voltage range or not through the voltage detection module, and conduct the first voltage to the power supply output end through the switch control module when the detection result is that the first voltage is in the preset voltage range, so as to realize the function of writing or erasing data of the nonvolatile memory. And when the detection result is that the first voltage is not in the preset voltage range, the voltage recovery module is used for providing a second voltage to the power output end by utilizing an internal power supply of the integrated chip so as to realize the data reading function of the nonvolatile memory. Therefore, the voltage required by reading, writing and erasing of the data can be provided for the nonvolatile memory in the integrated chip through the existing power pins of the integrated chip without an additional power circuit, so that the design is greatly simplified, and the cost is saved.
Drawings
FIG. 1 is a block diagram of a preferred embodiment of a non-volatile memory power supply circuit of the present invention.
FIG. 2 is a circuit diagram of a preferred embodiment of a non-volatile memory power supply circuit according to the present invention.
FIG. 3 is a flow chart of a method of powering a non-volatile memory in accordance with the present invention.
Description of the main reference signs
Nonvolatile memory power supply circuit 100
Power input terminal 10
Voltage detection module 20
Switch control module 30
Voltage recovery module 40
Power supply output terminal 50
Nodes P1, P2
Current source IBIAS1, IBIAS2
Capacitor C1
Resistors R1-R5
Diode D1
Electronic switches Q1-Q7
Comparator COMP1, COMP2
NOT gate INV1
NAND gate NAND1
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, the present invention provides a nonvolatile memory power supply circuit 100. The nonvolatile memory power supply circuit 100 includes a power input terminal 10, a voltage detection module 20, a switch control module 30, a voltage recovery module 40, and a power output terminal 50. In this embodiment, the nonvolatile memory power supply circuit 100 is integrated in an integrated chip to supply power to a nonvolatile memory (not shown) built in the integrated circuit.
In this embodiment, the power input terminal 10 is electrically connected to a power pin (not shown) of the integrated circuit. One end of the voltage detection module 20 is electrically connected to the power input terminal 10, and the other end of the voltage detection module 20 is electrically connected to the switch control module 30 and the voltage recovery module 40. The switch control module 30 is electrically connected between the power input terminal 10 and the power output terminal 50. The voltage recovery module 40 is also electrically connected to the power output 50. The power output 50 is electrically connected to the non-volatile memory.
The power input terminal 10 is used for inputting a first voltage. The voltage detection module 20 is configured to detect whether the first voltage is within a preset voltage range, and output a control signal to the switch control module 30 and the voltage recovery module 40 according to a detection result. In this embodiment, the preset voltage range is a voltage range required when the nonvolatile memory writes or erases data.
When the first voltage is within the preset voltage range, the voltage detection module 20 outputs a control signal of a first level to control the switch control module 30 to be turned on, so that the power input terminal 10 provides the first voltage to the power output terminal 50. Thus, the function of writing or erasing data of the nonvolatile memory can be realized.
When the first voltage is not within the preset voltage range, the voltage detection module 20 outputs a control signal of a second level to control the voltage recovery module 40 to provide the second voltage to the power output terminal 50 through the internal power supply of the integrated chip, and the second voltage output by the power output terminal 50 is irrelevant to the first voltage input by the power input terminal 10. Thus, the function of reading data of the nonvolatile memory can be realized.
In this embodiment, the control signal of the first level is a control signal of a low level, and the control signal of the second level is a control signal of a high level.
Therefore, the existing power supply pins of the integrated chip are utilized, and extra power supply circuits are not needed, so that voltages required by reading, writing and erasing of data can be provided for the nonvolatile memory in the integrated chip, the design is greatly simplified, and the cost is saved.
Referring to fig. 2, fig. 2 is a circuit connection diagram of a preferred embodiment of the present invention. In this embodiment, the power input terminal 10 is connected to a power pin point of the integrated circuit, and inputs the first voltage VPP. The voltage detection module 20 includes four resistors R1-R4, two comparators COMP1-COMP2, and a NAND gate NAND1. One end of the resistor R1 is electrically connected to the power input terminal 10, the other end of the resistor R1 is electrically connected to one end of the resistor R2, and a node P1 is formed between the resistor R1 and the resistor R2. The other end of the resistor R2 is grounded. One end of the resistor R3 is electrically connected to the power input terminal 10, the other end of the resistor R3 is electrically connected to one end of the resistor R4, and a node P2 is formed between the resistor R3 and the resistor R4. The other end of the resistor R4 is grounded. An inverting input terminal of the comparator COMP1 is electrically connected to the node P1. The inverting input of the comparator COMP2 is electrically connected to the node P2. The non-inverting input terminal of the comparator COMP1 and the non-inverting input terminal of the comparator COMP2 are both electrically connected to a reference voltage VREF, which in this embodiment is generated by an internal power supply VDD of the integrated chip. The output end of the comparator COMP1 and the output end of the comparator COMP2 are electrically connected to the first input end and the second input end of the NAND gate NAND1, respectively. The output end of the NAND gate NAND1 is electrically connected to the switch control module 30 and the voltage recovery module 40.
The switch control module 30 includes a resistor R5, a current source IBIAS1, and four electronic switches Q1-Q4. The first end of the electronic switch Q1 is electrically connected to the output end of the NAND gate NAND1, the second end of the electronic switch Q1 is grounded, and the third end of the electronic switch Q1 is electrically connected to the first end of the electronic switch Q2. The first end of the electronic switch Q2 is further electrically connected to the first end of the electronic switch Q3, the second end of the electronic switch Q2 is grounded, the third end of the electronic switch Q2 is electrically connected to the first end of the electronic switch Q2, and the third end of the electronic switch Q2 is further electrically connected to one end of the current source IBIAS 1. The other end of the current source IBIAS1 is electrically connected to the internal power supply VDD of the integrated chip. The second end of the electronic switch Q3 is grounded, the third end of the electronic switch Q3 is electrically connected to the power input end 10 through the resistor R5, and the third end of the electronic switch Q3 is further electrically connected to the first end of the electronic switch Q4. A second terminal of the electronic switch Q4 is electrically connected to the power input terminal 10, and a third terminal of the electronic switch Q4 is electrically connected to the power output terminal 50.
The voltage recovery module 40 includes a NOT gate INV1, a current source IBIAS2, a diode D1, a capacitor C1, and three electronic switches Q5-Q7. An input end of the NOT gate INV1 is electrically connected with an output end of the NOT gate NAND1, and an output end of the NOT gate INV1 is electrically connected with a first end of the electronic switch Q5. The second end of the electronic switch Q5 is grounded, and the third end of the electronic switch Q5 is electrically connected with the first end of the electronic switch Q6. The first end of the electronic switch Q6 is further electrically connected to the first end of the electronic switch Q7, the second end of the electronic switch Q6 is grounded, the third end of the electronic switch Q6 is electrically connected to the first end of the electronic switch Q6, and the third end of the electronic switch Q6 is further electrically connected to one end of the current source IBIAS 2. The other end of the current source IBIAS2 is electrically connected to the internal power supply VDD of the integrated chip. The second end of the electronic switch Q7 is grounded, and the third end of the electronic switch Q7 is electrically connected to the power output terminal 50. The anode of the diode D1 is electrically connected to the internal power supply VDD of the integrated chip, and the cathode of the diode D1 is electrically connected to the power output terminal 50. One end of the capacitor C1 is electrically connected to the power output terminal 50, and the other end of the capacitor C1 is grounded.
In operation, the resistor R1 and the resistor R2 divide the first voltage APP input from the power output terminal 10, so that the voltage at the inverting input terminal of the comparator COMP1 is v_r1, wherein,similarly, the resistor R3 and the resistor R4 divide the first voltage APP input from the power output terminal 10, so that the voltage at the inverting input terminal of the comparator COMP2 is v_r2, where->When the first voltage VPP input by the power output terminal 10 satisfies the formula: />At this time, the NAND gate NAND1 will output a control signal of low level. At this time, the electronic switch Q1 is turned off, the reference current Iref generated by the current source IBIAS1 generates a bias voltage of the electronic switch Q2 and the electronic switch Q3 through the electronic switch Q2, specifically, the electronic switch Q2 and the electronic switch Q3 form a current mirror circuit to mirror a current flowing through the electronic switch Q2 onto the electronic switch Q3, and the current generates a bias voltage through R3, thereby controlling the electronic switch Q4 to be turned on. In this way, the output voltage of the output terminal 50 will be equal to the first voltage VPP of the input of the power input terminal 10, so as to implement the function of writing or erasing data in the nonvolatile memory.
When the first voltage VPP input from the power output terminal 10 does not satisfy the formula (1), the NAND gate NAND1 outputs a control signal of a high level. At this time, the electronic switch Q1 is turned on, the current generated by the current source IBIAS1 passes through the electronic switch Q2 and is pulled down to the ground by the electronic switch Q1, the electronic switch Q3 cannot mirror the current of the electronic switch Q2, no current flows through the resistor R3, the voltage required for turning on the electronic switch Q4 cannot be generated, the electronic switch Q4 is turned off, and at this time, the output voltage of the power output terminal 50 is irrelevant to the first voltage VPP input by the power input terminal 10. Meanwhile, the electronic switch Q5 is turned off, the reference current generated by the current source IBIAS2 generates bias voltages of the electronic switch Q6 and the electronic switch Q7 through the electronic switch Q6, specifically, the electronic switch Q6 and the electronic switch Q7 form a current mirror circuit to mirror a current flowing through the electronic switch Q6 onto the electronic switch Q7, so as to provide a pull-down current to the power output terminal 50, and when the voltage of the power output terminal 50 is pulled to a certain value, the diode D1 is turned on in a forward direction, so as to clamp the output voltage of the power output terminal 50 at a second voltage slightly lower than the voltage value of the internal power supply VDD of the integrated chip. The capacitor C1 is a filter capacitor and is used for stabilizing the output voltage of the power supply output end. Thus, the function of the nonvolatile memory for reading data can be realized.
In this embodiment, the resistor R5 and the reference current Iref generated by the current source IBIAS1 are used to set the on voltage VON of the electronic switch Q4, where von=r5×iref.
In this embodiment, the electronic switches Q1-Q3 and the electronic switches Q5-Q7 are N-channel field effect transistors, and the first ends, the second ends and the third ends of the electronic switches Q1-Q3 and the electronic switches Q5-Q7 correspond to the gate, the source and the drain of the N-channel field effect transistor respectively. The electronic switch Q4 is a P-channel field effect transistor, and the first end, the second end and the third end of the electronic switch Q4 respectively correspond to the grid electrode, the source electrode and the drain electrode of the P-channel field effect transistor.
Referring to fig. 3, the invention further provides a power supply method of the power supply circuit of the nonvolatile memory, which comprises the following steps of;
s1, the power input end 10 provides a first voltage through a power pin of the integrated chip.
S2, the voltage detection module 20 detects whether the first voltage is within a preset voltage range, and outputs a control signal to the switch control module 30 and the voltage recovery module 40 according to the detection result, if yes, the step S3 is entered, otherwise the step S4 is entered.
In this embodiment, the preset voltage range is a voltage range required when the nonvolatile memory writes or erases data.
S3, the voltage detection module 20 outputs a control signal of a first level to control the switch control module 30 to be turned on, and the power input terminal 10 provides the first voltage to the power output terminal 50 to supply power to the nonvolatile memory.
In this embodiment, the control signal of the first level is a control signal of a low level.
S4, the voltage detection module 20 outputs a control signal of a second level to control the voltage recovery module 40 to provide a second voltage to the power output terminal 50 through the internal power supply of the integrated chip so as to supply power to the nonvolatile memory.
In this embodiment, the control signal of the second level is a control signal of a high level.
The above-mentioned nonvolatile memory power supply circuit and method detects whether the first voltage input by the power pin of the integrated chip is within the voltage range required when the nonvolatile memory writes or erases data through the voltage detection module 20, and is conducted when the detection result is that the first voltage is within the voltage range required when the nonvolatile memory writes or erases data through the switch control module 30, so that the first voltage directly supplies power to the nonvolatile memory, and also outputs a second voltage through the internal power supply of the integrated chip when the detection result is that the first voltage is not within the voltage range required when the nonvolatile memory writes or erases data through the voltage recovery module 40, so as to supply power to the nonvolatile memory. Therefore, the invention can provide the voltage required by reading, writing and erasing of the data for the nonvolatile memory in the integrated chip through the existing power pin of the integrated chip without an additional power circuit, thereby greatly simplifying the design and saving the cost.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. The nonvolatile memory power supply circuit is integrated in an integrated chip with a nonvolatile memory and comprises a power input end and a power output end, wherein the power input end is electrically connected with a power pin of the integrated chip and is used for inputting a first voltage, the power output end is electrically connected with the nonvolatile memory and is used for supplying power to the nonvolatile memory, and the nonvolatile memory power supply circuit is characterized by further comprising a voltage detection module, a switch control module and a voltage recovery module, one end of the voltage detection module is electrically connected with the power input end, the other end of the voltage detection module is electrically connected with the switch control module and the voltage recovery module, the switch control module is electrically connected between the power input end and the power output end, the voltage recovery module is also electrically connected with the power output end, and the voltage detection module is used for detecting whether the first voltage is in a preset voltage range or not and outputting a control signal to the switch control module and the voltage recovery module according to a detection result, wherein the preset voltage range is a voltage range required by writing or erasing data in the nonvolatile memory;
when the first voltage is within the preset voltage range, the voltage detection module outputs a low-level control signal to control the switch control module to be conducted, so that the power input end provides the first voltage to the power output end;
when the first voltage is not in the preset voltage range, the voltage detection module outputs a high-level control signal to control the voltage recovery module to provide a second voltage to the power output end through an internal power supply of the integrated chip.
2. The power supply circuit of claim 1, wherein the voltage detection module comprises a nand gate, a first comparator, a second comparator, and first to fourth resistors, one end of the first resistor is electrically connected to the power input terminal, the other end of the first resistor is electrically connected to one end of the second resistor, a first node is formed between the first resistor and the second resistor, the other end of the second resistor is grounded, one end of the third resistor is electrically connected to the power input terminal, the other end of the third resistor is electrically connected to one end of the fourth resistor, a second node is formed between the third resistor and the fourth resistor, the other end of the fourth resistor is grounded, the inverting input terminal of the first comparator is electrically connected to the first node, the inverting input terminal of the second comparator is electrically connected to the second node, the non-inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator are both electrically connected to a reference voltage, and the output terminal of the first comparator and the output terminal of the second comparator are electrically connected to the nand gate respectively.
3. The non-volatile memory power supply circuit of claim 2, wherein the switch control module comprises a fifth resistor, a first current source, and first to fourth electronic switches, a first end of the first electronic switch is electrically connected to the output of the nand gate, a second end of the first electronic switch is grounded, a third end of the first electronic switch is electrically connected to a first end of a second electronic switch, a first end of the second electronic switch is further electrically connected to a first end of a third electronic switch, a second end of the second electronic switch is grounded, a third end of the second electronic switch is further electrically connected to a first end of the second electronic switch, a third end of the second electronic switch is further electrically connected to one end of the first current source, another end of the first current source is electrically connected to an internal power supply of the integrated chip, a second end of the third electronic switch is grounded, a third end of the third electronic switch is electrically connected to the power supply input end through the fifth resistor, a third end of the third electronic switch is further electrically connected to a third end of the fourth electronic switch, and a third end of the fourth electronic switch is electrically connected to the third end of the fourth electronic switch.
4. The non-volatile memory power supply circuit of claim 3, wherein the voltage recovery module comprises a not gate, a second current source, a diode, and a fifth to seventh electronic switch, wherein an input end of the not gate is electrically connected to an output end of the not gate, an output end of the not gate is electrically connected to a first end of the fifth electronic switch, a second end of the fifth electronic switch is grounded, a third end of the fifth electronic switch is electrically connected to a first end of a sixth electronic switch, the first end of the sixth electronic switch is further electrically connected to a first end of the seventh electronic switch, a second end of the sixth electronic switch is grounded, a third end of the sixth electronic switch is electrically connected to a first end of the sixth electronic switch, a third end of the sixth electronic switch is further electrically connected to one end of the second current source, another end of the second current source is electrically connected to an internal power supply of the integrated chip, a second end of the seventh electronic switch is grounded, a third end of the seventh electronic switch is further electrically connected to a first end of the seventh electronic switch, a third end of the output switch is electrically connected to an internal power supply of the integrated chip, and the diode is electrically connected to an output end of the integrated chip.
5. The non-volatile memory power circuit of claim 4, wherein the first electronic switch, the second electronic switch, the third electronic switch, the fifth electronic switch, the sixth electronic switch, and the seventh electronic switch are N-channel field effect transistors, wherein the first end, the second end, and the third end of the first electronic switch, the second electronic switch, the third electronic switch, the fifth electronic switch, the sixth electronic switch, and the seventh electronic switch respectively correspond to a gate, a source, and a drain of the N-channel field effect transistor, and wherein the fourth electronic switch is a P-channel field effect transistor, and wherein the first end, the second end, and the third end of the fourth electronic switch respectively correspond to a gate, a source, and a drain of the P-channel field effect transistor.
6. A method of powering a non-volatile memory, comprising the steps of:
providing a first voltage through a power pin of the integrated chip;
detecting whether the first voltage is within a preset voltage range or not, and outputting a control signal according to a detection result;
when the first voltage is in the preset voltage range, outputting a low-level control signal to control the first voltage to supply power for the nonvolatile memory;
when the first voltage is not in the preset voltage range, outputting a high-level control signal to control an internal power supply of the integrated chip to provide a second voltage so as to supply power for the nonvolatile memory;
the preset voltage range is a voltage range required by the nonvolatile memory when writing or erasing data.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591687A (en) * | 2003-08-27 | 2005-03-09 | 株式会社瑞萨科技 | Data processing system and nonvolatile memory |
| CN101814508A (en) * | 2009-02-25 | 2010-08-25 | 三星电子株式会社 | Has the transistorized integrated circuit memory devices of selection |
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| US8184488B2 (en) * | 2009-11-20 | 2012-05-22 | Silicon Laboratories Inc. | Systems and methods for controlling integrated circuit operation with below ground pin voltage |
| US8988965B2 (en) * | 2010-11-03 | 2015-03-24 | Shine C. Chung | Low-pin-count non-volatile memory interface |
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| CN101814508A (en) * | 2009-02-25 | 2010-08-25 | 三星电子株式会社 | Has the transistorized integrated circuit memory devices of selection |
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