CN211554226U - Automatic grid voltage generation device used in power amplifier automatic test - Google Patents
Automatic grid voltage generation device used in power amplifier automatic test Download PDFInfo
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- CN211554226U CN211554226U CN201921899977.6U CN201921899977U CN211554226U CN 211554226 U CN211554226 U CN 211554226U CN 201921899977 U CN201921899977 U CN 201921899977U CN 211554226 U CN211554226 U CN 211554226U
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Abstract
The utility model provides a be arranged in power amplifier automatic test grid voltage automatic generation device belongs to the radio frequency microwave field, especially relates to power amplifier technical field. The device comprises a high-precision ultralow-resistance resistor, a current monitoring chip, a precision analog Microprocessor Chip (MCU), an EEPROM chip, a power supply and computer peripheral equipment. Wherein, the power supply supplies power for the power amplifier pre-amplifier stage and the final stage; the power supply circuit is connected with a high-precision ultralow-resistance resistor in series to be matched with a current monitoring chip to complete static current monitoring and convert the static current into an analog voltage value, an ADC (analog to digital converter) interface inside the MCU is used for prejudging the input voltage value, and then two paths of DAC (digital to analog converter) outputs inside the MCU are used for completing dynamic regulation of two-stage power amplifier grid voltage. And programming a program for the MCU through a JTAG interface by the computer peripheral equipment, and automatically adjusting the grid voltage by the program after the computer peripheral equipment is electrified until the static requirement is met.
Description
Technical Field
The utility model belongs to the radio frequency microwave field especially relates to power amplifier technical field.
Background
The innovation of the mobile communication technology not only changes the life style of people deeply, but also promotes the development of national economy. At present, all countries are at the pace of accelerating the development of high-speed networks, and with the large-scale commercial use of 4G networks, the development thereof is becoming mature. The 4G network requires high data transmission rate and multimode transmission, which greatly affects the communication system, the complex modulation mode puts higher requirements on the core module radio frequency power amplifier in the base station, and the research on the radio frequency power amplifier is also the current popular research field.
Radio frequency power amplifiers are an important component of various wireless transmitters. In the front stage circuit of the transmitter, the modulated radio frequency small signal has small power and needs to be subjected to a series of power amplification including a driving stage, a pre-amplification stage and a final amplification stage, and after the radio frequency power with high enough is obtained, the radio frequency small signal can be transmitted through an antenna feed system to realize remote communication. In the current 4G mobile communication network, the radio frequency power device of the Si-based LDMOS has a leading position in the base station market due to the extremely high cost performance. A key factor for ensuring high performance of the LDMOS radio frequency power device is to determine correct bias and meet the static state. Proper biasing may assist linearization techniques in minimizing distortion to ensure that the gain of the amplifier, and thus its distortion level, varies within a specified range.
In the batch production and test of the radio frequency power amplifier, the grid voltage of each chip cannot be designed to be the same value because the grid voltage of the power amplifier chips has difference. To stabilize the same quiescent current, each chip needs to dynamically adjust the gate voltage. The gate voltage of the traditional radio frequency power amplifier is regulated manually until the static current requirement is met, which not only needs professional radio frequency debugging personnel, but also consumes expensive time cost. The utility model discloses a be arranged in power amplifier automation test grid voltage automatic generation device, aim at providing a commonality strong, low cost, the design is simple, convenient operation, save time's device goes up the electricity and can automatically regulated grid voltage, satisfies statically, and the computer can the automatic reading grid voltage parameter, preserves the record, and convenient printing in the future is looked over.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that a grid voltage automatic generation device is provided in being arranged in power amplifier automatic testing.
The utility model discloses the technical scheme who adopts as follows:
a grid voltage automatic generation device used in power amplifier automatic test comprises a high-precision resistor, a current monitoring chip, a precision analog microprocessor chip MCU, an EEPROM chip, a first switch circuit, a second switch circuit, a power supply, a computer peripheral device and a plurality of power amplifiers; the power amplifier comprises a driving stage, a pre-amplifier stage and a final stage;
the power supply is respectively connected with the preventive stage and the final stage of the power amplifier and is used for supplying power to the pre-amplifier stage and the final stage;
the high-precision resistor is connected with the current monitoring chip in parallel and is connected in series with the power supply and the power supply circuits of the prevention stage and the final stage; the device is used for monitoring the quiescent current of a prevention stage and a final stage in a matched manner, converting the quiescent current into an analog voltage value and feeding the analog voltage value back to the MCU;
the precision analog microprocessor chip MCU is respectively connected with the EEPROM chip, the current monitoring chip, the first switch circuit and the second switch circuit, the first switch circuit is connected with the preventive stage, and the second switch circuit is connected with the final stage; the precise analog microprocessor chip MCU is used for setting an initial value of the gate voltage of the preventive stage, biasing the preventive stage through a first switch circuit, and judging the quiescent current according to the analog voltage value of the preventive stage to adjust the gate voltage of the preventive stage; the gate voltage control circuit is also used for setting a final-stage gate voltage initial value after the setting of the gate voltage of the preventive stage is finished, biasing the preventive stage and the final stage through the first switch circuit and the second switch circuit respectively, and judging the quiescent current according to the total analog voltage value to adjust the final-stage gate voltage; writing the pre-amplifier stage grid voltage parameter and the final stage grid voltage parameter into an EEPROM chip;
the computer peripheral equipment is connected with the precision analog microprocessor chip MCU; the device is used for reading pre-amplifier stage grid voltage parameters and final stage grid voltage parameters stored in the MCU of the precision analog microprocessor chip and storing test records.
The first switch circuit and the second switch circuit are analog switches or triodes to build switches.
The precision analog microprocessor chip MCU is connected with the current monitoring chip through an internal ADC interface to prejudge the input analog voltage value; two paths of DACs are respectively connected with a prevention stage and a final stage, and accurate grid voltage values are provided for the prevention stage and the final stage.
The utility model discloses compare prior art's advantage and do:
compared with the prior art, the utility model discloses can the automatic determination grid voltage value, make the power amplifier steady operation at the quiescent point, can assist the linearization technique furthest to reduce the distortion. The technology is used in the batch production of the power amplifier, and can effectively save the labor cost and the time cost.
Drawings
Fig. 1 is a schematic diagram of the hardware connection of the present invention.
Fig. 2 is a flow chart of the present invention.
Detailed Description
The present invention will be described in further detail with reference to fig. 1 and 2 and the following examples.
As shown in fig. 1, the gate voltage automatic generation device for the power amplifier automatic test in this embodiment includes a high-precision resistor, a current monitoring chip, a precision analog microprocessor chip MCU, an EEPROM chip, a first switch circuit, a second switch circuit, a power supply, a computer peripheral device, and a plurality of power amplifiers; each power amplifier comprises three stages of amplification, namely a driving stage, a pre-amplifying stage and a final stage. Only the pre-amplifier stage and the final stage need to accurately determine the grid voltage value, the embodiment includes two stages of power amplifier chips, an external power supply +28V supplies power for the two stages of power amplifiers, a high-precision resistor is connected in series on a power supply path, the high-precision resistor is matched with a current monitoring chip to complete static current monitoring and convert the static current to an analog voltage value, an ADC interface inside the MCU performs pre-judgment on an input voltage value, and then two paths of DAC outputs inside the MCU complete dynamic adjustment on the grid voltage of the two stages of power amplifiers.
The specific connection relationship is as follows:
the power supply is respectively connected with the preventive stage and the final stage of the power amplifier and is used for supplying power to the pre-amplifier stage and the final stage;
the high-precision resistor is connected with the current monitoring chip in parallel and is connected in series with the power supply and the power supply circuits of the prevention stage and the final stage; the device is used for monitoring the quiescent current of a prevention stage and a final stage in a matched manner, converting the quiescent current into an analog voltage value and feeding the analog voltage value back to the MCU;
the precision analog microprocessor chip MCU is respectively connected with the EEPROM chip, the current monitoring chip, the first switch circuit and the second switch circuit, the first switch circuit is connected with the preventive stage, and the second switch circuit is connected with the final stage; the precise analog microprocessor chip MCU is used for setting an initial value of the gate voltage of the preventive stage, biasing the preventive stage through a first switch circuit, and judging the quiescent current according to the analog voltage value transmitted by the current monitoring chip to adjust the gate voltage of the preventive stage; the current monitoring chip is also used for setting a final-stage grid voltage initial value after the setting of the preventive-stage grid voltage is finished, biasing the preventive stage and the final stage through the first switch circuit and the second switch circuit respectively, and judging the quiescent current according to the total analog voltage value transmitted by the current monitoring chip to adjust the final-stage grid voltage; writing the pre-amplifier stage grid voltage parameter and the final stage grid voltage parameter into an EEPROM chip;
the computer peripheral equipment is connected with the precision analog microprocessor chip MCU; the device is used for reading pre-amplifier stage grid voltage parameters and final stage grid voltage parameters stored in the MCU of the precision analog microprocessor chip and storing test records.
The specific implementation process is shown in figure 2.
Step 1: the MCU initializes the grid voltage of the power amplifier pre-amplifier stage, and the grid voltage value is a recommended value of the chip technical manual;
step 2: the MCU opens the first switch circuit to bias the pre-amplifier stage;
and step 3: the high-precision resistor is matched with the current monitoring chip to complete drain current monitoring, current is converted into voltage, and an ADC (analog to digital converter) interface of the MCU reads the voltage;
and 4, step 4: the MCU closes the first switch circuit; the purpose is to avoid the power amplifier from being electrified for a long time, the ambient temperature changes, and the grid voltage under the normal temperature environment can not be accurately determined. For grid voltage at different temperatures, static state can be stabilized by adding compensation values for normal-temperature grid voltage parameters.
And 5: the MCU reads the static current, carries out comparison and judgment, readjusts the pre-discharge gate voltage parameter if the static current is not in the set range, and enters the step 2; if the quiescent current is in the set range, entering step 6;
step 6: storing the current pre-discharge grid voltage parameter, wherein the value is the final determined pre-discharge grid voltage, and writing the pre-discharge grid voltage parameter into an EEPROM for storage;
and 7: the MCU initializes the final grid voltage of the power amplifier, and the grid voltage value is a recommended value of a chip technical manual;
and 8: the MCU switches on the first switch circuit and the second switch circuit to bias the pre-amplifier stage and the final stage simultaneously;
and step 9: the high-precision resistor is matched with the current monitoring chip to monitor the power amplifier quiescent current, and the current is converted into an analog voltage value and then fed back to the MCU for judgment. The current is the sum of the quiescent currents of the two stages of power amplifiers, and the total current can reflect the quiescent current of the final stage due to the stabilized quiescent current of the pre-amplifier stage.
Step 10: the MCU turns off the first switch circuit and the second switch circuit.
Step 11: the MCU reads the static current, carries out comparison and judgment, readjusts the grid voltage parameter of the final stage if the static current is not in the set range, and enters step 8; if the quiescent current is in the set range, entering step 12;
step 12: storing the current final grid voltage parameter, wherein the value is the final determined final grid voltage;
step 13: writing the final-stage grid voltage parameter into the EEPROM for storage;
and step 15, reading the gate voltage parameters of the pre-amplifier stage and the final stage in the EEPROM by a computer, storing the test record and ending the process.
The embodiment of the utility model provides a software and hardware can make automatic test mould with mechanical structure, also can directly integrate to power amplifier circuit PCB on. This novel utility model low cost overall, the design is simple, and convenient operation goes up the electricity and can automatically regulated grid voltage, satisfies statically.
What has been described above is merely a preferred embodiment of the invention. It should be noted that the present invention is not limited to the form described herein, and those skilled in the art can make a number of modifications and improvements without departing from the spirit and scope of the present invention, for example, the present invention can control the power amplifier grid voltage three or more, the power amplifier enable control can be changed to external circuit control, etc., and these modifications and changes should be considered as belonging to the protection scope of the present invention. The utility model is subsidized by the national key research and development plan, and has the project number of 2017YFC 0821903.
Claims (3)
1. A grid voltage automatic generation device used in power amplifier automatic test is characterized by comprising a high-precision resistor, a current monitoring chip, a precision analog microprocessor chip MCU, an EEPROM chip, a first switch circuit, a second switch circuit, a power supply, a computer peripheral device and a plurality of power amplifiers; the power amplifier comprises a driving stage, a pre-amplifier stage and a final stage;
the power supply is respectively connected with the preventive stage and the final stage of the power amplifier and is used for supplying power to the pre-amplifier stage and the final stage;
the high-precision resistor is connected with the current monitoring chip in parallel and is connected in series with the power supply and the power supply circuits of the prevention stage and the final stage; the device is used for monitoring the quiescent current of a prevention stage and a final stage in a matched manner, converting the quiescent current into an analog voltage value and feeding the analog voltage value back to the MCU;
the precision analog microprocessor chip MCU is respectively connected with the EEPROM chip, the current monitoring chip, the first switch circuit and the second switch circuit, the first switch circuit is connected with the preventive stage, and the second switch circuit is connected with the final stage; the precise analog microprocessor chip MCU is used for setting an initial value of the gate voltage of the preventive stage, biasing the preventive stage through a first switch circuit, and judging the quiescent current according to the analog voltage value transmitted by the current monitoring chip to adjust the gate voltage of the preventive stage; the current monitoring chip is also used for setting a final-stage grid voltage initial value after the setting of the preventive-stage grid voltage is finished, biasing the preventive stage and the final stage through the first switch circuit and the second switch circuit respectively, and judging the quiescent current according to the total analog voltage value transmitted by the current monitoring chip to adjust the final-stage grid voltage; writing the pre-amplifier stage grid voltage parameter and the final stage grid voltage parameter into an EEPROM chip;
the computer peripheral equipment is connected with the precision analog microprocessor chip MCU; the device is used for reading pre-amplifier stage grid voltage parameters and final stage grid voltage parameters stored in the MCU of the precision analog microprocessor chip and storing test records.
2. The device of claim 1, wherein the device for automatically generating the gate voltage in the power amplifier automation test comprises: the first switch circuit and the second switch circuit are analog switches or triodes to build switches.
3. The device of claim 1, wherein the device for automatically generating the gate voltage in the power amplifier automation test comprises: the precision analog microprocessor chip MCU is connected with the current monitoring chip through an internal ADC interface to prejudge the input analog voltage value; two paths of DACs are respectively connected with a prevention stage and a final stage, and accurate grid voltage values are provided for the prevention stage and the final stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921899977.6U CN211554226U (en) | 2019-11-06 | 2019-11-06 | Automatic grid voltage generation device used in power amplifier automatic test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921899977.6U CN211554226U (en) | 2019-11-06 | 2019-11-06 | Automatic grid voltage generation device used in power amplifier automatic test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211554226U true CN211554226U (en) | 2020-09-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921899977.6U Active CN211554226U (en) | 2019-11-06 | 2019-11-06 | Automatic grid voltage generation device used in power amplifier automatic test |
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| Country | Link |
|---|---|
| CN (1) | CN211554226U (en) |
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2019
- 2019-11-06 CN CN201921899977.6U patent/CN211554226U/en active Active
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Inventor after: Mi Dawei Inventor after: Si Lei Inventor after: Wang Wei Inventor after: Li Wansong Inventor after: Xin Li Inventor after: Fan Xiaoxing Inventor after: Du Yihao Inventor after: Li Lei Inventor after: Kang Zhijie Inventor after: Sun Jingwei Inventor after: Peng Leilei Inventor after: Feng Changle Inventor before: Mi Dawei Inventor before: Si Lei Inventor before: Wang Wei Inventor before: Li Wansong Inventor before: Fan Xiaoxing Inventor before: Du Yihao Inventor before: Li Lei Inventor before: Kang Zhijie Inventor before: Xin Li Inventor before: Sun Jingwei Inventor before: Peng Leilei Inventor before: Feng Changle |