CN211531424U - Circuit board with side wall circuit - Google Patents
Circuit board with side wall circuit Download PDFInfo
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- CN211531424U CN211531424U CN202020098205.9U CN202020098205U CN211531424U CN 211531424 U CN211531424 U CN 211531424U CN 202020098205 U CN202020098205 U CN 202020098205U CN 211531424 U CN211531424 U CN 211531424U
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Abstract
The utility model discloses a circuit board with lateral wall circuit, including insulating substrate, first circuit layer and second circuit layer, insulating substrate includes the first surface and deviates from the second surface of first surface, and insulating substrate sets up the through-hole that runs through first surface and second surface, and the lateral wall of through-hole is equipped with the third circuit layer of connecting first circuit layer and second circuit layer, and the third circuit layer includes the first sub-circuit that a plurality of intervals set up. The utility model discloses a circuit board with lateral wall circuit has not only promoted the circuit layout density of circuit board greatly through having been equipped with third circuit layer at the through-hole lateral wall fully utilizing the space that whole circuit board can be wired, greatly reduced its flow cost moreover and keep high yield, moreover, through the lateral wall wiring at the through-hole, can reduce the number of piles of product, satisfy the frivolous requirement of product.
Description
Technical Field
The utility model relates to a circuit board field especially relates to a circuit board with lateral wall circuit.
Background
With the rapid development of consumer electronics, the intelligent degree of electronic products is greatly enriched, and high intelligence further requires the improvement of electronic products in function integration, short, small and light size. As a packaging carrier of electronic products, the circuit board also has to face the challenges of more functions and smaller space. The circuit board can realize smaller space by reducing L/S and more interlayer interconnection. The traditional interlayer interconnection mode is realized by adopting metallized through holes, blind holes and micro through holes, but the layout density of circuits in the layers can be greatly reduced due to the existence of the through holes, and more functions are realized, so that more layers of layers, namely the thickness of a product plate, are required, and the requirement of lightening and thinning the product is deviated.
SUMMERY OF THE UTILITY MODEL
In order to overcome the not enough of prior art, the utility model discloses a circuit board with lateral wall circuit for solve present because the existence greatly reduced in situ circuit's of conducting hole overall arrangement density, the product number of piles is many moreover, requires the problem that deviates from mutually with product "frivolousization".
The purpose of the utility model is realized by adopting the following technical scheme:
the utility model provides a circuit board with lateral wall circuit, includes insulating substrate, first circuit layer and second circuit layer, insulating substrate includes the first surface and deviates from the second surface of first surface, insulating substrate sets up and runs through the first surface with the through-hole on second surface, the lateral wall of through-hole is equipped with the connection first circuit layer with the third circuit layer on second circuit layer, the third circuit layer includes the first sub-circuit of a plurality of intervals settings.
As an improvement mode, the circuit board with the lateral wall circuit further comprises an insulating layer, a fourth circuit layer, a fifth circuit layer and a sixth circuit layer, wherein the insulating layer covers the first circuit layer and is far away from one side of the insulating substrate, the second circuit layer and the third circuit layer are far away from one side of the insulating substrate, the fourth circuit layer is arranged on one side of the insulating substrate, the insulating layer is far away from one side of the first circuit layer, the fifth circuit layer is arranged on one side of the second circuit layer, the sixth circuit layer is arranged on one side of the third circuit layer, the insulating layer is far away from one side of the third circuit layer, the sixth circuit layer is connected with the fifth circuit layer, and the sixth circuit layer comprises a plurality of second sub-circuits arranged at intervals.
As an improvement mode, the circuit board with the side wall circuit further comprises a first ink layer, the first ink layer covers one side of the fourth circuit layer, which is far away from the insulating layer, and one side of the fifth circuit layer, which is far away from the insulating layer, and the first ink layer is provided with a window to expose the bonding pad and the circuit finger.
As an improvement mode, the circuit board with the side-wall circuit further comprises a second ink layer, and the second ink layer covers one side, far away from the insulating layer, of the sixth circuit layer.
As an improvement mode, a metal protection layer is arranged on one side, away from the insulating layer, of the pad and one side, away from the insulating layer, of the circuit finger.
As an improvement, the metal protection layer is a nickel layer, or a nickel-silver layer, or a nickel-gold layer, or a nickel-silver-gold layer, or a nickel-palladium-gold layer, or an organic solderability preservative film.
In an improvement, the insulating substrate is a BT board, an epoxy board, a silicone board, a polyphthalamide board, or an ABF board.
As an improvement mode, the thickness of the third circuit layer is D1, D1 is larger than or equal to 12um, the thickness of the sixth circuit layer is D2, and D2 is larger than or equal to 12 um.
As an improvement, the first circuit layer, the second circuit layer, the third circuit layer, the fourth circuit layer, the fifth circuit layer and the sixth circuit layer are all copper layers.
As an improvement, the insulating layer is a prepreg layer.
Compared with the prior art, the beneficial effects of the utility model reside in that:
the utility model provides a circuit board with lateral wall circuit is through being equipped with third circuit layer at the through-hole lateral wall, the space that whole circuit board can lay wire has been fully utilized, the circuit layout density of circuit board can not only have promoted greatly, and greatly reduced its flow cost and keep high yield, at the antenna, the inductance, the transformer, relevant fields such as high frequency product have cost and technical advantage that have been unique, and in addition, through the lateral wall wiring at the through-hole, the number of piles of product can be reduced, satisfy the frivolousization requirement of product.
Drawings
Fig. 1 is a schematic partial cross-sectional view of a circuit board with a side wall circuit according to an embodiment of the present invention;
fig. 2 is a schematic partial cross-sectional view of a circuit board with a side wall circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that the embodiments or technical features described below can be arbitrarily combined to form a new embodiment without conflict.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
It will also be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, a first embodiment of the present invention discloses a circuit board 10 with a sidewall circuit, including an insulating substrate 11, a first circuit layer 12 and a second circuit layer 13, the insulating substrate 11 includes a first surface 111 and a second surface 112 deviating from the first surface 111, the insulating substrate 11 is provided with a through hole 113 penetrating through the first surface 111 and the second surface 112, a sidewall of the through hole 113 is provided with a third circuit layer 14 connecting the first circuit layer 12 and the second circuit layer 13, and the third circuit layer 14 includes a plurality of first sub-circuits 141 arranged at intervals.
The circuit board 10 with the side wall circuit disclosed in the embodiment sufficiently utilizes the space where the whole circuit board can be wired by arranging the third circuit layer 14 on the side wall of the through hole 113, thereby not only greatly improving the circuit layout density of the circuit board, but also greatly reducing the flow cost and keeping high yield, and having unique cost and technical advantages in the related fields of antennas, inductors, transformers, high-frequency products and the like. In addition, the number of layers of the product can be reduced by wiring on the side wall of the through hole 113, and the requirement of lightening and thinning of the product is met.
It should be noted that the third circuit layer 14 may connect a part of the first circuit layer 12 and a part of the second circuit layer 13, or may connect all of the first circuit layers 12 and all of the second circuit layers 13, and the details may be determined according to actual design requirements.
As a modification of this embodiment, the insulating substrate 11 is a bt (bimoleimide) board, an epoxy board, a silicone board, a polyphthalamide board, or an ABF (Ajinomoto Build-up film) board.
As a modification of the present embodiment, the thickness of the third circuit layer 14 is D1, and D1 is greater than or equal to 12 um. By setting the thickness D1 of the third wiring layer 14 to be equal to or greater than 12um, the reliability of the third wiring layer 14 formed after etching can be improved.
Example two:
referring to fig. 1-2, a second embodiment of the present invention discloses a circuit board 100 with a side wall circuit, the circuit board 200 with a side wall circuit disclosed in the first embodiment includes an insulating layer 20, a fourth circuit layer 30, a fifth circuit layer 40, a sixth circuit layer 50 and the circuit board 10 with a side wall circuit described in the first embodiment, the insulating layer 20 covers one side of the first circuit layer 12 away from the insulating substrate 11, one side of the second circuit layer 13 away from the insulating substrate 11, and one side of the third circuit layer 13 away from the insulating substrate 11, the fourth circuit layer 30 is disposed on one side of the insulating layer 20 away from the first circuit layer 12, the fifth circuit layer 40 is disposed on one side of the insulating layer 20 away from the second circuit layer 13, the sixth circuit layer 50 is disposed on one side of the insulating layer 20 away from the third circuit layer 13, the sixth circuit layer 50 connects the fourth circuit layer 30 and the fifth circuit layer 40, the sixth wiring layer 50 includes a plurality of second sub-wirings 51 arranged at intervals.
With this design, the layout density of the wiring board is further improved by providing the sixth wiring layer 50. It should be noted that, in the subsequent process, more layers of circuits can be arranged at the through hole according to the actual design requirement.
It should be noted that the sixth circuit layer 50 may be a part of the fourth circuit layer 30 and a part of the fifth circuit layer 40, or may be a part of the fourth circuit layer 30 and a part of the fifth circuit layer 50, and may be specifically determined according to actual design requirements.
As an improvement of this embodiment, the circuit board 100 with a sidewall circuit further includes a first ink layer, the first ink layer covers a side of the fourth circuit layer 30 away from the insulating layer 20, a side of the fifth circuit layer 40 away from the insulating layer 20, and a side of the sixth circuit layer 50 away from the insulating layer 20, and the first ink layer is provided with a window to expose the pad and the circuit finger.
As an improvement of this embodiment, the circuit board 100 with a sidewall circuit further includes a second ink layer, and the second ink layer covers a side of the sixth circuit layer 50 away from the insulating layer 20. It should be noted that the second ink layer may not be disposed on the side of the sixth circuit layer 50 away from the insulating layer 20, and the sixth circuit layer may be determined according to actual design requirements.
As an improvement mode of this embodiment, a side of the pad away from the insulating layer and a side of the circuit finger away from the insulating layer are provided with a metal protection layer. The pad and the circuit finger can be oxidized before welding by arranging the metal protective layer.
As a modification of this embodiment, the metal protection layer is a nickel layer, a nickel-silver layer, a nickel-gold layer, a nickel-silver-gold layer, a nickel-palladium-gold layer, or an Organic Solderability Preservative (OSP).
As a modification of this embodiment, the thickness of the sixth circuit layer 50 is D2, and D2 is greater than or equal to 12 um. Similarly, the thickness D2 of the sixth circuit layer 50 is set to be greater than or equal to 12um, so that the reliability of the sixth circuit layer 50 formed after etching can be improved.
As a modification of the present embodiment, the first circuit layer 12, the second circuit layer 13, the third circuit layer 14, the fourth circuit layer 30, the fifth circuit layer 40 and the sixth circuit layer 50 are all copper layers.
As a modification of this embodiment, the insulating layer 20 is a prepreg layer.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention cannot be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are all within the protection scope of the present invention.
Claims (10)
1. The utility model provides a circuit board with lateral wall circuit, its characterized in that includes insulating substrate, first circuit layer and second circuit layer, insulating substrate includes the first surface and deviates from the second surface of first surface, insulating substrate offers and runs through the first surface with the through-hole on second surface, the lateral wall of through-hole is equipped with the connection first circuit layer with the third circuit layer on second circuit layer, the third circuit layer includes the first sub-circuit that a plurality of intervals set up.
2. The wiring board with sidewall wiring of claim 1, further comprising an insulating layer, a fourth wiring layer, a fifth wiring layer, and a sixth wiring layer, the insulating layer covers one side of the first circuit layer far away from the insulating substrate, one side of the second circuit layer far away from the insulating substrate and one side of the third circuit layer far away from the insulating substrate, the fourth circuit layer is arranged on one side of the insulating layer far away from the first circuit layer, the fifth circuit layer is arranged on one side of the insulating layer far away from the second circuit layer, the sixth circuit layer is arranged on one side, far away from the third circuit layer, of the insulating layer and connected with the fourth circuit layer and the fifth circuit layer, and the sixth circuit layer comprises a plurality of second sub-circuits arranged at intervals.
3. The circuit board with side wall circuits according to claim 2, further comprising a first ink layer covering a side of the fourth circuit layer away from the insulating layer and a side of the fifth circuit layer away from the insulating layer, wherein the first ink layer is provided with a window to expose the pad and the circuit finger.
4. The circuit board with the side-wall circuit according to claim 3, wherein the circuit board with the side-wall circuit further comprises a second ink layer covering a side of the sixth circuit layer away from the insulating layer.
5. The wiring board with sidewall circuits as claimed in claim 3, wherein a side of said pad away from said insulating layer and a side of said circuit finger away from said insulating layer are provided with a metal protective layer.
6. The circuit board with the side wall circuit according to claim 5, wherein the metal protection layer is a nickel layer, a nickel-silver layer, a nickel-gold layer, a nickel-silver-gold layer, a nickel-palladium-gold layer, or an organic solder mask.
7. The wiring board with the side wall wiring according to claim 1, wherein the insulating substrate is a BT board, or an epoxy board, or a silicone board, or a polyphthalamide board, or an ABF board.
8. The circuit board with the side-wall circuit of claim 2, wherein the thickness of the third circuit layer is D1, D1 is 12um or more, and the thickness of the sixth circuit layer is D2, D2 is 12um or more.
9. The wiring board with sidewall wiring of claim 2, wherein the first, second, third, fourth, fifth and sixth wiring layers are all copper layers.
10. The wiring board with sidewall wiring of claim 2, wherein the insulating layer is a prepreg layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020098205.9U CN211531424U (en) | 2020-01-16 | 2020-01-16 | Circuit board with side wall circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020098205.9U CN211531424U (en) | 2020-01-16 | 2020-01-16 | Circuit board with side wall circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211531424U true CN211531424U (en) | 2020-09-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020098205.9U Active CN211531424U (en) | 2020-01-16 | 2020-01-16 | Circuit board with side wall circuit |
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| CN (1) | CN211531424U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116634652A (en) * | 2023-05-06 | 2023-08-22 | 深南电路股份有限公司 | Printed circuit board conducted through groove wall and preparation method thereof |
-
2020
- 2020-01-16 CN CN202020098205.9U patent/CN211531424U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116634652A (en) * | 2023-05-06 | 2023-08-22 | 深南电路股份有限公司 | Printed circuit board conducted through groove wall and preparation method thereof |
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