CN211530839U - Anti-reflux dual-power switching circuit - Google Patents
Anti-reflux dual-power switching circuit Download PDFInfo
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- CN211530839U CN211530839U CN201922436847.5U CN201922436847U CN211530839U CN 211530839 U CN211530839 U CN 211530839U CN 201922436847 U CN201922436847 U CN 201922436847U CN 211530839 U CN211530839 U CN 211530839U
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Abstract
The utility model discloses a prevent dual supply switching circuit against current, including first control signal circuit, second control signal circuit, first supply circuit and second supply circuit, first control signal point and second supply circuit correspond with No. two batteries, and second control signal circuit and first supply circuit correspond with a battery, first control signal circuit and first supply circuit intercommunication, and second control signal circuit then communicates with second supply circuit. The utility model discloses a mutual control and intercommunication between power supply circuit and the signal control circuit based on the P-MOS pipe that sets up dorsad can effectively realize that the power supply mode between the dual supply freely switches and problem against the current each other.
Description
Technical Field
The utility model relates to a prevent dual supply switching circuit against current, concretely relates to prevent dual supply switching circuit against current belongs to circuit technical field.
Background
In a multi-battery power supply system, a backflow problem often exists, and at present, a backflow prevention mode is usually adopted to solve the backflow problem by adopting a diode. Fig. 1 is a schematic diagram of a conventional backflow prevention circuit. As shown in fig. 1: the terminal VIN1 is connected to the terminal VOUT through the diodes D1 and VIN2 respectively through the diode D2.
The circuit can solve the problem of reverse flow of the dual-power switching circuit, but the following problems exist in the high-power occasion, and 1, the required diode volume is large; 2. the inherent characteristics of the diode have large forward voltage drop; 3. in a large-current situation, a relatively large amount of power is consumed due to the existence of the internal resistance of the diode, and in addition, the diode generates heat seriously, so that the stability of a system is easily influenced; 4. the diode models with large current (more than 20A) can be selected less.
Disclosure of Invention
For solving the not enough of prior art, the utility model aims to provide a small, efficient, effectual dual power supply switching circuit prevents against current.
In order to achieve the above object, the utility model adopts the following technical scheme:
the utility model provides an anti-reflux dual power supply switching circuit, includes first control signal circuit, second control signal circuit, first power supply circuit and second power supply circuit, first control signal point and second power supply circuit correspond with No. two batteries, and second control signal circuit and first power supply circuit correspond with No. one battery, first control signal circuit and first power supply circuit intercommunication, and second control signal circuit then communicates with second power supply circuit.
The first control signal circuit comprises a resistor R19 and a resistor R20 which are connected in series, the other end of the resistor R19 is connected with a VIN2 end, the VIN2 end corresponds to a second battery, the resistor R19 and the resistor R20 are connected with the + input end of a second voltage comparator, the-input end of the second voltage comparator is connected with a first reference voltage, the output end of the second voltage comparator is communicated with the D end of an N-MOS (metal oxide semiconductor) transistor, the output end of the N-MOS transistor is communicated with a first power supply circuit through a control signal, a resistor R26 is further connected to a circuit connected between the second voltage comparator and the N-MOS transistor, and the resistor R26 is connected with a VCC end.
The second control signal circuit comprises a resistor R3 and a resistor R18 which are connected in series, the other end of the resistor R3 is connected with a VIN1 end, the VIN1 end corresponds to a battery, the resistor R3 and the resistor R18 are connected with the + input end of the first voltage comparator, the-input end of the first voltage comparator is connected with a second reference voltage, the output end of the first voltage comparator is communicated with the D end of an N-MOS tube, the output end of the N-MOS tube is communicated with the second power supply circuit through a control signal, a resistor R25 is further connected to a circuit connected between the first voltage comparator and the N-MOS tube, and the resistor R25 is connected with a VCC end.
Further, the first power supply circuit comprises a P-MOS transistor Q1 and a P-MOS transistor Q2 which are arranged symmetrically in a back-to-back manner on a circuit from the VIN1 end to the VOUT end, a Q1 control circuit for controlling the on-off of the P-MOS transistor Q1, and a Q2 control circuit for controlling the on-off of the P-MOS transistor Q2.
The Q1 control circuit comprises a resistor R4 connected with the pin 1 of the P-MOS transistor Q1; a resistor R6 connected in series with the resistor R4; an N-MOS tube Q4 connected with the resistor R6; a capacitor C2 and a resistor R8 which have the same input end and the same grounding end as the N-MOS transistor Q4 and are arranged in parallel; a voltage stabilizing diode D1, a resistor R1 and a capacitor C1 which are sequentially arranged in parallel, wherein one side of the voltage stabilizing diode D1 and the pin 3 of the P-MOS transistor Q1 are connected with the VIN1 end, the other side of the voltage stabilizing diode D1 is connected with a circuit between the resistor R4 and the resistor R6; a resistor R7 and a resistor R5 are also connected in series between the input end of the N-MOS transistor Q4 and the VIN1, and a circuit between the resistor R7 and the resistor R5 is connected with a first control signal.
The Q2 control circuit comprises a resistor R21 connected with pin 2 of a P-MOS transistor Q1; a resistor R22 connected in series with the resistor R21; a resistor R17 connected with pin 1 of the P-MOS transistor Q2; an N-MOS tube Q3 which is respectively communicated with circuits among the resistor R17, the resistor R12 and the resistor R22; one side of the resistor is connected with the 3 feet of the P-MOS transistor Q2 at the VOUT end, and the other side of the resistor is connected with a resistor R2 of a circuit between a resistor R17 and an N-MOS transistor Q3.
Furthermore, the second power supply circuit comprises a P-MOS tube Q5 and a P-MOS tube Q6 which are symmetrically arranged in a back-to-back mode on the circuit from the VIN2 end to the VOUT end, a Q10 control circuit for controlling the on-off of the P-MOS tube Q5 and a Q7 control circuit for controlling the on-off of the P-MOS tube Q6.
The Q5 control circuit comprises a resistor R12 connected with the pin 1 of the P-MOS transistor Q5; a resistor R14 connected in series with the resistor R12; an N-MOS tube Q10 connected with the resistor R14; a capacitor C4 and a resistor R16 which have the same input end and the same grounding end as the N-MOS transistor Q10 and are arranged in parallel; a voltage stabilizing diode D2, a resistor R9 and a capacitor C3 which are sequentially arranged in parallel, wherein one side of the voltage stabilizing diode D2 and the pin 3 of the P-MOS transistor Q5 are connected with the VIN2 end, the other side of the voltage stabilizing diode D2 is connected with a circuit between the resistor R12 and the resistor R14; a resistor R15 and a resistor R13 are also connected in series between the input end of the N-MOS transistor Q10 and the VIN2, and a circuit between the resistor R15 and the resistor R13 is connected with a second control signal.
The Q6 control circuit comprises a resistor R23 connected with the 2 pin of a P-MOS transistor Q6; a resistor R24 connected in series with the resistor R23; a resistor R11 connected with pin 1 of the P-MOS transistor Q6; an N-MOS tube Q7 which is respectively communicated with circuits among the resistor R11, the resistor R23 and the resistor R24; one side of the resistor is connected with the 3 feet of the P-MOS transistor Q6 at the VOUT end, and the other side of the resistor is connected with a resistor R10 of a circuit between a resistor R11 and an N-MOS transistor Q7.
The utility model discloses the beneficial effect who reaches: the utility model discloses a mutual control and intercommunication between power supply circuit and the signal control circuit based on the P-MOS pipe that sets up dorsad can effectively realize that the power supply mode between the dual supply freely switches and problem against the current each other.
Drawings
FIG. 1 is a schematic diagram of a conventional anti-reflux circuit;
FIG. 2 is a schematic diagram of the overall circuit structure of the present invention;
fig. 3 is a schematic structural diagram of a first control signal circuit according to the present invention;
fig. 4 is a schematic structural diagram of a second control signal circuit according to the present invention;
fig. 5 is a schematic structural diagram of a first power supply circuit according to the present invention;
fig. 6 is a schematic structural diagram of a second power supply circuit according to the present invention.
The main reference numerals in the figures mean:
1. first control signal circuit 2 and second control signal circuit
3. A first power supply circuit 4 and a second power supply circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
2 is the utility model discloses the overall circuit structure schematic diagram.
As shown in fig. 2: anti-reflux dual power supply switching circuit, including first control signal circuit 1, second control signal circuit 2, first power supply circuit 3 and second power supply circuit 4, wherein, first control signal point 1 and second power supply circuit 4 correspond with No. two batteries, and second control signal circuit 2 and first power supply circuit 3 correspond with No. one battery, first control signal circuit 1 and first power supply circuit 3 intercommunication, and second control signal circuit 2 then communicates with second power supply circuit 4.
Fig. 3 is a schematic structural diagram of the first control signal circuit according to the present invention.
As shown in fig. 3: the first control signal circuit 1 comprises a resistor R19 and a resistor R20 which are connected in series, the other end of the resistor R19 is connected with a VIN2 end, the VIN2 end corresponds to a second battery, the resistor R19 and the resistor R20 are connected with the + input end of a second voltage comparator, the-input end of the second voltage comparator is connected with a first reference voltage, the output end of the second voltage comparator is communicated with the D end of an N-MOS (metal oxide semiconductor) transistor, the output end of the N-MOS transistor is communicated with a first power supply circuit through a control signal, a resistor R26 is further connected to a circuit connected between the second voltage comparator and the N-MOS transistor, and the resistor R26 is connected with a VCC end.
Fig. 4 is a schematic structural diagram of a second control signal circuit according to the present invention.
As shown in fig. 4: the second control signal circuit 2 comprises a resistor R3 and a resistor R18 which are connected in series, the other end of the resistor R3 is connected with a VIN1 end, the VIN1 end corresponds to a battery, the resistor R3 and the resistor R18 are connected with the + input end of a first voltage comparator, the-input end of the first voltage comparator is connected with a second reference voltage, the output end of the first voltage comparator is communicated with the D end of an N-MOS (metal oxide semiconductor) transistor, the output end of the N-MOS transistor is communicated with a second power supply circuit through a control signal, a resistor R25 is further connected to a circuit connected between the first voltage comparator and the N-MOS transistor, and the resistor R25 is connected with a VCC end.
Fig. 5 is a schematic structural diagram of the first power supply circuit of the present invention.
As shown in fig. 5: the first power supply circuit 3 comprises a P-MOS transistor Q1 and a P-MOS transistor Q2 which are symmetrically arranged in a back-to-back mode on a circuit from a VIN1 end to a VOUT end, a Q1 control circuit for controlling the on-off of the P-MOS transistor Q1 and a Q2 control circuit for controlling the on-off of the P-MOS transistor Q2. The Q1 control circuit comprises a resistor R4 connected with the pin 1 of the P-MOS transistor Q1; a resistor R6 connected in series with the resistor R4; an N-MOS tube Q4 connected with the resistor R6; a capacitor C2 and a resistor R8 which have the same input end and the same grounding end as the N-MOS transistor Q4 and are arranged in parallel; a voltage stabilizing diode D1, a resistor R1 and a capacitor C1 which are sequentially arranged in parallel, wherein one side of the voltage stabilizing diode D1 and the pin 3 of the P-MOS transistor Q1 are connected with the VIN1 end, the other side of the voltage stabilizing diode D1 is connected with a circuit between the resistor R4 and the resistor R6; a resistor R7 and a resistor R5 are also connected in series between the input end of the N-MOS transistor Q4 and the VIN1, and a circuit between the resistor R7 and the resistor R5 is connected with a first control signal. The Q2 control circuit comprises a resistor R21 connected with the 2 pin of the P-MOS transistor Q1; a resistor R22 connected in series with the resistor R21; a resistor R17 connected with pin 1 of the P-MOS transistor Q2; an N-MOS tube Q3 which is respectively communicated with circuits among the resistor R17, the resistor R12 and the resistor R22; one side of the resistor is connected with the 3 feet of the P-MOS transistor Q2 at the VOUT end, and the other side of the resistor is connected with a resistor R2 of a circuit between a resistor R17 and an N-MOS transistor Q3.
Fig. 6 is a schematic structural diagram of a second power supply circuit according to the present invention.
As shown in fig. 6: the second power supply circuit 4 comprises a P-MOS transistor Q5 and a P-MOS transistor Q6 which are symmetrically arranged in a back-to-back mode on a circuit from a VIN2 end to a VOUT end, a Q10 control circuit for controlling the on-off of the P-MOS transistor Q5 and a Q7 control circuit for controlling the on-off of the P-MOS transistor Q6. The Q5 control circuit comprises a resistor R12 connected with the pin 1 of the P-MOS transistor Q5; a resistor R14 connected in series with the resistor R12; an N-MOS tube Q10 connected with the resistor R14; a capacitor C4 and a resistor R16 which have the same input end and the same grounding end as the N-MOS transistor Q10 and are arranged in parallel; a voltage stabilizing diode D2, a resistor R9 and a capacitor C3 which are sequentially arranged in parallel, wherein one side of the voltage stabilizing diode D2 and the pin 3 of the P-MOS transistor Q5 are connected with the VIN2 end, the other side of the voltage stabilizing diode D2 is connected with a circuit between the resistor R12 and the resistor R14; a resistor R15 and a resistor R13 are also connected in series between the input end of the N-MOS transistor Q10 and the VIN2, and a circuit between the resistor R15 and the resistor R13 is connected with a second control signal. The Q6 control circuit comprises a resistor R23 connected with the 2 pin of a P-MOS transistor Q6; a resistor R24 connected in series with the resistor R23; a resistor R11 connected with pin 1 of the P-MOS transistor Q6; an N-MOS tube Q7 which is respectively communicated with circuits among the resistor R11, the resistor R23 and the resistor R24; one side of the resistor is connected with the 3 feet of the P-MOS transistor Q6 at the VOUT end, and the other side of the resistor is connected with a resistor R10 of a circuit between a resistor R11 and an N-MOS transistor Q7.
When both the VIN1 and the VIN2 can maintain the system operating, the "control signal 1" generated by the first control signal circuit 1 will control the P-MOS transistor Q1 to turn off, and the VIN1 no longer supplies power to the subsequent system.
When the VIN1 voltage can meet the system operation requirement, but the VIN2 voltage is too low to meet the system operation requirement; at the moment, the N-MOS transistor Q8 is turned off, and the N-MOS transistor Q9 is turned on; the control signal 1 controls the P-MOS tube Q1 to be conducted, and power is supplied to a subsequent load to ensure the normal operation of the system; meanwhile, the control signal 2 controls the P-MOS transistor Q5 to be turned off, so that VIN2 cannot flow through the P-MOS transistor Q5, and at the moment, the P-MOS transistor Q6 is turned off because the differential pressure of the gs end of the P-MOS transistor Q6 is 0, so that VOUT cannot supply power to the second battery through the P-MOS transistor Q6 and the P-MOS transistor Q5, and the problem of backflow of charging VIN2 at the VIN1 is solved.
When the VIN2 voltage can meet the system operation requirement, but the VIN1 voltage is too low to meet the system operation requirement; at the moment, the N-MOS transistor Q8 is switched on, and the N-MOS transistor Q9 is switched off; the 'control signal 2' generated by the second signal control circuit 2 controls the P-MOS transistor Q5 to be conducted, so as to supply power to the subsequent load and ensure the normal operation of the system; meanwhile, the control signal 1 controls the P-MOS transistor Q1 to be turned off, so that VIN1 cannot flow through the P-MOS transistor Q1, and at the moment, the P-MOS transistor Q2 is turned off because the differential pressure of the gs end of the P-MOS transistor Q2 is 0, so that VOUT cannot supply power to a first battery through the P-MOS transistor Q2 and the P-MOS transistor Q1, and the problem of backflow of charging VIN1 at the VIN2 is solved.
As mentioned above, although the present invention has been shown and described with reference to certain preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. The utility model provides an anti-reflux dual supply switching circuit, its characterized in that includes first control signal circuit, second control signal circuit, first power supply circuit and second power supply circuit, first control signal point and second power supply circuit correspond with No. two batteries, and second control signal circuit and first power supply circuit correspond with No. one battery, first control signal circuit and first power supply circuit intercommunication, and second control signal circuit then communicates with second power supply circuit.
2. The anti-reflux dual-power switching circuit as claimed in claim 1, wherein the first control signal circuit comprises a resistor R19 and a resistor R20 connected in series, the other end of the resistor R19 is connected to a terminal VIN2, the terminal VIN2 corresponds to a second battery, a resistor R19 and a resistor R20 are connected to a + input terminal of a second voltage comparator, a-input terminal of the second voltage comparator is connected to the first reference voltage, an output terminal of the second voltage comparator is connected to a D terminal of an N-MOS transistor, an output terminal of the N-MOS transistor is connected to the first power supply circuit through a control signal, a resistor R26 is further connected to a circuit connected between the second voltage comparator and the N-MOS transistor, and the resistor R26 is connected to a VCC terminal.
3. The anti-reflux dual-power switching circuit as claimed in claim 1, wherein the second control signal circuit comprises a resistor R3 and a resistor R18 connected in series, the other end of the resistor R3 is connected to a terminal VIN1, the terminal VIN1 corresponds to a battery number one, a resistor R3 and a resistor R18 are connected to a + input terminal of a first voltage comparator, a-input terminal of the first voltage comparator is connected to the second reference voltage, an output terminal of the first voltage comparator is connected to a D terminal of an N-MOS transistor, an output terminal of the N-MOS transistor is connected to the second power supply circuit through a control signal, a resistor R25 is further connected to a circuit connected between the first voltage comparator and the N-MOS transistor, and the resistor R25 is connected to a VCC terminal.
4. The anti-reflux dual-power-supply switching circuit as claimed in claim 1, wherein the first power supply circuit comprises a P-MOS transistor Q1 and a P-MOS transistor Q2 which are symmetrically arranged in a back-to-back manner in a circuit from a VIN1 end to a VOUT end, a Q1 control circuit for controlling the on-off of the P-MOS transistor Q1, and a Q2 control circuit for controlling the on-off of the P-MOS transistor Q2.
5. The anti-reflux dual-power switching circuit as claimed in claim 4, wherein the Q1 control circuit comprises a resistor R4 connected to pin 1 of a P-MOS transistor Q1; a resistor R6 connected in series with the resistor R4; an N-MOS tube Q4 connected with the resistor R6; a capacitor C2 and a resistor R8 which have the same input end and the same grounding end as the N-MOS transistor Q4 and are arranged in parallel; a voltage stabilizing diode D1, a resistor R1 and a capacitor C1 which are sequentially arranged in parallel, wherein one side of the voltage stabilizing diode D1 and the pin 3 of the P-MOS transistor Q1 are connected with the VIN1 end, the other side of the voltage stabilizing diode D1 is connected with a circuit between the resistor R4 and the resistor R6; a resistor R7 and a resistor R5 are also connected in series between the input end of the N-MOS transistor Q4 and the VIN1, and a circuit between the resistor R7 and the resistor R5 is connected with a first control signal.
6. The anti-reflux dual-power switching circuit as claimed in claim 4, wherein the Q2 control circuit comprises a resistor R21 connected to pin 2 of a P-MOS transistor Q1; a resistor R22 connected in series with the resistor R21; a resistor R17 connected with pin 1 of the P-MOS transistor Q2; an N-MOS tube Q3 which is respectively communicated with circuits among the resistor R17, the resistor R12 and the resistor R22; one side of the resistor is connected with the 3 feet of the P-MOS transistor Q2 at the VOUT end, and the other side of the resistor is connected with a resistor R2 of a circuit between a resistor R17 and an N-MOS transistor Q3.
7. The anti-reflux dual-power-supply switching circuit as claimed in claim 1, wherein the second power supply circuit comprises a P-MOS transistor Q5 and a P-MOS transistor Q6 which are symmetrically arranged in a back-to-back manner in a circuit from a VIN2 end to a VOUT end, a Q10 control circuit for controlling the on-off of the P-MOS transistor Q5, and a Q7 control circuit for controlling the on-off of the P-MOS transistor Q6.
8. The anti-reflux dual-power switching circuit as claimed in claim 7, wherein the Q5 control circuit comprises a resistor R12 connected to pin 1 of a P-MOS transistor Q5; a resistor R14 connected in series with the resistor R12; an N-MOS tube Q10 connected with the resistor R14; a capacitor C4 and a resistor R16 which have the same input end and the same grounding end as the N-MOS transistor Q10 and are arranged in parallel; a voltage stabilizing diode D2, a resistor R9 and a capacitor C3 which are sequentially arranged in parallel, wherein one side of the voltage stabilizing diode D2 and the pin 3 of the P-MOS transistor Q5 are connected with the VIN2 end, the other side of the voltage stabilizing diode D2 is connected with a circuit between the resistor R12 and the resistor R14; a resistor R15 and a resistor R13 are also connected in series between the input end of the N-MOS transistor Q10 and the VIN2, and a circuit between the resistor R15 and the resistor R13 is connected with a second control signal.
9. The anti-reflux dual-power switching circuit as claimed in claim 7, wherein the Q6 control circuit comprises a resistor R23 connected to pin 2 of a P-MOS transistor Q6; a resistor R24 connected in series with the resistor R23; a resistor R11 connected with pin 1 of the P-MOS transistor Q6; an N-MOS tube Q7 which is respectively communicated with circuits among the resistor R11, the resistor R23 and the resistor R24; one side of the resistor is connected with the 3 feet of the P-MOS transistor Q6 at the VOUT end, and the other side of the resistor is connected with a resistor R10 of a circuit between a resistor R11 and an N-MOS transistor Q7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922436847.5U CN211530839U (en) | 2019-12-30 | 2019-12-30 | Anti-reflux dual-power switching circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922436847.5U CN211530839U (en) | 2019-12-30 | 2019-12-30 | Anti-reflux dual-power switching circuit |
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| CN211530839U true CN211530839U (en) | 2020-09-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510810A (en) * | 2020-12-07 | 2021-03-16 | 中国第一汽车股份有限公司 | Automobile and monitoring circuit of power supply system thereof |
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2019
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510810A (en) * | 2020-12-07 | 2021-03-16 | 中国第一汽车股份有限公司 | Automobile and monitoring circuit of power supply system thereof |
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