CN211481579U - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
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- CN211481579U CN211481579U CN201922052935.5U CN201922052935U CN211481579U CN 211481579 U CN211481579 U CN 211481579U CN 201922052935 U CN201922052935 U CN 201922052935U CN 211481579 U CN211481579 U CN 211481579U
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- inlayer
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Abstract
The utility model relates to a radio frequency signal transmission and data communication field provide a printed circuit board. This printed circuit board includes the base plate, the base plate includes top layer, bottom and sets up a plurality of inlayers between top layer and the bottom, it is a plurality of the inlayer certainly the top layer extremely the direction of bottom sets gradually, between the top layer with between the inlayer with between the bottom and adjacent two all be equipped with the insulating layer between the inlayer, at least one via hole has been seted up to the base plate, the via hole have with inlayer one-to-one's inlayer pad, every the size of inlayer pad with correspond the width of printed conductor on the inlayer suits. The utility model discloses simple structure, simple process, the size through making the inlayer pad suits with the width that corresponds the printed conductor on the inlayer, alright improve its radio frequency signal's integrality, reduce the insertion loss.
Description
Technical Field
The utility model relates to a radio frequency signal transmission and data communication field especially relate to a printed circuit board.
Background
A Printed Circuit Board (hereinafter, referred to as PCB) is a support for electronic components, and is used to implement wiring and electrical connection between various electronic components such as an integrated Circuit.
Vias, also known as metallized holes, are one of the basic components of a PCB, and are electrical paths for switching between circuit layers of the PCB, with copper attached to the inner walls thereof, providing conductivity. The through holes are generally divided into three types, namely signal through holes, device through holes and mounting and positioning through holes, wherein the signal through holes are used for connecting printed conductors of different circuit layers, the device through holes are used for connecting pins for inserting devices and the printed conductors of the circuit layers, and the mounting and positioning through holes are used for fixing a PCB. Divide according to the structure, the via hole generally divide into through-hole via hole, blind hole via hole and buried via hole, and wherein, the through-hole via hole directly runs through the PCB, and the blind hole via hole reaches certain layer in the PCB from the surface of PCB, does not run through the PCB, and the buried via hole does not pierce through the PCB top layer, only communicates certain several layers in the PCB.
At present, the widths of the printed wires on different inner layers of the printed circuit board are generally different, and the sizes of the pads of the via holes on different inner layers are the same, that is, the sizes of the pads of the via holes and the widths of the printed wires are probably not matched, which can cause the integrity of the radio frequency signals of the printed circuit board to be reduced and the insertion loss to be increased.
SUMMERY OF THE UTILITY MODEL
The present invention aims at least solving one of the technical problems existing in the prior art or the related art. Therefore, the utility model provides a printed circuit board to improve its radio frequency signal's integrality, reduce the insertion loss.
According to the utility model discloses printed circuit board of first aspect embodiment, which comprises a substrate, the base plate includes top layer, bottom and sets up a plurality of inlayers between top layer and the bottom, it is a plurality of the inlayer certainly the top layer extremely the direction of bottom sets gradually, the top layer with between the inlayer with between the bottom and adjacent two all be equipped with the insulating layer between the inlayer, at least one via hole has been seted up to the base plate, the via hole have with the inlayer pad of inlayer one-to-one, every the size of inlayer pad with correspond the width of the printing wire on the inlayer suits.
According to the utility model discloses printed circuit board suits through the width that makes the size of inlayer pad and the printed conductor on the inlayer that corresponds, alright improve its radio frequency signal's integrality, reduce the insertion loss.
In addition, according to the utility model discloses printed circuit board, can also have following additional technical characterstic:
according to the utility model discloses an embodiment, the width of inlayer pad equals to correspond the width of printed conductor, the width of inlayer pad means the inlayer pad corresponds along the perpendicular to the maximum dimension of printed conductor's length direction.
According to the utility model discloses an embodiment, a plurality of the cross sectional shape of inlayer pad is different.
According to an embodiment of the present invention, the substrate further comprises a power layer or a ground layer disposed between the top layer and the bottom layer.
According to an embodiment of the present invention, the via hole further has a surface layer pad corresponding to the top layer and/or the bottom layer.
According to the utility model discloses an embodiment, the cross sectional shape of top layer pad with the inlayer pad is inequality.
According to the utility model discloses an embodiment, the cross sectional shape of top layer pad or inlayer pad is ring, oval ring or multilateral ring.
The embodiment of the utility model provides an in above-mentioned one or more technical scheme, one of following technological effect has at least:
the utility model discloses simple structure, simple process, the width of the size through making the inlayer pad suits with the printed conductor on the inlayer that corresponds, alright improve its radio frequency signal's integrality, reduce the insertion loss.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a via hole on a printed circuit board according to an embodiment of the present invention;
fig. 2 is a schematic structural view of the printed circuit board according to the embodiment of the present invention, wherein resistors and vias are attached to the upper surface of the printed circuit board;
FIG. 3 is a schematic diagram of the connection of vias to traces on a prior art printed circuit board;
FIG. 4 is a schematic diagram of the connection between via holes and conductive traces on a printed circuit board according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another via hole on a printed circuit board according to an embodiment of the present invention;
fig. 6 is a diagram of insertion loss versus frequency of a printed circuit board according to an embodiment of the present invention.
Reference numerals:
1: a via hole; 1.1: an inner layer pad; 1.2: a surface layer bonding pad; 2: a resistor is pasted on the surface;
3: and (6) printing a conducting wire.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the utility model, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the utility model.
In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "connected" and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the embodiments of the present invention can be understood in specific cases by those skilled in the art.
In embodiments of the invention, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Combine fig. 1, fig. 2, fig. 4, fig. 5 is shown, the embodiment of the utility model provides a printed circuit board, this printed circuit board includes the base plate, the base plate includes the top layer, bottom and a plurality of inlayers of setting between top layer and bottom, a plurality of inlayers set gradually from the direction of top layer to bottom, between top layer and the inlayer, all be equipped with the insulating layer between inlayer and the bottom and between two adjacent inlayers, at least one via hole 1 has been seted up to the base plate, via hole 1 has the inlayer pad 1.1 with inlayer one-to-one, the size of every inlayer pad 1.1 suits with the width of the printed conductor 3 on the inlayer that corresponds, that is to say, the width of every inlayer pad 1.1 equals or slightly is greater than the width of the printed conductor 3 on the corresponding inlayer. The width of the inner pad 1.1 refers to the maximum dimension of the inner pad 1.1 in the direction perpendicular to the length direction of the corresponding printed conductor 3, and for example, the width of the inner pad 1.1 indicates the diameter when it is circular. Further, the width of the inner layer pad 1.1 is preferably 20-40 mil, and the via 1 further has a surface layer pad 1.2 corresponding to the top layer and/or the bottom layer.
The following description will be made of how to set the size of the via 1 on the pcb, taking the top layer of the pcb as 0603 packaged surface mount resistor 2 as an example:
as shown in fig. 2, surface mount resistor 2 on a pcb has two rectangular pads of 59 x 51mil each, one of which is used to connect to a 18mil wide printed wire 3 on one of the inner layers of the pcb. Thus, when the size of the via hole 1 is set according to the size of the rectangular land of the surface mount resistor 2, in order to avoid an increase in the welding difficulty and a decrease in the welding quality due to the fact that the via hole 1 provided in the printed circuit board occupies an excessively large area of the rectangular land, and to avoid an increase in the processing difficulty due to an excessively small diameter of the via hole 1, the diameter of the via hole 1 provided in the printed circuit board is preferably 10 mils and the diameter of the surface land 1.2 is preferably 24 mils. And because the size of the inner layer pad 1.1 in the embodiment of the present invention is adapted to the width of the printed wire 3 on the corresponding inner layer, the diameter of the inner layer pad 1.1 corresponding to the inner layer on the via hole 1 is 18 mil.
It should be noted that the relative size of the inner layer pad 1.1 and the printed wire 3 directly affects the insertion loss of the printed circuit board, and the printed circuit board with the via hole 1 having an aperture of 18mil, the surface layer pad 1.2 having a diameter of 36mil, and the inner layer having the printed wire 3 of 28mil is taken as an example: as shown in fig. 3, according to the conventional printed circuit board arrangement, i.e. the diameter of the inner layer pad 1.1 is the same as the diameter of the surface layer pad 1.2, the diameter of the inner layer pad 1.1 is 36 mils, and the diameter of the inner layer pad 1.1 is greater than the width of the printed conductor 3. As shown in fig. 4, according to the embodiment of the present invention, the size of the inner layer pad 1.1 is adapted to the width of the corresponding printed wire 3 on the inner layer, and then the diameter of the inner layer pad 1.1 in the printed circuit board is preferably 28 mil. Therefore, as shown in table 1 and fig. 6, the insertion loss generated by the two methods is different, and under the same frequency, the insertion loss generated by the printed circuit board in the embodiment of the present invention is significantly smaller than the insertion loss generated by the existing printed circuit board; and, along with the increase of frequency, the insertion loss that current printed circuit board produced with the embodiment of the utility model provides an insertion loss's that printed circuit board produced difference also increases thereupon. It can be seen that the printed circuit board can improve the integrity of the radio frequency signal and reduce the insertion loss by adapting the size of the inner layer bonding pad 1.1 to the width of the corresponding printed conductor 3 on the inner layer.
TABLE 1 insertion loss generated by the existing printed circuit board and the embodiment of the utility model provides an insertion loss contrast table generated by the printed circuit board
| frequency/GHz | Insertion loss/dB of printed circuit board A | Insertion loss/dB of printed circuit board B | Difference C | Percentage D |
| 3 | -0.0164 | -0.0149 | 0.0015 | 10.07 |
| 6 | -0.0391 | -0.0337 | 0.0054 | 16.02 |
| 9 | -0.0744 | -0.0619 | 0.0125 | 20.19 |
Wherein, printed circuit board A is current printed circuit board in table 1, and printed circuit board B is the embodiment of the utility model provides a printed circuit board, difference C represent printed circuit board A's the difference of inserting the loss with printed circuit board B's insertion loss, percentage D represents the ratio of difference C and printed circuit board B's insertion loss.
Further, the plurality of inner layer pads 1.1 differ in cross-sectional shape. Of course, the cross-sectional shapes of the surface layer bonding pad 1.2 and the inner layer bonding pad 1.1 can also be different. The cross section of the surface bonding pad 1.2 or the inner bonding pad 1.1 is a circular ring, an elliptical ring or a polygonal ring. Wherein, the polygonal ring is a polygon with a through hole at the center. For example, as shown in fig. 5, the surface layer pad 1.2 of the via 1 on the printed circuit board is in the shape of a square ring, and the inner layer pad 1.1 is in the shape of a circular ring.
Further, the substrate further comprises a power supply layer or a ground layer arranged between the top layer and the bottom layer.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. The utility model provides a printed circuit board, includes the base plate, the base plate includes top layer, bottom and sets up a plurality of inlayers between top layer and the bottom, it is a plurality of the inlayer certainly the top layer extremely the direction of bottom sets gradually, between the top layer with between the inlayer with between the bottom and adjacent two all be equipped with the insulating layer between the inlayer, its characterized in that, at least one via hole has been seted up to the base plate, the via hole have with the inlayer pad of inlayer one-to-one, every the size of inlayer pad and corresponding the width of printed conductor on the inlayer suits.
2. The printed circuit board of claim 1, wherein the width of the inner pad is equal to the width of the corresponding printed wiring, and the width of the inner pad is the maximum dimension of the inner pad in a direction perpendicular to the length direction of the corresponding printed wiring.
3. The printed circuit board of claim 1, wherein a plurality of the inner pads differ in cross-sectional shape.
4. The printed circuit board of claim 1, wherein the substrate further comprises a power or ground layer disposed between the top layer and the bottom layer.
5. The printed circuit board of any of claims 1 to 4, wherein the via further has a surface pad corresponding to the top layer and/or the bottom layer.
6. The printed circuit board of claim 5, wherein the surface layer pads and the inner layer pads have different cross-sectional shapes.
7. The printed circuit board of claim 5, wherein the surface pad or the inner pad has a cross-sectional shape of a circular ring, an elliptical ring, or a polygonal ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922052935.5U CN211481579U (en) | 2019-11-25 | 2019-11-25 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922052935.5U CN211481579U (en) | 2019-11-25 | 2019-11-25 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211481579U true CN211481579U (en) | 2020-09-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922052935.5U Active CN211481579U (en) | 2019-11-25 | 2019-11-25 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211481579U (en) |
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2019
- 2019-11-25 CN CN201922052935.5U patent/CN211481579U/en active Active
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