CN211478988U

CN211478988U - Clock topological structure of operation server

Info

Publication number: CN211478988U
Application number: CN202020242659.9U
Authority: CN
Inventors: 康金荣; 周贝; 王大岁
Original assignee: Shanghai Conglian Information Technology Co ltd
Current assignee: Shanghai Conglian Information Technology Co ltd
Priority date: 2020-03-03
Filing date: 2020-03-03
Publication date: 2020-09-11
Anticipated expiration: 2030-03-03

Abstract

The utility model provides an operation server clock topological structure, including crystal oscillator and chip array, the chip array comprises the calculation chip that a plurality of matrixes were arranged, have the buffer among the calculation chip, the buffer has clock input end, first clock output end and second clock output end, the crystal oscillator links to each other with the clock input end that is located the first calculation chip in the first row of chip array, and the first clock output end of the calculation chip in the first row connects gradually the clock input end of the next calculation chip in the same row; and the second clock output end of the computing chip in each row is sequentially connected with the clock input end of the next computing chip in the same row. By adopting the clock topological structure, the number of chips supported by a single crystal oscillator can be greatly increased, the number of crystal oscillators is reduced, and the manufacturing cost is reduced.

Description

Clock topological structure of operation server

Technical Field

The utility model relates to a block chain technical field especially relates to a clock topological structure of operation server.

Background

Existing calculation servers typically employ a chip array layout. In such an arrangement, a plurality of computing chips are usually driven by one external crystal oscillator as a clock source, and for the computing chips, the quality of the clock signal directly determines whether the circuit can operate stably. Therefore, in the chip array system, it is important to select a reasonably effective clock topology. If the topology selection is not proper, problems of overshoot, jitter and the like are introduced, so that the quality of a clock signal is affected, and even the operation of an operation server is possibly abnormal. The clock signal topological modes commonly used in the industry at present are two types: one is shown in fig. 3, each group of chips is configured with an external crystal oscillator as a clock source. This approach can guarantee clock signal quality but at a higher cost. As shown in fig. 4, a serial connection method is adopted to cascade clock signals of a certain number of chips, and each crystal oscillator can only drive a limited number of chips to ensure the quality of the clock signals because a new jitter is introduced into each chip when the clock signals pass through the chips, so that a plurality of crystal oscillators still need to be configured to realize the operation of the crystal oscillators, and the cost reduction effect is limited.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a clock topological structure of operation server is provided, when guaranteeing the clock quality, improve the chip quantity that single crystal oscillator can drive by a wide margin to reduce manufacturing cost.

The utility model discloses a following mode is solved this technical problem: a clock topological structure of an operation server comprises a crystal oscillator and a chip array, wherein the chip array is composed of a plurality of computing chips arranged in a matrix manner, a buffer is arranged in each computing chip, the buffer has a clock input end, a first clock output end and a second clock output end, the crystal oscillator is connected with the clock input end of a first computing chip in a first column of the chip array, and the first clock output end of the computing chip in the first column is sequentially connected with the clock input end of the next computing chip in the same column; and the second clock output end of the computing chip in each row is sequentially connected with the clock input end of the next computing chip in the same row.

Therefore, by adopting the structure, the clock signal flows through (M + N-2) chips before reaching the computing chips of the Nth row and the Mth column (N, M are natural numbers), and when the (M + N-2) reaches the limit of the number of the chips which can be driven by a single crystal oscillator, the normal operation of the M.N computing chips can be supported, so that the number of the chips driven by the single crystal oscillator is greatly increased.

As a preferred embodiment of the present invention, the number of rows and the number of columns of the chip array are equal to maximize the number of chips supported by a single crystal oscillator.

More than synthesizing, the utility model discloses a clock topological structure can promote the chip quantity that single crystal oscillator supported by a wide margin, has reduced the use quantity of crystal oscillator to the cost of manufacture has been reduced.

Drawings

The present invention will be further explained with reference to the following drawings:

fig. 1 is a schematic diagram of the topology of the present invention;

FIG. 2 is a schematic diagram of an internal structure of a computing chip;

FIG. 3 is a schematic diagram of a prior art topology;

FIG. 4 is a schematic diagram of another prior art topology;

wherein: 100-crystal oscillator, 200-chip array, 201-computing chip, 202-buffer, 203-clock input terminal, 204-first clock output terminal, 205-second clock output terminal.

Detailed Description

The invention is further illustrated below by means of specific examples:

as shown in fig. 1, a clock topology of an operation server includes a crystal oscillator 100 and a chip array 200.

The chip array 100 is composed of a plurality of computing chips 201 arranged in a matrix, the computing chips 201 have a buffer 202 therein, and the buffer 202 includes a clock input terminal 203, a first clock output terminal 204 and a second clock output terminal 205.

The crystal oscillator 100 is connected with a clock input terminal 203 of a first computing chip 201 in a first column of the chip array 200, and a first clock output terminal 204 of the computing chip 201 in the first column is sequentially connected with the clock input terminal 203 of a next computing chip 201 in the same column; the second clock output 205 of the compute chip 201 in each row is connected in turn to the clock input (203) of the next compute chip 201 in the same row.

Therefore, by adopting the topological structure, the clock signal flows through (M + N-2) chips before reaching the computing chips in the Nth row and the Mth column (N and M are natural numbers), and when the (M + N-2) reaches the limit of the number of the chips which can be driven by a single crystal oscillator, the normal operation of the M.N computing chips can be supported, so that the number of the chips which can be driven by the single crystal oscillator is greatly increased.

The number of rows and columns of the chip array 200 is equal to maximize the number of computing chips driven by a single crystal oscillator. An exponential increase in the number of supporting chips is achieved.

More than synthesizing, the utility model discloses a clock topological structure can promote the calculation chip quantity that single crystal oscillator supported by a wide margin, has reduced the use quantity of crystal oscillator to the cost of manufacture has been reduced.

However, those skilled in the art should realize that the above embodiments are only for illustrative purposes and are not to be used as limitations of the present invention, and that changes and modifications to the above embodiments are intended to fall within the scope of the appended claims, as long as they fall within the true spirit of the present invention.

Claims

1. A clock topological structure of an operation server comprises a crystal oscillator (100) and a chip array (200), wherein the chip array (200) is composed of a plurality of computing chips (201) arranged in a matrix, and the clock topological structure is characterized in that: the computing chip (201) is provided with a buffer (202), the buffer (202) is provided with a clock input end (203), a first clock output end (204) and a second clock output end (205), the crystal oscillator (100) is connected with the clock input end (203) of a first computing chip (201) in a first column of the chip array (200), and the first clock output end (204) of the computing chip (201) in the first column is sequentially connected with the clock input end (203) of the next computing chip (201) in the same column; the second clock output terminal (205) of the computing chip (201) in each row is connected with the clock input terminal (203) of the next computing chip (201) in the same row in sequence.

2. The clock topology of a calculation server according to claim 1, characterized by: the number of rows and the number of columns of the chip array (200) are equal.