CN211457113U - Multiplexing circuit of high-speed pulse receiving and input IO port - Google Patents
Multiplexing circuit of high-speed pulse receiving and input IO port Download PDFInfo
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- CN211457113U CN211457113U CN201922431080.7U CN201922431080U CN211457113U CN 211457113 U CN211457113 U CN 211457113U CN 201922431080 U CN201922431080 U CN 201922431080U CN 211457113 U CN211457113 U CN 211457113U
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Abstract
The utility model provides a high-speed pulse is received and is inputed multiplexing circuit of IO mouth, including high-speed pulse receiving circuit, high-speed pulse receiving circuit has four pulse signal receiving terminals and two pulse signal output ends, two pulse signal output ends are connected respectively in two IO ports of MCU treater, four pulse signal receiving terminals include two pulse signal receiving positive ends and two pulse signal receiving negative ends, two pulse signal receiving positive ends are connected with first multiplexing resistance and second multiplexing resistance respectively, the one end interconnect of pulse signal receiving positive end is kept away from to first multiplexing resistance and second multiplexing resistance, and the COM port has been drawn forth with the public end of second multiplexing resistance to first multiplexing resistance. The utility model discloses the realization can effectively practice thrift the cost to high-speed pulse receiving circuit's multiplexing.
Description
Technical Field
The utility model belongs to the technical field of high-speed pulse is received, especially, relate to a multiplexing circuit of high-speed pulse receiving and input IO mouth.
Background
In order to enable one PCB to cope with different application scenarios, so that the PCB can be applied to both occasions where high-speed pulse signals need to be received and occasions where high-speed pulse signals do not need to be received, it is necessary to provide an IO port for receiving high-speed pulse signals and a port for receiving common signals at the same time.
It is a common practice in the prior art to provide all ports for receiving normal signals and all ports for receiving high-speed pulse signals separately. However, in practical applications, the number of IO ports of the MCU processor is limited, and in order to provide all the required IO ports, the MCU processor with more IO ports needs to be used, but the MCU processor with more IO ports needs more cost and resources. In many PCB circuits, all or part of the IO ports for receiving common signals and the ports for receiving high-speed pulse signals are not used simultaneously, that is, when the PCB circuit board is applied to a situation where high-speed pulse signals need to be received, a plurality of ports for receiving common signals are idle, and when the PCB circuit board is applied to a situation where high-speed pulse signals do not need to be received, the ports for receiving high-speed pulse signals are idle, which causes waste of the IO ports.
SUMMERY OF THE UTILITY MODEL
The utility model aims at the above-mentioned problem, provide a multiplexing circuit of fast pulse receipt and input IO mouth.
In order to achieve the above purpose, the utility model adopts the following technical proposal:
a multiplexing circuit of a fast pulse receiving and input IO port comprises a high-speed pulse receiving circuit, wherein the high-speed pulse receiving circuit is provided with four pulse signal receiving ends and two pulse signal output ends, the two pulse signal output ends are respectively connected with two IO ports of an MCU processor, the four pulse signal receiving ends comprise two pulse signal receiving positive ends and two pulse signal receiving negative ends, the two pulse signal receiving positive ends are respectively connected with a first multiplexing resistor and a second multiplexing resistor, one ends of the first multiplexing resistor and the second multiplexing resistor, which are far away from the pulse signal receiving positive ends, are mutually connected, and a COM port is led out from a common end of the first multiplexing resistor and the second multiplexing resistor, so that when an external signal input circuit is connected with the two pulse signal receiving positive ends and the two pulse signal receiving negative ends, the two pulse signal output ends are used as high-speed pulse signal access ports, when the external signal input circuit is connected to the COM port and the two pulse signal receiving negative terminals, the two pulse signal output terminals are used as common signal access ports.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, the two pulse signal receiving positive terminals and the two pulse signal receiving negative terminals are respectively a command pulse PLUS terminal, a command pulse SIGN positive terminal, a command pulse PLUS terminal and a command pulse SIGN negative terminal.
In the above-mentioned multiplexing circuit of high-speed pulse receiving and input IO mouth, high-speed pulse receiving circuit includes the opto-coupler, and two pulse signal receiving positive terminals are connected respectively at two input positive terminals department of opto-coupler, and two pulse signal receiving negative terminals are connected respectively at two input negative terminals department of opto-coupler, and two pulse signal output ends are connected respectively at two output terminals department of opto-coupler.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, two input negative terminals of the optical coupler are connected to two pulse signal receiving negative terminals through a second resistor and a third resistor respectively.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, two input positive terminals of the optical coupler are connected to two pulse signal receiving positive terminals through a first resistor and a fourth resistor respectively.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, a first capacitor, a fifth resistor and a first diode are connected between the first resistor and the second resistor in parallel; and a second capacitor, a sixth resistor and a second diode which are connected in parallel with the second capacitor are connected between the third resistor and the fourth resistor.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, two output ends of the optical coupler are connected to two pulse signal output ends through a seventh resistor and an eighth resistor respectively, a common end of the seventh resistor and the pulse signal output ends is connected to digital ground through a third capacitor, and a common end of the eighth resistor and the pulse signal output ends is connected to digital ground through a fourth capacitor.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, two output ends of the optical coupler are connected to a power supply end through a ninth resistor and a tenth resistor respectively.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, the type of the optical coupler is ACPL 074L.
In the multiplexing circuit of the high-speed pulse receiving and input IO port, the resistance values of the first multiplexing resistor and the second multiplexing resistor are both 2K ohms.
The utility model has the advantages of, improve through simple circuit and realize the multiplexing to high-speed pulse receiving circuit, make this circuit can enough be applicable to the application scene that needs high-speed pulse, be applicable to the application scene that does not need high-speed pulse again, and will be used for receiving pulse signal's IO port originally as the IO port that is used for receiving ordinary signal under the application scene that does not need high-speed pulse, do not cause the wasting of resources of IO port, effectively practice thrift the cost.
Drawings
Fig. 1 is a circuit diagram of the multiplexing circuit of the fast pulse receiving and input IO port of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the present embodiment discloses a multiplexing circuit of a fast pulse receiving and input IO port, including a high-speed pulse receiving circuit, the high-speed pulse receiving circuit has four pulse signal receiving terminals and two pulse signal output terminals INP, IND, the two pulse signal output terminals INP, IND are respectively connected to two IO ports of an MCU processor, the four pulse signal receiving terminals include two pulse signal receiving positive terminals INP +, IND + and two pulse signal receiving negative terminals INP-, IND-, the two pulse signal receiving positive terminals INP +, IND + are respectively connected to a first multiplexing resistor R111 and a second multiplexing resistor R112, ends of the first multiplexing resistor R111 and the second multiplexing resistor R112 far away from the pulse signal receiving positive terminals INP +, IND + are connected to each other, and a COM port COM + is led out from a common end of the first multiplexing resistor R111 and the second multiplexing resistor R112.
Preferably, the first multiplexing resistor R111 and the second multiplexing resistor R112 both have a resistance of 2K ohms.
In the embodiment, a high-speed pulse receiving circuit is multiplexed, and in an application scene requiring high-speed pulses, an external signal input circuit is directly connected with two pulse signal receiving positive terminals INP +, IND + and two pulse signal receiving negative terminals INP-, IND-, i.e., a first multiplexing resistor R111 and a second multiplexing resistor R112 are idle, and at the moment, two pulse signal output terminals INP and IND serve as high-speed pulse signal access ports to output pulse signals to an MCU processor; under the condition that high-speed pulse does not need to be received and more IO ports are needed, the first multiplexing resistor R111 and the second multiplexing resistor R112 are used, the external signal input circuit is connected with the COM port and the two pulse signal receiving negative terminals INP and IND, and at the moment, the two pulse signal output terminals INP and IND are used as common signal access ports.
The same PCB circuit is used, and different application scenes can be dealt with by adjusting the connecting interface, so that resources can be effectively saved.
Specifically, the two pulse signal receiving positive terminals INP +, IND + and the two pulse signal receiving negative terminals INP-, IND-are a command pulse PLUS terminal, a command pulse SIGN positive terminal, a command pulse PLUS terminal, and a command pulse SIGN negative terminal, respectively.
Specifically, the high-speed pulse receiving circuit includes an optical coupler OP1, and the model adopted by the optical coupler OP1 of the present embodiment is ACPL 074L. Two pulse signal receiving positive terminals INP + and IND + are respectively connected at two input positive ends of the optical coupler OP1, two pulse signal receiving negative terminals INP-, IND-are respectively connected at two input negative ends of the optical coupler OP1, and two pulse signal output terminals INP, IND are respectively connected at two output ends of the optical coupler OP 1.
Further, two input negative terminals of the optical coupler OP1 are connected to two pulse signal receiving negative terminals INP-, IND-, through a second resistor R2 and a third resistor R3, respectively, and the resistances of the second resistor R2 and the third resistor R3 are both 75 ohms.
Similarly, two input positive terminals of the optical coupler OP1 are connected to the two pulse signal receiving positive terminals INP +, IND + through the first resistor R1 and the fourth resistor R4, respectively, and values of the first resistor R1 and the fourth resistor R4 are both 75 ohms.
A first capacitor C19 with the capacity of 2200PF is connected between the first resistor R1 and the second resistor R2, and a fifth resistor R5 and a first diode D1 which are connected with the first capacitor C19 in parallel; a second capacitor C20 with capacity of 2200PF, a sixth resistor R6 connected in parallel with the second capacitor C20 and a second diode D2 are connected between the third resistor R3 and the fourth resistor R4. The fifth resistor R5 and the sixth resistor R6 are both 4.7K ohms, and the first diode D1 and the second diode D2 are both IN 4148.
Further, two output ends of the optical coupler OP1 are connected to the two pulse signal output ends INP and IND through a seventh resistor R16 and an eighth resistor R17, respectively, a common end of the seventh resistor R16 and the pulse signal output end IN is connected to the digital DGND through a third capacitor C21, and a common end of the eighth resistor R17 and the pulse signal output end IND is connected to the digital DGND through a fourth capacitor C22. The capacities of the third capacitor C21 and the fourth capacitor C22 are 2200PF, and the resistances of the seventh resistor R16 and the eighth resistor R17 are 680 ohms.
Further, two output terminals of the optical coupler OP1 are connected to the power supply terminal VDD33 through a ninth resistor R14 and a tenth resistor R15, respectively. And the resistance values of the ninth resistor R14 and the tenth resistor R15 are both 680 ohms.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications, additions and substitutions for the specific embodiments described herein may be made by those skilled in the art without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Although the first multiplexing resistor R111, the second multiplexing resistor R112, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the low-order resistor R5, the sixth resistor R6, the seventh resistor R16, the eighth resistor R17, the ninth resistor R14, the tenth resistor R15, the first capacitor C19, the second capacitor C20, the third capacitor C21, the fourth capacitor C22, the first diode D1, the second diode D2, the optical coupler OP1, the pulse signal output terminals INP, IND, the pulse signal receiving negative terminals INP-, IND-; the pulse signal receives terms like positive terminal INP +, IND +, etc., but does not exclude the possibility of using other terms. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed in a manner that is inconsistent with the spirit of the invention.
Claims (10)
1. A high-speed pulse receiving and input IO port multiplexing circuit comprises a high-speed pulse receiving circuit, wherein the high-speed pulse receiving circuit is provided with four pulse signal receiving ends and two pulse signal output ends, the two pulse signal output ends are respectively connected with two IO ports of an MCU processor, the four pulse signal receiving ends comprise two pulse signal receiving positive ends and two pulse signal receiving negative ends, the high-speed pulse receiving circuit is characterized in that the two pulse signal receiving positive ends are respectively connected with a first multiplexing resistor and a second multiplexing resistor, one ends of the first multiplexing resistor and the second multiplexing resistor, which are far away from the pulse signal receiving positive ends, are mutually connected, and a COM port is led out from a common end of the first multiplexing resistor and the second multiplexing resistor, so that when an external signal input circuit is connected with the two pulse signal receiving positive ends and the two pulse signal receiving negative ends, the two pulse signal output ends are used as high-speed pulse signal access ports, when the external signal input circuit is connected to the COM port and the two pulse signal receiving negative terminals, the two pulse signal output terminals are used as common signal access ports.
2. The multiplexing circuit of high speed pulse reception and input IO port as claimed in claim 1, wherein the two pulse signal reception positive terminals and the two pulse signal reception negative terminals are a command pulse PLUS terminal, a command pulse SIGN positive terminal, a command pulse PLUS terminal, and a command pulse SIGN negative terminal, respectively.
3. The multiplexing circuit of high speed pulse receiving and input IO port according to claim 1, wherein the high speed pulse receiving circuit comprises an optical coupler, two positive pulse signal receiving terminals are respectively connected to two positive input terminals of the optical coupler, two negative pulse signal receiving terminals are respectively connected to two negative input terminals of the optical coupler, and two pulse signal output terminals are respectively connected to two output terminals of the optical coupler.
4. The multiplexing circuit of high-speed pulse receiving and input IO port of claim 3 wherein, the two input negative terminals of said optical coupler are connected to the two pulse signal receiving negative terminals through the second resistor and the third resistor respectively.
5. The multiplexing circuit of high speed pulse receiving and input IO port of claim 4 wherein the two input positive terminals of said optocoupler are connected to the two pulse signal receiving positive terminals through a first resistor and a fourth resistor respectively.
6. The multiplexing circuit for receiving high-speed pulses and inputting the IO port according to claim 5, wherein a first capacitor is connected between the first resistor and the second resistor, and a fifth resistor and a first diode are connected in parallel with the first capacitor; and a second capacitor, a sixth resistor and a second diode which are connected in parallel with the second capacitor are connected between the third resistor and the fourth resistor.
7. The multiplexing circuit of a high speed pulse receiving and input IO port according to claim 6, wherein two output terminals of the optocoupler are connected to two pulse signal output terminals through a seventh resistor and an eighth resistor, respectively, and a common terminal of the seventh resistor and the pulse signal output terminal is connected to digital ground through a third capacitor, and a common terminal of the eighth resistor and the pulse signal output terminal is connected to digital ground through a fourth capacitor.
8. The multiplexing circuit of a high speed pulse receiving and input IO port according to claim 7, wherein two output terminals of the optocoupler are connected to a power supply terminal through a ninth resistor and a tenth resistor, respectively.
9. The multiplexing circuit for high speed pulse reception and input IO port according to claim 8, wherein the optocoupler is of ACPL 074L.
10. The multiplexing circuit for high-speed pulse reception and input IO ports according to any one of claims 1 to 9, wherein the first multiplexing resistor and the second multiplexing resistor each have a resistance of 2K ohms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922431080.7U CN211457113U (en) | 2019-12-30 | 2019-12-30 | Multiplexing circuit of high-speed pulse receiving and input IO port |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922431080.7U CN211457113U (en) | 2019-12-30 | 2019-12-30 | Multiplexing circuit of high-speed pulse receiving and input IO port |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211457113U true CN211457113U (en) | 2020-09-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922431080.7U Expired - Fee Related CN211457113U (en) | 2019-12-30 | 2019-12-30 | Multiplexing circuit of high-speed pulse receiving and input IO port |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211457113U (en) |
-
2019
- 2019-12-30 CN CN201922431080.7U patent/CN211457113U/en not_active Expired - Fee Related
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200908 Termination date: 20201230 |
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| CF01 | Termination of patent right due to non-payment of annual fee |