CN211426752U - High-precision hybrid integrated circuit test jig isolation protection structure - Google Patents
High-precision hybrid integrated circuit test jig isolation protection structure Download PDFInfo
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- CN211426752U CN211426752U CN201922222702.5U CN201922222702U CN211426752U CN 211426752 U CN211426752 U CN 211426752U CN 201922222702 U CN201922222702 U CN 201922222702U CN 211426752 U CN211426752 U CN 211426752U
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Abstract
The utility model discloses a high accuracy hybrid integrated circuit test jig isolation protection structure relates to circuit test auxiliary structure technical field. This test jig isolation protection structure is single chip computer, the test chip, the relay, keep apart opto-coupler and Handle interface integration on a circuit substrate, utilize the opto-coupler to realize that the test jig power detects with ground short circuit, the test jig power is kept apart with the chip power that awaits measuring, can prevent hot plug damage chip, easy to assemble and increase the availability factor, its all analog power and digital power, analog ground and digital ground all adopt the opto-coupler to keep apart, restrain common mode interference, the common mode interference that produces when avoiding the integrated design, guarantee that system signal is stable and whole normal work, the volume of system has been reduced, reduce cost raises the efficiency, can also measure whether the power of chip and ground short circuit, and power and command signal adopt the opto-coupler to keep apart, prevent to crosstalk.
Description
Technical Field
The utility model relates to a circuit test auxiliary structure technical field especially relates to a high accuracy hybrid integrated circuit test jig isolation protection architecture.
Background
The integrated circuit test is an electrical characteristic measurement and use condition test for a chip to be tested, which must be completed after the integrated circuit is manufactured and before the integrated circuit is delivered to a customer.
Integrated circuit testing is the process of testing an integrated circuit or module, determining or evaluating the function and performance of integrated circuit components by measuring the output response to the integrated circuit and comparing the expected output, and is an important means of verifying design, monitoring production, ensuring quality, analyzing failures, and guiding applications.
The abnormal state of the integrated circuit is defective (defect), fault (failure), failure (failure), etc. The integrated circuit is not in accordance with technical conditions and can not work normally due to incomplete design consideration or some physical and chemical factors in the manufacturing process, and the integrated circuit is called to have defects.
A defect in an integrated circuit causes a change in its function, known as a fault. A fault may or may not cause the integrated circuit to fail, and the integrated circuit loses the functionality required to implement its particular specification, referred to as an integrated circuit failure. The faults are equivalent to the defects, but the faults are different from the defects, the defects can cause the faults, the faults are expressed, are relatively stable and are easy to test; the defects are relatively hidden and microscopic, and the defects are difficult to search and locate.
The test rack typically needs to be powered, signaled, and output control signals to the Handle. The hybrid integrated circuit test rack generally needs to provide test signals to a chip to be tested, and collects various output indexes of the chip to be tested under the condition of loading a specific test signal through a single chip microcomputer to analyze and judge whether various technical indexes of the chip are qualified.
At present, chinese patent with publication number CN209525426U discloses an integrated circuit tester, and it includes the workstation, the bottom of workstation is equipped with the supporting leg, the bottom of supporting leg is equipped with moving mechanism, the one end of workstation upper surface is equipped with the PLC controller, the other end of workstation upper surface is equipped with integrated circuit tester main part, the upper surface of integrated circuit tester main part inner chamber is equipped with the relay matrix board.
In the test process of the integrated circuit test rack, in order to protect a chip to be tested, a switch is generally required to be installed on a power supply of the test chip to prevent the chip from being damaged by live insertion, and the use efficiency is very low; if the signal source adopts a standard signal generator, the cost is high, the installation is inconvenient, and the system signal is unstable and cannot work normally due to common-mode interference during the integrated design; the signal of test jig output needs to be connected with Handle, because the two mains voltage are different, in order to prevent the interference, generally add the relay isolation, with high costs, bulky, inefficiency.
SUMMERY OF THE UTILITY MODEL
The utility model provides an above-mentioned technical problem, overcome prior art's shortcoming, provide a high accuracy hybrid integrated circuit test jig isolation protection structure.
In order to solve the technical problem, the utility model provides a high accuracy hybrid integrated circuit test jig isolation protection structure.
The technical effects are as follows: can prevent hot plugging from damaging the chip, easy to assemble and increase the availability factor, all analog power supplies and digital power supplies thereof, the opto-coupler isolation is adopted to analog ground and digital ground, restrain the common mode interference, the common mode interference that produces when avoiding the integrated design, guarantee that system signal is stable and whole work is normal, the volume of system has been reduced, reduce cost raises the efficiency, can also measure whether the power and the ground of chip short circuit, and power and command signal adopt the opto-coupler to keep apart, prevent to crosstalk.
The utility model discloses the technical scheme who further injects is: the utility model provides a high accuracy hybrid integrated circuit test jig isolation protection architecture, includes circuit substrate, the last integration of circuit substrate has:
the test rack comprises a chip socket to be tested, a power supply module and a single chip microcomputer, wherein the chip socket to be tested is used for supplying power to the whole test rack and controlling and analyzing the test module;
the ADC/DAC detection unit is isolated and powered through the power supply module, a signal line between the single chip microcomputer and the ADC/DAC detection unit is isolated through a high-speed optical coupler HCPL2231, and a2 omega/2W test resistor is connected in series with a power supply input end of the single chip microcomputer;
the Handle module, the setting is kept apart To the power module in Handle module and the test jig, still is equipped with the To _ Handle socket that is used for connecting test jig and automated inspection instrument on the circuit substrate, and singlechip test signal selects in order To realize multiplexed output through the 138 decoders of locating in the circuit substrate, and the instruction signal of Handle module and singlechip all keeps apart through high-speed opto-coupler HCPL 2231.
Further, the voltage regulator comprises MAX8875EUK50-T, MAX6198AESA and MAX6191AESA, which are respectively connected with the ADC/DAC detection unit and used for ensuring the accuracy and stability of the reference voltage in the ADC/DAC detection unit.
In the high-precision hybrid integrated circuit test jig isolation protection structure, the type of the single chip microcomputer is AT89S52, an ADC chip in the ADC/DAC detection unit is CS5532, and the DAC chip is DAC 8534.
The high-precision hybrid integrated circuit test jig isolation protection structure comprises a single chip microcomputer AT89S51, an ADC chip CS5532, a DAC chip DAC8534, a high-speed optical coupler HCPL2231, a relay and a Handle module, wherein interfaces of the single chip microcomputer AT89S51, the ADC chip CS5532, the DAC chip DAC8534, the high-speed optical coupler HCPL2231, the relay and the Handle module are integrated on the same circuit substrate.
The high-precision hybrid integrated circuit test jig isolation protection structure comprises a single chip microcomputer, wherein the single chip microcomputer controls an ADC (analog-to-digital converter) chip and a DAC (digital-to-analog converter) chip through high-speed optical coupling isolation, and the single chip microcomputer is isolated from an interface of a Handle module and a power supply module through optical couplings.
The utility model has the advantages that:
(1) the utility model discloses in, the power test of chip adopts the relay isolation technique. The single chip microcomputer controls the switch of the relay EA2-5, the power supply of the chip to be tested is separated from the power supply of the test frame, and power supply crosstalk is prevented. The circuit can also measure whether the power supply and the ground of the chip are short-circuited or not;
(2) the utility model discloses in, high accuracy constant voltage power supply design and isolation technique guarantee that the required reference voltage of AD and DA conversion is accurate, stable through stabiliser MAX8875EUK50-T, MAX6198AESA, MAX6191AESA, and all analog power and digital power, analog ground and digital ground all adopt the opto-coupler to keep apart, restrain common mode interference;
(3) in the utility model, the power supply and the instruction signal of the Handle are isolated by the optical coupler to prevent crosstalk, the test signal is given by the single chip microcomputer and is selected by the 138 decoder to realize multi-path output and can be expanded;
(4) the utility model discloses can prevent that hot plug from damaging the chip, easy to assemble and increase the availability factor, all analog power supply and digital power supply thereof, the opto-coupler isolation is all adopted with digital ground to the simulation ground, restrain the common mode interference, the common mode interference that produces when avoiding the integrated design, guarantee system signal stability and whole normal work, the volume of system has been reduced, reduce cost raises the efficiency, can also measure whether the power and the ground of chip short circuit, and power and command signal adopt the opto-coupler to keep apart, prevent to crosstalk.
Drawings
FIG. 1 is a circuit diagram of a power supply in embodiment 1;
FIG. 2 is a circuit diagram showing the connection between a power supply and an ADC/DAC detection unit according to embodiment 1;
FIG. 3 is a circuit diagram showing the connection of a power supply and a Handle module in embodiment 1;
fig. 4 is an overall circuit diagram in embodiment 1.
Detailed Description
The embodiment provides a high accuracy hybrid integrated circuit test jig isolation protection architecture, including circuit substrate, the last integration of circuit substrate has:
the test rack comprises a chip socket to be tested, a power supply module and a single chip microcomputer, wherein the chip socket to be tested is used for supplying power to the whole test rack and controlling and analyzing the test module;
the ADC/DAC detection unit is isolated and powered through the power supply module, a signal line between the single chip microcomputer and the ADC/DAC detection unit is isolated through a high-speed optical coupler HCPL2231, and a2 omega/2W test resistor is connected in series with a power supply input end of the single chip microcomputer;
the Handle module, the setting is kept apart To the power module in Handle module and the test jig, still is equipped with the To _ Handle socket that is used for connecting test jig and automated inspection instrument on the circuit substrate, and singlechip test signal selects in order To realize multiplexed output through the 138 decoders of locating in the circuit substrate, and the instruction signal of Handle module and singlechip all keeps apart through high-speed opto-coupler HCPL 2231.
The voltage stabilizer comprises MAX8875EUK50-T, MAX6198AESA and MAX6191AESA which are respectively connected with the ADC/DAC detection unit and used for ensuring the accuracy and stability of reference voltage in the ADC/DAC detection unit. The model of the single chip microcomputer is AT89S52, an ADC chip in the ADC/DAC detection unit is CS5532, and a DAC chip is DAC 8534.
The single chip microcomputer AT89S51, the ADC chip CS5532, the DAC chip DAC8534, the high-speed optical coupler HCPL2231, the relay and the interface of the Handle module are integrated on the same circuit substrate. The single chip microcomputer controls the ADC chip and the DAC chip through high-speed optical coupling isolation, and the single chip microcomputer is isolated from an interface of the Handle module and the power supply module through the optical coupling.
As shown in fig. 1-4, during operation, the single chip microcomputer is IC6, the relay is IC7 and IC8(EA2-5), power supply short circuit detection and isolated power supply are performed, and after the chip to be tested is installed in the test seat, the single chip microcomputer controls the on-off of the relay to test whether the power supply and the ground of the chip are short-circuited. After the chip power supply is detected to be normal, the working power supply of the chip is switched on through the relay;
secondly, the ADC and DAC power supplies are isolated and mainly include ICs 3(7805), R6, the filter capacitor network, ICs 5(7806), IC1(MAX8875), and the filter capacitor network. During the working process of AVDD and DVDD generated by the voltage-stabilized power supply, signal lines given by all the single-chip microcomputers AT89S52 are isolated by the high-speed optocouplers HCPL2231 and sent to the ADC and DAC units, so that the influence of power supply fluctuation on conversion accuracy is prevented.
Meanwhile, a power resistor of about 2 omega/2W is connected in series with the input end DVDD of the singlechip power supply, the working current of the chip can be tested, voltage signals AD _ CH1+ and AD _ CH 1-at two ends of the resistor can be sampled and sent to the positive input end and the negative input end of the high-precision ADC in a differential mode, and any one of AD _ CH +, AD _ CH-can be connected into the input end of the single-chip ADC from AD _ CH 1-AD _ CH 4.
And finally, the Handle power supply is isolated from the test jig power supply DVDD, the To _ Handle socket is a passage for connecting the test jig with the automatic detection instrument, and the test jig power supply DVDD and the Handle power supply are isolated from each other by the optocoupler PC817 for power supply. The test signal is given by the single chip microcomputer and is selected by a 138 decoder, so that multi-path output (expandable) is realized, and the test signal is isolated by an optical coupler at the same time.
In addition to the above embodiments, the present invention may have other embodiments. All the technical solutions formed by adopting equivalent substitutions or equivalent transformations fall within the protection scope claimed by the present invention.
Claims (5)
1. The utility model provides a high accuracy hybrid integrated circuit test jig isolation protection architecture, includes circuit substrate, its characterized in that, the last integration of circuit substrate has:
the test rack comprises a chip socket to be tested, a power supply module and a single chip microcomputer, wherein the chip socket to be tested is used for supplying power to the whole test rack and controlling and analyzing the test module;
the ADC/DAC detection unit is isolated and powered through the power supply module, a signal line between the single chip microcomputer and the ADC/DAC detection unit is isolated through a high-speed optical coupler HCPL2231, and a2 omega/2W test resistor is connected in series with a power supply input end of the single chip microcomputer;
the Handle module, the setting is kept apart To the power module in Handle module and the test jig, still is equipped with the To _ Handle socket that is used for connecting test jig and automated inspection instrument on the circuit substrate, and singlechip test signal selects in order To realize multiplexed output through the 138 decoders of locating in the circuit substrate, and the instruction signal of Handle module and singlechip all keeps apart through high-speed opto-coupler HCPL 2231.
2. The high-precision hybrid integrated circuit test jig isolation protection architecture of claim 1, wherein: the voltage stabilizer comprises MAX8875EUK50-T, MAX6198AESA and MAX6191AESA which are respectively connected with the ADC/DAC detection unit and used for ensuring the accuracy and stability of reference voltage in the ADC/DAC detection unit.
3. The high-precision hybrid integrated circuit test jig isolation protection architecture of claim 1, wherein: the type of the single chip microcomputer is AT89S52, an ADC chip in the ADC/DAC detection unit is CS5532, and a DAC chip is DAC 8534.
4. The high-precision hybrid integrated circuit test jig isolation protection architecture of claim 3, wherein: the single chip microcomputer AT89S51, the ADC chip CS5532, the DAC chip DAC8534, the high-speed optical coupler HCPL2231, the relay and the interface of the Handle module are integrated on the same circuit substrate.
5. The high-precision hybrid integrated circuit test jig isolation protection architecture of claim 4, wherein: the single chip microcomputer controls the ADC chip and the DAC chip through high-speed optical coupling isolation, and the single chip microcomputer is isolated from an interface of the Handle module and the power supply module through optical couplings.
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| CN111060836A (en) * | 2019-12-12 | 2020-04-24 | 无锡职业技术学院 | High-precision hybrid integrated circuit test jig isolation protection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111060836A (en) * | 2019-12-12 | 2020-04-24 | 无锡职业技术学院 | High-precision hybrid integrated circuit test jig isolation protection structure |
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