CN211350644U - Electrostatic protection circuit for integrated circuit - Google Patents
Electrostatic protection circuit for integrated circuit Download PDFInfo
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- CN211350644U CN211350644U CN202020103507.0U CN202020103507U CN211350644U CN 211350644 U CN211350644 U CN 211350644U CN 202020103507 U CN202020103507 U CN 202020103507U CN 211350644 U CN211350644 U CN 211350644U
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Abstract
The utility model discloses an electrostatic protection circuit of an integrated circuit, which comprises a protection point, wherein the electrostatic protection circuit comprises a forward trigger circuit and a reverse trigger circuit; the forward trigger circuit comprises a clamping triode; the reverse trigger circuit comprises at least one diode circuit; the diode circuit includes a cathode terminal and an anode terminal; and the collector electrode of the clamping triode is electrically connected with the protection point, the base electrode of the clamping triode is electrically connected with the cathode end, and the emitter electrode of the clamping triode and the anode end are grounded. The utility model provides an integrated circuit's electrostatic protection circuit can compromise the electrostatic protection effect, and the circuit area occupied is little, parasitic device is little, can guarantee integrated circuit chip's normal work simultaneously.
Description
Technical Field
The utility model relates to an integrated circuit field, in particular to integrated circuit's electrostatic protection circuit.
Background
ESD (Electrostatic Discharge) is an important reliability issue in integrated circuit fabrication. Static charges can be accumulated on the chip in the manufacturing process of the integrated circuit, so that a potential difference between the chip and other parts or other objects is generated, if the potential difference is very high, the accumulated charges can be instantaneously exchanged between the chip and the other parts or other objects due to a high electric field, so that strong current and electromagnetic pulses are generated, the chip is damaged or permanently damaged, the product quality and reliability are finally reduced, and the product yield is reduced. For example, a human body may generate several hundreds to several thousands of volts of static voltage in a working environment, and when the static voltage is generated when the static voltage is close to or in contact with a chip, a transient current of up to several amperes may be generated, and if the chip is not protected by ESD, permanent damage to devices (such as resistors, capacitors, transistors, and the like) on the chip may be caused.
With the high integration and miniaturization of integrated circuits, the requirements for ESD protection circuits are becoming more and more demanding. Especially, the rf integrated circuit not only requires the ESD protection circuit to play a role of protecting the chip from ESD shock in all directions, but also requires the occupied area to be as small as possible, and meanwhile, the parasitic device is also as small as possible, so that the normal operation of the rf chip is not affected. How to consider the electrostatic protection effect in the radio frequency integrated circuit, and simultaneously reduce the occupied area of the circuit and the parasitic devices as much as possible to ensure the normal work of the radio frequency chip is a problem which needs to be solved urgently.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is that the electrostatic protection circuit in order to overcome integrated circuit among the prior art can't compromise the defect of the size of electrostatic protection effect and circuit area occupied and parasitic device, provides one kind and can compromise the electrostatic protection effect, and circuit area occupied is little, parasitic device is little, can guarantee the integrated circuit's of the normal work of chip electrostatic protection circuit simultaneously.
The utility model discloses an above-mentioned technical problem is solved through following technical scheme:
the utility model provides an electrostatic protection circuit of an integrated circuit, the integrated circuit comprises a protection point, the electrostatic protection circuit comprises a forward trigger circuit and a reverse trigger circuit;
the forward trigger circuit comprises a clamping triode;
the reverse trigger circuit comprises at least one diode circuit; the diode circuit includes a cathode terminal and an anode terminal;
and the collector electrode of the clamping triode is electrically connected with the protection point, the base electrode of the clamping triode is electrically connected with the cathode end, and the emitter electrode of the clamping triode and the anode end are grounded.
In the scheme, the parasitic capacitor mainly comes from an equivalent series capacitor of a PN junction reverse bias parasitic capacitor between a base electrode and a collector electrode of the clamping triode and a reverse bias parasitic capacitor in the diode circuit under a normal positive voltage bias state. Because the parasitic capacitance of the PN junction in the reverse working area is small, the parasitic capacitance introduced by the electrostatic protection circuit provided by the scheme is small, and the influence on the protected integrated circuit is small.
The scheme can give consideration to the electrostatic protection effect, the circuit occupies small area and the parasitic device is small, and the normal work of the integrated circuit chip can be ensured.
Preferably, the reverse trigger circuit comprises one of the diode circuits, the diode circuit comprising one diode; the cathode of the diode is the cathode end, and the anode of the diode is the anode end.
In the scheme, the electrostatic protection circuit only uses two devices, so that the area occupied by an integrated circuit chip can be reduced to the greatest extent, and the cost is reduced; meanwhile, the forward ESD trigger voltage range of the electrostatic protection circuit is wide, the parasitic influence on the protected integrated circuit is small, and the ESD problem of the integrated circuit can be effectively solved.
Preferably, the reverse trigger circuit comprises a plurality of the diode circuits, each of the diode circuits comprising a diode; the plurality of diodes are connected in series in such a manner that the directions of cathodes are consistent, one end of the plurality of diodes connected in series, which faces the cathodes, is the cathode end, and one end of the plurality of diodes connected in series, which faces the anodes, is the anode end.
In the scheme, the reverse trigger circuit is formed by connecting a plurality of diodes in series. When the protection point of the electrostatic protection circuit is subjected to reverse ESD pulse, the reverse clamping voltage is the sum of forward conducting voltages of all diodes and the forward conducting voltage of a PN junction between a base electrode and a collector electrode of the clamping triode. Because a plurality of diodes are connected in series to serve as trigger diodes, the reverse clamping voltage is correspondingly increased, and the range of the reverse trigger voltage of the electrostatic protection circuit is enlarged.
Preferably, the diode is implemented by a triode.
Preferably, the adoption of the triode is realized by electrically connecting a base electrode and a collector electrode of the triode of the reverse trigger circuit as a cathode of the diode and an emitter electrode of the triode of the reverse trigger circuit as an anode of the diode.
Preferably, the clamping transistor is an NPN (one type of transistor) type transistor.
Preferably, the integrated circuit is a radio frequency integrated circuit.
The utility model discloses an actively advance the effect and lie in: the utility model provides an integrated circuit's electrostatic protection circuit can compromise the electrostatic protection effect, and the circuit area occupied is little, parasitic device is little, can guarantee integrated circuit chip's normal work simultaneously.
Drawings
Fig. 1 is a circuit diagram of an electrostatic protection circuit of an integrated circuit according to embodiment 1 of the present invention.
Fig. 2 is a circuit diagram of an electrostatic protection circuit of an integrated circuit according to embodiment 2 of the present invention.
Fig. 3 is a circuit diagram of an electrostatic protection circuit of an integrated circuit according to embodiment 3 of the present invention.
Detailed Description
The present invention is further illustrated by way of the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in FIG. 1, the present embodiment provides an electrostatic protection circuit of an integrated circuit, the integrated circuit 5 includes a protection point 1, the electrostatic protection circuit includes a forward trigger circuit 2 and a reverse trigger circuit3. The forward trigger circuit 2 comprises a clamping triode T1; the reverse trigger circuit 3 includes a diode circuit including a cathode terminal and an anode terminal. The diode circuit is composed of a diode D1Realization, diode D1The cathode of (D) is a cathode terminal, and a diode D1The anode of (2) is an anode terminal. The collector C of the clamp triode T1 is connected with the protection point 1, and the base B of the clamp triode T1 is connected with the diode D1That is, the cathode terminal, clamps the emitter E of the transistor T1 and the diode D1I.e. the anode terminals are all connected to ground 4. The clamping transistor T1 is an NPN transistor, and the integrated circuit 5 is a radio frequency integrated circuit.
In this embodiment, when the ESD protection circuit is applied to the protection point 1 in the forward direction, the collector C of the clamping transistor T1 is much higher than the base B, so that the PN junction between the base B and the collector C of the clamping transistor T1 is subjected to reverse voltage surge, causing it to temporarily break down in the reverse direction, thereby temporarily providing a path for current to flow from the collector C to the base B, and the diode D connected to the base B1Now connected in reverse, so it is assumed that the voltage at the base B does not exceed the diode D1The current flowing from the collector C to the base B is not shunted through the diode D1The current to the base B can only flow to the emitter E through the base B at this time, so that the collector C to the emitter E of the clamping transistor T1 is turned on, a large amount of current is drained to the emitter E through the collector C of the clamping transistor T1, that is, to the ground, and the voltage of the protection point where the electrostatic protection circuit is located is clamped, thereby protecting the integrated circuit 5. In this embodiment, the clamp voltage approaches the sum of the reverse breakdown voltage of the PN junction between the BC electrodes of the clamp transistor T1 and the forward conduction voltage of the PN junction between the BE electrodes of the clamp transistor T1 when the protection point is subjected to a forward ESD pulse. The former can reach about 10-30V (volt) on most modern radio frequency integrated circuit processes, the latter is about 0.5-1.5V, and the sum of the two is far greater than the working voltage of the integrated circuit chip, so that the normal work of the circuit where the protected integrated circuit chip is located is not influenced. In this embodiment, the diode D1Reverse breakdown ofWhen the voltage is higher than the voltage V when the clamping triode T1 is conductedBE(potential difference from the base electrode B to the emitter electrode E). V when the base B of the clamping triode is conducted to the emitter EBEWill be maintained at a small value (e.g. about 0.7-1.5V), i.e. diode D1The reverse voltage is maintained at a small value when the clamping transistor T1 is turned on, which is much smaller than the diode D of the diode circuit in most integrated circuit processes1The above condition is easily satisfied under most processes. In addition, due to the current amplification principle (I) of the clamp transistor T1CE～＝βIBEWherein β is current amplification coefficient when clamping the triode), the reverse breakdown current of PN junction between BC poles of clamping triode T1 is far less than ICETherefore, the PN junction between the BC poles of the clamping triode T1 cannot be broken down permanently in the process, and the normal work of the electrostatic protection circuit is guaranteed.
In this embodiment, when the protection point 1 where the electrostatic protection circuit is located receives a reverse ESD pulse, the potential of the emitter E of the clamping transistor T1 is higher than that of the collector C; the anode terminal of the trigger diode circuit is at a higher potential than the cathode terminal, i.e. diode D1Is higher than the cathode, in which case the diode D1Forward conduction and triggering ESD protection to ensure that PN junction between BC poles of the clamping triode T1 is also forward conducted, negative charge is put into a collector C from a protection point 1 where the electrostatic protection circuit is located through the clamping triode T1, flows through a base B and then passes through a diode D1And flows to ground. Thereby clamping the potential of the protection point 1 at which the electrostatic protection circuit is located, and effectively protecting the integrated circuit 5 from ESD shock. This clamping voltage is equal to the trigger diode D1And the forward conduction voltage of the PN junction between the BC pole of the clamping transistor T1. That is, when the voltage of the protection point 1 where the ESD protection circuit is located is lower than the clamping voltage, the ESD protection circuit provided in this embodiment triggers protection of the ESD reverse pulse. Under most conditions, the working voltage of the protected integrated circuit is not lower than 0V, so that negative voltage clamping cannot be triggered when the chip circuit of the protected integrated circuit works normally, and influence is avoidedAnd (5) normal operation of the chip. It is noted that according to the triode operating principle, the clamping triode T1 operates in the reverse bias region under this condition, and partial negative charge of the collector C also flows from the collector C to the emitter E under the forward conduction of the PN junction between the BC electrodes, so that the shunting path of the negative charge is also increased. Specifically, IEC＝βR*IBC＝βR*ID1Wherein βRIs a clamping triode T1 reverse bias current amplification factor, ID1To flow through a diode D1βRAbout 0.1-1 in most integrated circuit processes, the clamp transistor T1 can take part of the shunting capability during reverse ESD pulses. Accordingly, diode D1And the size of the clamp transistor T1 may also be adjusted in design based on this function.
In this embodiment, the parasitic capacitor mainly originates from the diode D and the PN junction reverse bias parasitic capacitor between the BC pole of the clamp transistor T1 in the normal positive voltage bias state1The equivalent series capacitance of the reverse bias parasitic capacitance of (1). Since the parasitic capacitance of the PN junction in the reverse operating region is small, the electrostatic protection circuit provided in this embodiment introduces a small parasitic capacitance, and has a very small influence on the protected integrated circuit 5.
In the embodiment, the electrostatic protection circuit only uses two devices, so that the area occupied by an integrated circuit chip can be reduced to the greatest extent, and the cost is reduced; meanwhile, the forward ESD trigger voltage range of the electrostatic protection circuit is wide, the parasitic influence on the protected integrated circuit is small, and the ESD problem of the integrated circuit can be effectively solved.
The electrostatic protection circuit of the integrated circuit provided by the embodiment can give consideration to the electrostatic protection effect, the occupied area of the circuit is small, the parasitic device is small, and the normal work of the integrated circuit chip can be ensured.
Example 2
As shown in fig. 2, the present embodiment is a further improvement on embodiment 1. The difference is that the reverse trigger circuit 3 in this embodiment comprises a plurality of diode circuits, each comprising a diode, denoted asD in FIG. 21……Dn(ii) a A plurality of diodes D1……DnIn series with the cathodes oriented in the same direction, i.e. diodes D1Anode of (2) and diode D2(not shown) is electrically connected to the cathode of a diode D2Anode of (2) in turn with diode D3(not shown) cathode electrical connection, … …, diode Dn-1(not shown) an anode and a diode DnA plurality of diodes D connected in series1……DnThe cathode-facing end of (A) is a cathode end, i.e. a diode D1The cathode of the diode is a cathode end, and a plurality of diodes D are connected in series1……DnThe anode-facing end of (a) is the anode end, i.e. diode DnThe anode of (2) is an anode terminal.
In this embodiment, the parasitic capacitor mainly originates from the diode D and the PN junction reverse bias parasitic capacitor between the BC pole of the clamp transistor T1 in the normal positive voltage bias state1……DnThe equivalent series capacitance of the reverse bias parasitic capacitance of (1). Because the parasitic capacitance of the PN junction in the reverse working area is small and the equivalent capacitance is reduced by the series connection of the capacitors, the electrostatic protection circuit provided by the embodiment has small introduced parasitic capacitance and has small influence on the protected integrated circuit 5.
In this embodiment, the forward trigger circuit 2 is composed of a clamping transistor T1, and the reverse trigger circuit 3 is composed of n (n is greater than or equal to 2) trigger diodes D1……DnAre connected in series. When the protection point 1 where the electrostatic protection circuit is located is subjected to a positive ESD pulse, the working principle of the electrostatic protection circuit is similar to that in embodiment 1, and its positive clamping voltage is also consistent with that, i.e. is much larger than the working voltage of the protected chip circuit in most integrated circuit processes. However, when the protection point 1 where the electrostatic protection circuit is located receives a reverse ESD pulse, the reverse clamp voltage is equal to VD1+VD2+……+VDn+VCB(wherein VDxFor triggering diode DxForward on voltage of VCBThe forward conduction voltage of the PN junction between the CB poles of transistor T1 is clamped. Due to series connection ofThe reverse clamping voltage is correspondingly increased by more than two trigger diodes, so that the range of the reverse trigger voltage of the electrostatic protection circuit is enlarged.
Example 3
As shown in fig. 3, the present embodiment is a further improvement on embodiment 1. The difference is that the diode D in this embodiment1The method is realized by adopting a triode. Specifically, the base and collector of the transistor in the reverse trigger circuit 3 are electrically connected as a diode D1The emitter of the triode of the reverse trigger circuit 3 is used as a diode D1Of (2) an anode. The selection of the implementation of the transistor or the diode by the back-trigger circuit 3 depends on the specific manufacturing process and application requirements.
Although specific embodiments of the present invention have been described above, it will be understood by those skilled in the art that this is by way of example only and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and the principles of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (7)
1. An electrostatic protection circuit of an integrated circuit, the integrated circuit comprising a protection point, wherein the electrostatic protection circuit comprises a forward trigger circuit and a reverse trigger circuit;
the forward trigger circuit comprises a clamping triode;
the reverse trigger circuit comprises at least one diode circuit; the diode circuit includes a cathode terminal and an anode terminal;
and the collector electrode of the clamping triode is electrically connected with the protection point, the base electrode of the clamping triode is electrically connected with the cathode end, and the emitter electrode of the clamping triode and the anode end are grounded.
2. The integrated circuit electrostatic protection circuit of claim 1, wherein said reverse trigger circuit comprises one of said diode circuits, said diode circuit comprising one diode; the cathode of the diode is the cathode end, and the anode of the diode is the anode end.
3. The electrostatic protection circuit of an integrated circuit of claim 1, wherein said reverse trigger circuit comprises a plurality of said diode circuits, each of said diode circuits comprising a diode; the plurality of diodes are connected in series in such a manner that the directions of cathodes are consistent, one end of the plurality of diodes connected in series, which faces the cathodes, is the cathode end, and one end of the plurality of diodes connected in series, which faces the anodes, is the anode end.
4. The esd protection circuit of claim 2 or 3, wherein the diode is implemented as a transistor.
5. The esd protection circuit of claim 4, wherein the transistor is implemented to electrically connect a base and a collector of the transistor of the reverse trigger circuit as a cathode of the diode, and an emitter of the transistor of the reverse trigger circuit as an anode of the diode.
6. The integrated circuit electrostatic protection circuit of claim 1, wherein the clamping transistor is an NPN transistor.
7. The integrated circuit electrostatic protection circuit of claim 1, wherein the integrated circuit is a radio frequency integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020103507.0U CN211350644U (en) | 2020-01-17 | 2020-01-17 | Electrostatic protection circuit for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020103507.0U CN211350644U (en) | 2020-01-17 | 2020-01-17 | Electrostatic protection circuit for integrated circuit |
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| Publication Number | Publication Date |
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| CN211350644U true CN211350644U (en) | 2020-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202020103507.0U Active CN211350644U (en) | 2020-01-17 | 2020-01-17 | Electrostatic protection circuit for integrated circuit |
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| CN (1) | CN211350644U (en) |
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