CN112397499B - Electrostatic discharge protection device and method - Google Patents

Abstract

The electrostatic discharge protection device includes a first clamping circuit, a second clamping circuit and a diode circuit. The first clamping circuit is coupled between the first power rail and the second power rail. The second clamping circuit is coupled between the third power rail and the second power rail. The diode circuit is used to direct the electrostatic discharge current from the input and output pads to at least one of the first clamp circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage. The electrostatic discharge protection device and method provided by some embodiments of this case can provide a set of clamping circuits with lower operating voltage and lower internal resistance to improve the performance of the electrostatic discharge protection device.

Description

Electrostatic discharge protection devices and methods

Technical field

This case relates to an electrostatic discharge protection device, and in particular to an electrostatic discharge protection device and method using a median voltage.

Background technique

Generally speaking, integrated circuits are implemented with one or more transistors. With the development of manufacturing processes, the size of transistors is getting smaller and smaller. In order to avoid damage caused by excessive voltage stress caused by electrostatic discharge, electrostatic discharge protection circuits are often used to protect integrated circuits from electrostatic discharge damage. In the existing technology, considering the withstand voltage, electrostatic discharge protection circuits are implemented with input and output transistors. As such, the internal resistance of the discharge path in the electrostatic discharge protection circuit may be high, thereby reducing the effectiveness of the electrostatic discharge protection circuit.

Contents of the invention

In order to solve the above problems, some aspects of this case provide an electrostatic discharge protection device, which includes a first clamping circuit, a second clamping circuit and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is used to direct an electrostatic discharge current from an input-output pad to at least one of the first clamp circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage higher than the second voltage.

In some embodiments, the first clamping circuit is implemented by a plurality of core transistors, and the second clamping circuit is implemented by a plurality of input-output transistors or a plurality of stacked core transistors.

In some embodiments, the first voltage is 2/3˜3/4 times the third voltage.

In some embodiments, a discharge capability of the first clamp circuit is higher than a discharge capability of the second clamp circuit.

In some embodiments, an internal resistance of the first clamp circuit is lower than an internal resistance of the second clamp circuit.

In some embodiments, the diode circuit includes a first diode, a second diode, and a third diode. The anode of the first diode is coupled to the input-output pad, and the cathode of the first diode is coupled to the first power rail. The anode of the second diode is coupled to the first power rail, and the cathode of the second diode is coupled to the third power rail. The anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input-output pad.

In some embodiments, the electrostatic discharge current is directed to the first clamp circuit via the first diode, or to the third power rail via the first diode and the second diode in sequence. .

In some embodiments, the diode circuit includes a first diode, a second diode, and a third diode. The anode of the first diode is coupled to the input-output pad, and the cathode of the first diode is coupled to the first power rail. The anode of the second diode is coupled to the input-output pad, and the cathode of the second diode is coupled to the third power rail. The anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input-output pad.

In some embodiments, the electrostatic discharge current is directed to the first clamp circuit via the first diode or to the third power rail via the second diode.

In some embodiments, the diode circuit includes a first diode, a second diode, and a third diode. The anode of the first diode is coupled to the input-output pad, and the cathode of the first diode is coupled to the first power rail. The anode of the second diode is coupled to the second power rail, and the cathode of the second diode is coupled to the third power rail. The anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input-output pad.

In some embodiments, the electrostatic discharge current is directed to the first clamp circuit through the first diode, or through the first diode, the first clamp circuit and the second diode in sequence Directed to this third power rail.

Some aspects of the present invention provide an electrostatic discharge protection method that includes the following operations: directing an electrostatic discharge current from an input and output pad through a diode circuit to a first clamp circuit or a first power rail. at least one; and discharging the electrostatic discharge current through the first clamp circuit, wherein the first clamp circuit is coupled between a second power rail and a third power rail, a second clamp circuit coupled between the first power rail and the second power rail, the first power rail receives a first voltage, the second power rail receives a second voltage, and the third power rail receives a third voltage, The first voltage is higher than the third voltage, and the third voltage is higher than the second voltage.

To sum up, the electrostatic discharge protection device and electrostatic discharge protection method provided by some embodiments of this case can provide a set of clamping circuits with lower operating voltage and lower internal resistance to improve the performance of the electrostatic discharge protection device.

Description of the drawings

Figure 1 is a schematic diagram of an electrostatic discharge (ESD) protection device drawn according to some embodiments of this case;

Figure 2 is a schematic diagram of an ESD protection device drawn according to some embodiments of this case;

Figure 3 is a schematic diagram of an ESD protection device drawn according to some embodiments of this case;

Figure 4 is a schematic diagram of a clamping circuit drawn according to some embodiments of this case;

Figure 5 is a schematic diagram of a clamping circuit drawn according to some embodiments of this case; and

Figure 6 is a flow chart of an ESD protection method drawn according to some embodiments of this case.

【Symbol Description】

100: Electrostatic discharge protection device 100A: Input and output pad

110: Diode circuit 120, 130: Clamp circuit

101: Power rail 102: Power rail

103: Power rail D1～D3: Diode

IESD+: Positive electrostatic discharge current IESD-: Negative electrostatic discharge current

P1～P3: path VDD1～VDD2, VSS: voltage

C, C1, C2: capacitor R1, R2: resistor

T1～T5: Transistor Q1～Q3: Transistor

410: Inverter VC: Control signal

600: ESD protection methods S610, S620: Operation

Detailed ways

The following is a detailed description of embodiments with accompanying drawings. However, the embodiments provided are not intended to limit the scope of this case, and the description of structural operations is not intended to limit the order of their execution. Any recombination of components Structure and devices with equal efficacy are all within the scope of this case.

In addition, as used herein, "coupling" or "connecting" may refer to two or more elements that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. Multiple components interact or act with each other.

It is understood that the terms first, second, third, etc. are used herein to describe various elements. But these elements should not be limited by these terms. These terms are limited to identifying single components. Therefore, in the following text, a first element may also be called a second element without departing from the original meaning of the present application.

In this article, the term "circuitry" can generally refer to a single system formed by one or more circuits. The term "circuit" can generally refer to an object that is composed of one or more transistors and/or one or more active and passive components connected in a certain manner to process signals.

As used herein, "about", "approximately" or "approximately" generally means that the error or range of the index value is within about 20%, preferably within about 10%, and more preferably within about 10%. It is within about 5%. Unless explicitly stated in the text, the values mentioned are regarded as approximate values, that is, the error or range expressed by "about", "approximately" or "approximately".

For ease of understanding, similar elements in the following drawings will be designated with the same reference numerals.

FIG. 1 is a schematic diagram of an electrostatic discharge (ESD) protection device 100 drawn according to some embodiments of this case. In some embodiments, the ESD protection device 100 can be applied to an input/output (I/O) interface in a chip or integrated circuit to prevent ESD events from the I/O pad 100A from damaging the chip or Internal components in integrated circuits.

In some embodiments, the ESD protection device 100 includes a diode circuit 110 , a clamp circuit 120 and a clamp circuit 130 . Diode circuit 110 is coupled to power rails 101, 102, and 103. Diode circuit 110 is used to direct ESD current generated by an ESD event on I/O pad 100A to at least one of clamp circuit 120 and/or power rail 101 . For example, the diode circuit 110 includes a plurality of diodes D1 to D3. The anode of diode D1 is coupled to power rail 102 and the cathode of diode D1 is coupled to power rail 101 . The anode of diode D2 is coupled to I/O pad 100A and the cathode of diode D2 is coupled to power rail 102 . The anode of diode D3 is coupled to power rail 103 and the cathode of diode D3 is coupled to I/O pad 100A. When an ESD event occurs, a positive ESD current IESD+ appears on I/O pad 100A. This positive ESD current IESD+ can be directed to power rail 102 and clamp circuit 120 via diode D2 (i.e., path P2), or to power rail 101 (and clamp circuit 130) via diodes D2 and D1 (i.e., path P1) in sequence. . Alternatively, when an ESD event occurs, a negative ESD current IESD- appears on I/O pad 100A. This negative ESD current IESD- may be directed to power rail 103 via diode D3 (ie, path P3).

As shown in Figure 1, power rail 101 receives voltage VDD1, power rail 102 receives voltage VDD2, and power rail 103 receives voltage VSS. In some embodiments, voltage VDD1 is higher than voltage VDD2, and voltage VDD2 is higher than voltage VSS.

The clamp circuit 120 is coupled between the power rail 102 and the power rail 103 , and the clamp circuit 130 is coupled between the power rail 101 and the power rail 103 . In response to an ESD event from I/O pad 100A, at least one of clamp circuit 120 and/or clamp circuit 130 may conduct to provide at least one discharge path. In this way, the positive ESD current IESD+ generated by the ESD event can be discharged through at least one of the clamping circuits 120 or 130 to avoid accidentally damaging the chip or other components in the integrated circuit.

In some embodiments, the discharge capability of the clamp circuit 120 (equivalent to the current driving capability) is higher than the discharge capability of the clamp circuit 130 . In some embodiments, the internal resistance of the clamp circuit 120 is lower than the internal resistance of the clamp circuit 130 . In some embodiments, clamp circuit 120 may be implemented by core transistors, and clamp circuit 130 may be implemented by I/O transistors. Generally speaking, core transistors are used to implement the main circuit parts in the chip, while I/O transistors have relatively high voltage withstand capabilities and are usually used to implement I/O interface circuits. The critical voltage of the core transistor is lower than that of the I/O transistor. Therefore, the clamp circuit 120 can be turned on at a lower operating voltage to provide a discharge path. In addition, the discharge path provided by the clamp circuit 120 implemented using core transistors has a lower internal resistance compared to I/O transistors. In this way, when there is a positive ESD current IESD+, the clamp circuit 120 can be turned on faster to discharge the positive ESD current IESD+ to provide ESD protection. In other words, by providing the clamping circuit 120, the performance of the ESD protection device 100 can be further improved.

In some embodiments, the operating voltage of the clamp circuit 120 (eg, the voltage VDD2) is lower than the operating voltage of the clamp circuit 130 (eg, the voltage VDD1). In some embodiments, voltage VDD2 may be lower than voltage VDD1 and higher than or equal to the nominal core voltage of the core transistor. In some embodiments, the voltage VDD2 is approximately 2/3 times to 3/4 times the voltage VDD1. In some embodiments, voltage VDD2 may be lower than 2/3 times voltage VDD1. The above multiple relationships are used as examples, and this case is not limited to these multiples.

In some related applications, considering the withstand voltage, only I/O transistors are used to implement ESD protection devices. However, circuits implemented using I/O transistors will have higher internal resistance due to higher threshold voltages and/or stacked circuit structures. In this way, the discharge speed of the positive ESD current IESD+ and the negative ESD current IESD- will be too unbalanced, thereby reducing the effectiveness of ESD protection. Compared with the above technology, by setting the clamp circuit 120, the internal resistance of the discharge path can be effectively reduced to further balance the discharge speed of the positive ESD current IESD+ and the negative ESD current IESD-.

In some embodiments, the ESD protection device 100 may further include a capacitor C. Capacitor C is coupled between power rail 102 and power rail 103 to provide an auxiliary path to discharge the positive ESD current IESD+.

FIG. 2 is a schematic diagram of an ESD protection device 100 according to some embodiments of the present invention. Compared to FIG. 1 , in this example, diode D1 is coupled between I/O pad 100A and power rail 101 , wherein the anode of diode D1 is coupled to I/O pad 100A, and the cathode of diode D1 is coupled to Power Rail 101. In other words, in this example, I/O pad 100A may be coupled to power rail 101 without diode D2. In this way, when there is a positive ESD current IESD+, the positive ESD current IESD+ can be directed to the power rail 101 (and the clamp circuit 130) through the diode D1 (ie, the path P1), or can be directly directed through the diode D2 (ie, the path P2). Leading to power rail 102 and clamp circuit 120 .

Figure 3 is a schematic diagram of an ESD protection device 100 drawn according to some embodiments of the present case. Compared with FIG. 1 , in this example, the diode D1 is coupled between the power rail 103 and the power rail 101 , wherein the anode of the diode D1 is coupled to the power rail 103 , and the cathode of the diode D1 is coupled to the power rail 101 . In this way, when there is a positive ESD current IESD+, in addition to the aforementioned path P2, the positive ESD current IESD+ can also be directed to the power rail 101 (and the clamp circuit 101) through the diode D2, the clamp circuit 120 and the diode D1 (ie, the path P1) in sequence. bit circuit 130).

FIG. 4 is a schematic diagram of the clamp circuit 120 drawn according to some embodiments of the present invention. In this example, transistors T1 to T3 are implemented by core transistors.

The clamp circuit 120 includes a resistor R1, a capacitor C1, and transistors T1˜T3. The first terminal of the resistor R1 is coupled to the power rail 102 , and the second terminal of the resistor R1 is coupled to the first terminal of the capacitor C1 . The second terminal of capacitor C1 is coupled to power rail 103 . Transistor T1 and transistor T2 operate as inverter 410 . The first terminal of the transistor T1 is coupled to the power rail 102 , the second terminal of the transistor T1 is coupled to the first terminal of the transistor T2 , and the control terminals of the transistor T1 and the transistor T2 are coupled to the first terminal of the capacitor C1 . The second terminal of transistor T2 is coupled to power rail 103 . Transistor T3 is used to provide a discharge path for the positive ESD current IESD+. The first terminal of the transistor T3 is coupled to the power rail 102 , the second terminal of the transistor T3 is coupled to the power rail 103 , and the control terminal of the transistor T3 is coupled to the second terminal of the transistor T1 .

When there is a positive ESD current IESD+, the first terminal of the capacitor C1 is coupled to the power rail 103 to pull down the potential of the first terminal of the capacitor C1 to a lower voltage VSS. The inverter 410 accordingly outputs the control signal VC having the voltage VDD2. In response to this control signal VC, transistor T3 is turned on to discharge the positive ESD current IESD+.

FIG. 5 is a schematic diagram of the clamp circuit 130 drawn according to some embodiments of the present invention. In this example, transistors Q1-Q3 are implemented by I/O transistors.

The clamp circuit 130 includes a resistor R2, a capacitor C2, and transistors Q1˜Q3. Compared with the clamp circuit 120 , the clamp circuit 130 is coupled to the power rail 101 instead of the power rail 102 , and the remaining circuit structure of the clamp circuit 130 is similar to that of the clamp circuit 120 , so the details are not repeated here.

The above-mentioned circuit arrangement of the clamp circuit 120 and the clamp circuit 130 is used as an example, and the present invention is not limited thereto. For example, in other embodiments, the clamp circuit 120 and the clamp circuit 130 may also be implemented by silicon controlled rectifier circuits. Alternatively, as shown in FIG. 5 , in other embodiments, each of the transistors Q1 to Q3 may also be implemented by multiple stacked core transistors. Taking transistor Q3 as an example, transistor Q3 can be implemented by two or more core transistors T4 and T5, wherein these core transistors T4 and T5 are stacked on each other to operate equivalently as a single transistor Q3.

The number of components (diodes, capacitors, transistors, etc.) in the above-mentioned embodiments is used as an example. Depending on different applications, the number of components in the ESD protection device 100 can be adjusted accordingly.

Figure 6 is a flow chart of an ESD protection method 600 drawn according to some embodiments of this case.

In operation S610, the electrostatic discharge current IESD+ from the input-output pad 100A is directed to at least one of the clamp circuit 120 or the power rail 101 via the diode circuit 110.

In operation S620, the positive ESD current IESD+ is discharged through the clamp circuit 120.

The description of the above-mentioned operations S610 and S620 can refer to the aforementioned embodiments of FIGS. 1 to 5 , and therefore will not be repeated. The multiple operations of the above-mentioned ESD protection method 600 are only examples and are not limited to the sequential execution of the above-mentioned examples. Various operations under the ESD protection method 600 can be appropriately added, replaced, omitted, or performed in a different order without violating the operation mode and scope of each embodiment of the present application.

To sum up, the ESD protection device and ESD protection method provided by some embodiments of this case can provide a set of clamping circuits with lower operating voltage and lower internal resistance to improve the performance of the ESD protection device.

Although this case has been disclosed in the form of implementation, it does not limit this case. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection of this case should be determined accordingly. The scope defined by the appended claims shall prevail.

Claims (19)

1. An electrostatic discharge protection device, characterized by comprising: a first clamping circuit coupled between a first power rail and a second power rail; a second clamp circuit coupled between a third power rail and the second power rail, wherein the first clamp circuit and the second clamp circuit are used to provide different discharge paths for an input and output pad, And the first clamp circuit turns on faster than the second clamp circuit to discharge an electrostatic discharge current from the input and output pad; and a diode circuit for directing the electrostatic discharge current from the input-output pad to at least one of the first clamp circuit or the second clamp circuit, wherein the diode circuit includes a first diode, wherein the The anode of the first diode is coupled to the input-output pad, and the cathode of the first diode is coupled to the first power rail. The electrostatic discharge current is directed to the first clamp via the first diode. bit circuit, The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage higher than the second voltage. 2. The electrostatic discharge protection device according to claim 1, wherein the first clamping circuit is implemented by a plurality of core transistors, and the second clamping circuit is implemented by a plurality of input-output transistors or a plurality of stacked cores. Transistor implementation. 3. The electrostatic discharge protection device according to claim 1, wherein the first voltage is 2/3 to 3/4 times the third voltage. 4. The electrostatic discharge protection device according to claim 1, wherein a discharge capability of the first clamp circuit is higher than a discharge capability of the second clamp circuit. 5. The electrostatic discharge protection device according to claim 1, wherein an internal resistance of the first clamping circuit is lower than an internal resistance of the second clamping circuit. 6. The electrostatic discharge protection device according to any one of claims 1 to 5, characterized in that the diode circuit includes: a second diode, wherein the anode of the second diode is coupled to the first power rail and the cathode of the second diode is coupled to the third power rail; and A third diode, wherein the anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input-output pad. 7. The electrostatic discharge protection device according to claim 6, wherein the electrostatic discharge current is directed to the third power rail via the first diode and the second diode in sequence. 8. The electrostatic discharge protection device according to any one of claims 1 to 5, characterized in that the diode circuit includes: a second diode, wherein the anode of the second diode is coupled to the input-output pad, and the cathode of the second diode is coupled to the third power rail; and A third diode, wherein the anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input-output pad. 9. The electrostatic discharge protection device of claim 8, wherein the electrostatic discharge current is directed to the third power rail via the second diode. 10. The electrostatic discharge protection device according to any one of claims 1 to 5, characterized in that the diode circuit includes: a second diode, wherein the anode of the second diode is coupled to the second power rail, and the cathode of the second diode is coupled to the third power rail; and A third diode, wherein the anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input-output pad. 11. The electrostatic discharge protection device according to claim 10, wherein the electrostatic discharge current is directed to the third diode via the first diode, the first clamping circuit and the second diode in sequence. power rail. 12. An electrostatic discharge protection method, characterized by comprising: directing an electrostatic discharge current from an input-output pad via a diode circuit to at least one of a first clamp circuit or a second clamp circuit; and discharging the electrostatic discharge current through the first clamping circuit, The first clamp circuit is coupled between a second power rail and a third power rail, the second clamp circuit is coupled between a first power rail and the second power rail, and the first The power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the first voltage is higher than the third voltage, and the third voltage is higher than the third voltage. Two voltages, The first clamp circuit and the second clamp circuit are used to provide different discharge paths for the input and output pads, and the first clamp circuit turns on faster than the second clamp circuit to discharge the input from the input and output pads. The electrostatic discharge current of the pad is discharged, Wherein the diode circuit includes a first diode, wherein the anode of the first diode is coupled to the input and output pad, and the cathode of the first diode is coupled to the third power rail, the electrostatic discharge Current is directed to the first clamp circuit via the first diode. 13. The electrostatic discharge protection method according to claim 12, wherein the first clamp circuit is implemented by a plurality of core transistors, and the second clamp circuit is implemented by a plurality of input and output transistors or a plurality of stacked core transistors. implementation. 14. The electrostatic discharge protection method according to claim 12, wherein the third voltage is 2/3 to 3/4 times of the first voltage. 15. The electrostatic discharge protection method according to claim 12, wherein a discharge capability of the first clamp circuit is higher than a discharge capability of the second clamp circuit. 16. The electrostatic discharge protection method according to claim 12, wherein an internal resistance of the first clamping circuit is lower than an internal resistance of the second clamping circuit. 17. The electrostatic discharge protection method according to any one of claims 12 to 16, wherein the diode circuit includes a second diode, and the electrostatic discharge current directed through the diode circuit includes: Directing the electrostatic discharge current to the first power rail via the first diode and the second diode in sequence, wherein the cathode of the first diode is coupled to the third power rail, the anode of the second diode is coupled to the third power rail, and the cathode of the second diode is coupled to the first power rail. 18. The electrostatic discharge protection method according to any one of claims 12 to 16, wherein the diode circuit includes a second diode, and the electrostatic discharge current directed through the diode circuit includes: directing the electrostatic discharge current to the first power rail via the second diode, The cathode of the first diode is coupled to the third power rail, the anode of the second diode is coupled to the input-output pad, and the cathode of the second diode is coupled to the first power rail. rail. 19. The electrostatic discharge protection method according to any one of claims 12 to 16, wherein the diode circuit includes a second diode, and the electrostatic discharge current directed through the diode circuit includes: Directing the electrostatic discharge current to the first power rail via the first diode, the first clamp circuit and the second diode in sequence, The cathode of the first diode is coupled to the third power rail, the anode of the second diode is coupled to the second power rail, and the cathode of the second diode is coupled to the first power rail. power rail.