CN112397499B

CN112397499B - Electrostatic discharge protection device and method

Info

Publication number: CN112397499B
Application number: CN201910737730.2A
Authority: CN
Inventors: 王文泰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2019-08-12
Filing date: 2019-08-12
Publication date: 2023-09-26
Anticipated expiration: 2039-08-12
Also published as: CN112397499A

Abstract

The ESD protection device includes a first clamp circuit, a second clamp circuit, and a diode circuit. The first clamping circuit is coupled between the first power rail and the second power rail. The second clamping circuit is coupled between the third power rail and the second power rail. The diode circuit is configured to direct an electrostatic discharge current from the input-output pad to at least one of the first clamp circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage. Some embodiments of the present invention provide an ESD protection device and method that can provide a set of clamping circuits with lower operating voltage and lower internal resistance to enhance the performance of the ESD protection device.

Description

Electrostatic discharge protection device and method

Technical Field

The present disclosure relates to an esd protection device, and more particularly, to an esd protection device and method using a median voltage.

Background

Generally, integrated circuits are implemented with one or more transistors. As processes develop, the size of the transistor becomes smaller. In order to avoid the damage caused by the excessive voltage stress caused by the electrostatic discharge, an electrostatic discharge protection circuit is generally used to protect the integrated circuit from the electrostatic discharge. In the prior art, considering voltage withstanding, the esd protection circuit is implemented by the input/output transistor. In this way, the internal resistance of the discharge path in the esd protection circuit may be high, thereby reducing the performance of the esd protection circuit.

Disclosure of Invention

In order to solve the above-mentioned problems, some aspects of the present invention provide an esd protection device, which includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to direct an electrostatic discharge current from an input/output pad to at least one of the first clamp circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.

In some embodiments, the first clamp is implemented by a plurality of core transistors and the second clamp is implemented by a plurality of input-output transistors or a plurality of stacked core transistors.

In some embodiments, the first voltage is 2/3 to 3/4 times the third voltage.

In some embodiments, a discharge capacity of the first clamp is higher than a discharge capacity of the second clamp.

In some embodiments, an internal resistance of the first clamping circuit is lower than an internal resistance of the second clamping circuit.

In some embodiments, the diode circuit includes a first diode, a second diode, and a third diode. The anode of the first diode is coupled to the input/output pad, and the cathode of the first diode is coupled to the first power rail. The anode of the second diode is coupled to the first power rail, and the cathode of the second diode is coupled to the third power rail. The anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input/output pad.

In some embodiments, the ESD current is directed to the first clamp circuit via the first diode or to the third power rail via the first diode and the second diode in sequence.

In some embodiments, the diode circuit includes a first diode, a second diode, and a third diode. The anode of the first diode is coupled to the input/output pad, and the cathode of the first diode is coupled to the first power rail. Wherein an anode of the second diode is coupled to the input/output pad, and a cathode of the second diode is coupled to the third power rail. The anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input/output pad.

In some embodiments, the electrostatic discharge current is directed to the first clamp via the first diode or to the third power rail via the second diode.

In some embodiments, the diode circuit includes a first diode, a second diode, and a third diode. The anode of the first diode is coupled to the input/output pad, and the cathode of the first diode is coupled to the first power rail. The anode of the second diode is coupled to the second power rail, and the cathode of the second diode is coupled to the third power rail. The anode of the third diode is coupled to the second power rail, and the cathode of the third diode is coupled to the input/output pad.

In some embodiments, the esd current is directed to the first clamp via the first diode or to the third power rail via the first diode, the first clamp, and the second diode in sequence.

Some aspects of the present disclosure provide an esd protection method, which includes: directing an electrostatic discharge current from an input/output pad to at least one of a first clamp circuit or a first power rail via a diode circuit; and discharging the electrostatic discharge current through the first clamping circuit, wherein the first clamping circuit is coupled between a second power rail and a third power rail, a second clamping circuit is coupled between the first power rail and the second power rail, the first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the first voltage is higher than the third voltage, and the third voltage is higher than the second voltage.

In summary, the esd protection device and the esd protection method according to some embodiments of the present disclosure can provide a set of clamping circuits with lower operating voltage and lower internal resistance to enhance the performance of the esd protection device.

Drawings

Fig. 1 is a schematic diagram of an electrostatic discharge (Electrostatic Discharge, ESD) protection device according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of an ESD protection device according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of an ESD protection device according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a clamp circuit according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a clamp circuit according to some embodiments of the present disclosure; and

fig. 6 is a flow chart of an ESD protection method according to some embodiments of the present disclosure.

[ symbolic description ]

100: the esd protection device 100A: input/output pad

110: diode circuits 120, 130: clamping circuit

101: power rail 102: power supply rail

103: power supply rails D1 to D3: diode

IESD +: positive electrostatic discharge current IESD-: negative electrostatic discharge current

P1 to P3: paths VDD1 to VDD2, VSS: voltage (V)

C. C1, C2: capacitance R1, R2: resistor

T1 to T5: transistors Q1 to Q3: transistor with a high-voltage power supply

410: inverter VC: control signal

600: ESD protection methods S610, S620: operation of

Detailed Description

The following detailed description of the embodiments is provided in connection with the accompanying drawings, but the embodiments are not intended to limit the scope of the disclosure, and the description of the structure operation is not intended to limit the order in which the operations may be performed, as any device with equivalent performance may be produced by a re-combination of elements.

In addition, as used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other.

The terms first, second, third, etc. are used herein to describe various elements and should be understood. But these elements should not be limited by these terms. These terms are only limited to distinguishing between single elements. Accordingly, a first element could also be termed a second element below without departing from the spirit of the present disclosure.

As used herein, the term "circuitry" may refer broadly to a single system formed by one or more circuits (circuits). The term "circuit" may generally refer to an article of manufacture that is connected in a manner by one or more transistors and/or one or more active and passive elements to process signals.

As used herein, "about," "about," or "approximately" generally refers to an error or range of values within about twenty percent, preferably within about ten percent, and more preferably within about five percent. Whenever not explicitly stated herein, reference to values is made to approximate values, i.e., errors or ranges as expressed by "about", "about" or "approximately".

For ease of understanding, like elements in the following figures will be designated with the same reference numerals.

Fig. 1 is a schematic diagram of an electrostatic discharge (Electrostatic Discharge, ESD) protection device 100 according to some embodiments of the present disclosure. In some embodiments, the ESD protection device 100 may be applied to an input/output (I/O) interface in a wafer or integrated circuit to avoid ESD events from the I/O pad (pad) 100A from damaging internal components in the wafer or integrated circuit.

In some embodiments, the ESD protection device 100 includes a diode circuit 110, a clamp circuit 120, and a clamp circuit 130. Diode circuit 110 is coupled to power rails 101, 102, and 103. The diode circuit 110 is configured to direct an ESD current generated by an ESD event on the I/O pad 100A to at least one of the clamp circuit 120 and/or the power rail 101. For example, the diode circuit 110 includes a plurality of diodes D1 to D3. The anode of diode D1 is coupled to power rail 102 and the cathode of diode D1 is coupled to power rail 101. The anode of diode D2 is coupled to I/O pad 100A and the cathode of diode D2 is coupled to power rail 102. The anode of diode D3 is coupled to power rail 103 and the cathode of diode D3 is coupled to I/O pad 100A. When an ESD event occurs, a positive ESD current iesd+ appears on I/O pad 100A. The positive ESD current iesd+ may be directed to the power rail 102 and the clamp circuit 120 via the diode D2 (i.e., path P2), or to the power rail 101 (and the clamp circuit 130) via the diodes D2 and D1 (i.e., path P1) in sequence. Alternatively, when an ESD event occurs, a negative ESD current IESD-appears on I/O pad 100A. This negative ESD current IESD-may be directed to the power rail 103 via diode D3 (i.e., path P3).

As shown in fig. 1, power rail 101 receives voltage VDD1, power rail 102 receives voltage VDD2, and power rail 103 receives voltage VSS. In some embodiments, voltage VDD1 is higher than voltage VDD2, and voltage VDD2 is higher than voltage VSS.

The clamp circuit 120 is coupled between the power rail 102 and the power rail 103, and the clamp circuit 130 is coupled between the power rail 101 and the power rail 103. In response to an ESD event from I/O pad 100A, at least one of clamp 120 and/or clamp 130 is turned on to provide at least one discharge path. In this way, the positive ESD current iesd+ generated by the ESD event can be discharged through at least one of the clamp circuits 120 or 130 to avoid damaging other devices in the chip or integrated circuit by mistake.

In some embodiments, the discharge capability (corresponding to the current driving capability) of the clamp circuit 120 is higher than the discharge capability of the clamp circuit 130. In some embodiments, the internal resistance of the clamp 120 is lower than the internal resistance of the clamp 130. In some embodiments, clamp 120 may be implemented by core (core) transistors and clamp 130 may be implemented by I/O transistors. In general, core transistors are used to implement the main circuit portion in a wafer, while I/O transistors have relatively high voltage withstand capability and are commonly used to implement I/O interface circuits. The threshold voltage of the core transistor is lower than the threshold voltage of the I/O transistor. Thus, the clamp circuit 120 may be turned on at a lower operating voltage to provide a discharge path. In addition, the discharge path provided by the clamp circuit 120 implemented using core transistors has a lower internal resistance than the I/O transistors. In this way, when the positive ESD current iesd+ exists, the clamp circuit 120 can be turned on more quickly to discharge the positive ESD current iesd+ to provide ESD protection. In other words, by providing the clamp circuit 120, the performance of the esd protection device 100 can be further improved.

In some embodiments, the operating voltage of the clamp circuit 120 (e.g., the voltage VDD 2) is lower than the operating voltage of the clamp circuit 130 (e.g., the voltage VDD 1). In some embodiments, the voltage VDD2 may be lower than the voltage VDD1 and higher than or equal to a nominal core (nominal core) voltage of the core transistor. In some embodiments, the voltage VDD2 is about 2/3 times to about 3/4 times the voltage VDD1. In some embodiments, the voltage VDD2 may be less than 2/3 times the voltage VDD1. The above multiple relationships are used for illustration, and the present disclosure is not limited to these multiple relationships.

In some related applications, the ESD protection device is implemented using only I/O transistors in view of withstand voltage. However, circuits implemented using I/O transistors may have higher internal resistances due to higher threshold voltages and/or stacked circuit structures. In this way, the discharge speeds of the positive and negative ESD currents iesd+ and IESD-are excessively unbalanced, thereby reducing the ESD protection performance. Compared to the above-mentioned technique, by providing the clamp circuit 120, the internal resistance of the discharge path can be effectively reduced to further balance the discharge speeds of the positive ESD current iesd+ and the negative ESD current IESD-.

In some embodiments, the ESD protection device 100 may further comprise a capacitor C. The capacitor C is coupled between the power rail 102 and the power rail 103 to provide an auxiliary path for discharging the positive ESD current iesd+.

Fig. 2 is a schematic diagram of an ESD protection device 100 according to some embodiments of the present disclosure. In comparison to fig. 1, in this example, a diode D1 is coupled between the I/O pad 100A and the power rail 101, wherein an anode of the diode D1 is coupled to the I/O pad 100A and a cathode of the diode D1 is coupled to the power rail 101. In other words, in this example, the I/O pad 100A may be coupled to the power rail 101 without the diode D2. Thus, when a positive ESD current iesd+ is present, the positive ESD current iesd+ may be directed to the power rail 101 (and clamp 130) via diode D1 (i.e., path P1), or may be directed to the power rail 102 and clamp 120 via diode D2 (i.e., path P2).

Fig. 3 is a schematic diagram of an ESD protection device 100 according to some embodiments of the present disclosure. In comparison to fig. 1, in this example, the diode D1 is coupled between the power rail 103 and the power rail 101, wherein an anode of the diode D1 is coupled to the power rail 103 and a cathode of the diode D1 is coupled to the power rail 101. Thus, when the positive ESD current iesd+ exists, the positive ESD current iesd+ can be further directed to the power rail 101 (and the clamp 130) through the diode D2, the clamp 120 and the diode D1 (i.e. the path P1) in order, in addition to the path P2.

Fig. 4 is a schematic diagram of a clamp circuit 120 according to some embodiments of the present disclosure. In this example, the transistors T1 to T3 are implemented by core transistors.

The clamp circuit 120 includes a resistor R1, a capacitor C1, and transistors T1 to T3. The first terminal of the resistor R1 is coupled to the power rail 102, and the second terminal of the resistor R1 is coupled to the first terminal of the capacitor C1. A second terminal of the capacitor C1 is coupled to the power rail 103. The transistors T1 and T2 operate as an inverter 410. The first terminal of the transistor T1 is coupled to the power rail 102, the second terminal of the transistor T1 is coupled to the first terminal of the transistor T2, and the control terminals of the transistor T1 and the transistor T2 are coupled to the first terminal of the capacitor C1. A second terminal of transistor T2 is coupled to power rail 103. The transistor T3 is used to provide a discharge path for the positive ESD current iesd+. The first terminal of the transistor T3 is coupled to the power rail 102, the second terminal of the transistor T3 is coupled to the power rail 103, and the control terminal of the transistor T3 is coupled to the second terminal of the transistor T1.

When a positive ESD current iesd+ is present, the first terminal of the capacitor C1 is coupled to the power rail 103 to pull down the potential of the first terminal of the capacitor C1 to the lower voltage VSS. The inverter 410 outputs a control signal VC having a voltage VDD2 accordingly. In response to this control signal VC, transistor T3 is turned on to discharge the positive ESD current iesd+.

Fig. 5 is a schematic diagram of a clamp circuit 130 according to some embodiments of the present disclosure. In this example, the transistors Q1 to Q3 are implemented by I/O transistors.

The clamp circuit 130 includes a resistor R2, a capacitor C2, and transistors Q1 to Q3. Compared to the clamp circuit 120, the clamp circuit 130 is coupled to the power rail 101 instead of the power rail 102, and the rest of the circuit structure of the clamp circuit 130 is similar to the circuit structure of the clamp circuit 120, so the description is not repeated here.

The above circuit arrangement of the clamping circuits 120 and 130 is used for example, and the disclosure is not limited thereto. For example, in other embodiments, the clamping circuits 120 and 130 may also be implemented by scr circuits. Alternatively, as shown in FIG. 5, in other embodiments, each of the transistors Q1-Q3 may also be implemented by a plurality of stacked core transistors. Taking the transistor Q3 as an example, the transistor Q3 may be implemented by two or more core transistors T4 and T5, wherein the core transistors T4 and T5 are stacked on each other to operate as a single transistor Q3.

The number of elements (diodes, capacitors, transistors, etc.) in each of the above embodiments is for example, and the number of elements in ESD protection device 100 may be adjusted accordingly depending on the application.

Fig. 6 is a flow chart of an ESD protection method 600 according to some embodiments of the present disclosure.

In operation S610, the electrostatic discharge current iesd+ from the input/output pad 100A is directed to at least one of the clamp 120 or the power rail 101 via the diode circuit 110.

In operation S620, the positive ESD current iesd+ is discharged through the clamp circuit 120.

The descriptions of the operations S610 and S620 may refer to the embodiments of fig. 1 to 5, so that the descriptions are not repeated. The various operations of ESD protection method 600 described above are merely examples and are not limited to sequential execution of the examples described above. The various operations under the ESD protection method 600 may be added, replaced, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the present disclosure.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present invention, and the scope of the present invention is accordingly defined by the appended claims.

Claims

1. An electrostatic discharge protection device, comprising:

a first clamping circuit coupled between a first power rail and a second power rail;

a second clamping circuit coupled between a third power rail and the second power rail, wherein the first clamping circuit and the second clamping circuit are configured to provide different discharge paths for an input/output pad, and the first clamping circuit is turned on faster than the second clamping circuit to discharge an electrostatic discharge current from the input/output pad; and

a diode circuit for directing the ESD current from the input/output pad to at least one of the first clamp circuit or the second clamp circuit, wherein the diode circuit comprises a first diode, wherein an anode of the first diode is coupled to the input/output pad, and a cathode of the first diode is coupled to the first power rail, the ESD current is directed to the first clamp circuit via the first diode,

the first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.

2. The esd protection device of claim 1, wherein the first clamp is implemented by a plurality of core transistors and the second clamp is implemented by a plurality of input-output transistors or by a plurality of stacked core transistors.

3. The ESD protection device of claim 1 wherein the first voltage is 2/3-3/4 times the third voltage.

4. The esd protection device of claim 1 wherein a discharge capacity of the first clamp is higher than a discharge capacity of the second clamp.

5. The esd protection device of claim 1 wherein an internal resistance of the first clamp is lower than an internal resistance of the second clamp.

6. The esd protection device of any one of claims 1 to 5, wherein the diode circuit comprises:

a second diode, wherein an anode of the second diode is coupled to the first power rail, and a cathode of the second diode is coupled to the third power rail; and

and a third diode, wherein an anode of the third diode is coupled to the second power rail, and a cathode of the third diode is coupled to the input/output pad.

7. The esd protection device of claim 6 wherein the esd current is directed to the third power rail via the first diode and the second diode in sequence.

8. The esd protection device of any one of claims 1 to 5, wherein the diode circuit comprises:

a second diode, wherein an anode of the second diode is coupled to the input/output pad, and a cathode of the second diode is coupled to the third power rail; and

9. The esd protection device of claim 8 wherein the esd current is directed to the third power rail via the second diode.

10. The esd protection device of any one of claims 1 to 5, wherein the diode circuit comprises:

a second diode, wherein an anode of the second diode is coupled to the second power rail, and a cathode of the second diode is coupled to the third power rail; and

11. The esd protection device of claim 10 wherein the esd current is directed to the third power rail sequentially through the first diode, the first clamp and the second diode.

12. An electrostatic discharge protection method, comprising:

directing an electrostatic discharge current from an input/output pad to at least one of a first clamp circuit or a second clamp circuit via a diode circuit; and

discharging the electrostatic discharge current via the first clamping circuit,

wherein the first clamping circuit is coupled between a second power rail and a third power rail, the second clamping circuit is coupled between a first power rail and the second power rail, the first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the first voltage is higher than the third voltage, and the third voltage is higher than the second voltage,

wherein the first clamping circuit and the second clamping circuit are used for providing different discharging paths of the input and output pad, and the first clamping circuit is faster conducted than the second clamping circuit to discharge the electrostatic discharge current from the input and output pad,

the diode circuit comprises a first diode, wherein an anode of the first diode is coupled to the input/output pad, and a cathode of the first diode is coupled to the third power rail, and the electrostatic discharge current is guided to the first clamping circuit through the first diode.

13. The esd protection method of claim 12 wherein the first clamp is implemented with a plurality of core transistors and the second clamp is implemented with a plurality of input-output transistors or a plurality of stacked core transistors.

14. The method of claim 12, wherein the third voltage is 2/3-3/4 times the first voltage.

15. The method of claim 12, wherein a discharging capability of the first clamping circuit is higher than a discharging capability of the second clamping circuit.

16. The method of claim 12, wherein an internal resistance of the first clamping circuit is lower than an internal resistance of the second clamping circuit.

17. The esd protection method according to any one of claims 12 to 16, wherein the diode circuit comprises a second diode, and directing the esd current through the diode circuit comprises:

the ESD current is directed to the first power rail through the first diode and the second diode in sequence,

wherein the cathode of the first diode is coupled to the third power rail, the anode of the second diode is coupled to the third power rail, and the cathode of the second diode is coupled to the first power rail.

18. The esd protection method according to any one of claims 12 to 16, wherein the diode circuit comprises a second diode, and directing the esd current through the diode circuit comprises:

directing the electrostatic discharge current to the first power rail via the second diode,

wherein the cathode of the first diode is coupled to the third power rail, the anode of the second diode is coupled to the input/output pad, and the cathode of the second diode is coupled to the first power rail.

19. The esd protection method according to any one of claims 12 to 16, wherein the diode circuit comprises a second diode, and directing the esd current through the diode circuit comprises:

the ESD current is directed to the first power rail via the first diode, the first clamp circuit and the second diode in sequence,

wherein the cathode of the first diode is coupled to the third power rail, the anode of the second diode is coupled to the second power rail, and the cathode of the second diode is coupled to the first power rail.