CN211350639U

CN211350639U - Wafer

Info

Publication number: CN211350639U
Application number: CN201922416043.9U
Authority: CN
Inventors: 姜域; 殷昌荣; 汪秀全; 袁鹏
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-08-25
Anticipated expiration: 2029-12-27

Abstract

The utility model provides a wafer, which comprises a plurality of exposure areas, wherein at least one exposure area comprises a plurality of functional areas arranged in a matrix, a first scribing channel is arranged between the functional areas in adjacent rows, and a second scribing channel is arranged between the functional areas in adjacent rows; wherein, a plurality of the functional areas are internally provided with a test circuit. Because the first scribing channel is arranged between the functional areas of the adjacent rows and the second scribing channel is arranged between the functional areas of the adjacent columns, the first scribing channel and the second scribing channel can be cut, and because the test circuit is not arranged in the scribing channel, the problems of blade blunting, chip edge collapse and the like caused by cutting the test circuit can be avoided.

Description

Wafer

Technical Field

The utility model relates to a semiconductor manufacturing technology field, more specifically say, relate to a wafer.

Background

In the chip packaging process, a mechanical cutting blade (i.e., a dicing blade) is mainly used to cut streets between chips, so as to separate one chip on a wafer. However, when dicing streets are formed in any exposure area of the wafer by mechanical dicing, because the streets have test circuits for self-test requirements added in the wafer processing process, and the test circuits are generally of a ductile metal (e.g., Al/Cu) structure, when the streets are diced by mechanical dicing, the problems of blade dulling, chip edge chipping and the like can be caused, and chip reliability and electrical performance can be directly affected by the chip edge chipping.

To solve this problem, the methods mainly adopted in the prior art include the following two methods: 1. the scribing channel is cut by using a laser grooving process, however, the process cost is high, and the width of the scribing channel is wide and generally not less than 65 micrometers (micrometers) under the limitation of the size of a laser hot melting area, so that the requirements of practical application cannot be well met; 2. however, this method cannot completely avoid the problem of chip chipping due to dicing of the test circuit, and a large amount of wafer effective area is lost for a small-sized chip.

SUMMERY OF THE UTILITY MODEL

In view of this, the present invention provides a wafer.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

a wafer comprises a plurality of exposure areas, at least one exposure area comprises a plurality of functional areas arranged in a matrix, a first scribing channel is arranged between the functional areas in adjacent rows, and a second scribing channel is arranged between the functional areas in adjacent columns;

wherein, a plurality of the functional areas are internally provided with a test circuit.

Optionally, the functional region includes a first functional region and a second functional region, a chip is disposed in the first functional region, and a test circuit is disposed in the second functional region.

Optionally, a plurality of the first functional regions are arranged in a matrix; a plurality of the second functional regions are located on at least one side of the array of the first functional regions.

Optionally, a plurality of said second functional areas are located in at least one column on one side of said array of first functional areas.

Optionally, a plurality of said second functional areas are located in at least one row of one side of said array of first functional areas.

Optionally, a plurality of the second functional regions are located in at least one row of one side and at least one column of an adjacent side of the array of the first functional regions.

Optionally, the first functional region and the second functional region have a spacing of greater than 10 μm.

Optionally, the width of the first scribe lane is less than or equal to 60 μm, and/or the width of the second scribe lane is less than or equal to 60 μm.

Optionally, the first functional area and the second functional area are equal in size.

Compared with the prior art, the utility model provides a technical scheme has following advantage:

the utility model provides a wafer, every exposure area is equipped with test circuit including being a plurality of functional areas of matrix arrangement in the functional area, because first scribing way has between the functional area of adjacent line, second scribing way has between the functional area of adjacent row, consequently, can cut first scribing way and second scribing way, and, because test circuit no longer sets up in the scribing way, consequently, can not appear leading to blade dulling and chip edge to appear collapsing the scheduling problem because of cutting test circuit yet.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a wafer according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a wafer exposure area according to an embodiment of the present invention;

fig. 3 is a diagram illustrating a position relationship between a first functional area and a second functional area according to an embodiment of the present invention;

fig. 4 is a diagram illustrating a positional relationship between a first functional area and a second functional area according to another embodiment of the present invention;

fig. 5 is a diagram illustrating a position relationship between a first functional area and a second functional area according to another embodiment of the present invention;

fig. 6 is a diagram illustrating a position relationship between a first functional area and a second functional area according to another embodiment of the present invention.

Detailed Description

Above is the core thought of the utility model, for making the above-mentioned purpose, characteristic and advantage of the utility model can be more obvious understandable, will combine below in the embodiment of the utility model the drawing, to technical scheme in the embodiment of the utility model is clear, completely describe, obviously, the embodiment that describes is only a partial embodiment of the utility model, rather than whole embodiment. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The inventor finds out through analysis that in the existing scheme, the dominant idea is to arrange the test circuit pattern in the scribe lane, and accordingly, in the mechanical cutting mode, the width of the scribe lane is intentionally increased to avoid touching the test circuit during the cutting process, while in the laser cutting mode, the width of the scribe lane also needs to be set to a larger value due to process limitations, and both of the two modes result in the loss of the effective area of the wafer, and especially when the chip size is smaller, the loss is more obvious. The inventors inventively placed the test circuits in the chip area and not in the scribe lanes, thereby proposing the following embodiments.

One embodiment of the present invention provides a wafer, as shown in fig. 1, including a plurality of exposure areas S0 to Sn, where n is an integer greater than 1. It should be noted that, since the wafer is circular in shape, the exposure area includes a rectangular exposure area such as S1 and a non-rectangular exposure area such as S0, and the non-rectangular exposure area such as S0 is located in the edge area of the wafer.

Fig. 2 shows a schematic structural diagram of exposure areas of a wafer, and as shown in fig. 2, at least one exposure area includes a plurality of functional areas C, the functional areas C are arranged in a matrix, a first scribe lane P1 is provided between functional areas C in adjacent rows, a second scribe lane P2 is provided between functional areas C in adjacent columns, and it is understood that there are a plurality of first scribe lanes P1 and a plurality of second scribe lanes P2.

Wherein, be provided with test circuit in a plurality of functional areas C. Since the test circuit is no longer disposed in the scribe lanes, i.e., the first scribe lane P1 and the second scribe lane P2, the problems of blade dulling and chip edge chipping caused by cutting the test circuit do not occur.

Optionally, a chip, a test circuit, or both a chip and a test circuit are disposed in each functional region C. It should be noted that, since the non-rectangular exposed area such as the area near the edge of the wafer in S0 cannot be completely exposed, the area near the edge of the wafer in the partial non-rectangular exposed area may not have the functional area C.

Further, as shown in fig. 3, the functional region C includes a first functional region C1 and a second functional region C2, a chip is disposed in the first functional region C1, and a test circuit is disposed in the second functional region C2. Taking exposure area S6 as an example, the exposure area S6 has a plurality of functional areas C, and any one of the functional areas C may be first functional area C1 or second functional area C2. Preferably, the first functional zone C1 and the second functional zone C2 are equal in size.

In the embodiment of the present invention, each functional area is only illustrated as a rectangular area, but not limited thereto, and in other embodiments, the functional area may also be a circular area, a triangular area, or a trapezoidal area. It should be noted that the test circuits are circuits added for specific test purposes during wafer processing, and in an alternative, the test circuits are circuits added for monitoring the stability of the wafer manufacturing process and the electrical integrity after the wafer processing is completed.

The embodiment of the utility model provides an in, can separate the chip through cutting first scribing way P1 and second scribing way P2, because the utility model discloses in the embodiment abandon the industry field general knowledge of setting test circuit in the scribing way, promptly the utility model discloses well test circuit no longer sets up in the scribing way between the chip, but sets up in the exposure area, especially the edge in exposure area. Therefore, when cutting is carried out along the scribing way, namely along the first scribing way P1 and the second scribing way P2, smooth cutting can be realized without increasing the width of the scribing way, the problems of blade blunting and chip edge breakage and the like caused by cutting of a test circuit can be avoided, and the scribing quality and the packaging yield can be improved. And, the embodiment of the utility model provides an in still adopt mechanical cutting technology to cut, compare with laser cutting, the cost is lower.

In the embodiment of the present invention, the first functional region C1 provided with the chip and the second functional region C2 provided with the test circuit may be arranged alternately, as shown in fig. 4, the second functional region C2 is located in partial row and/or partial column of the functional region C array, the first functional region C1 is located in other rows and/or other columns of the functional region C array, or all the second functional regions C2 are located on one side of all the first functional regions C1, optionally, the plurality of first functional regions C1 are arranged in a matrix, and the plurality of second functional regions C2 are located on at least one side of the array of the first functional regions C1.

Further alternatively, the plurality of second functional regions C2 are located in at least one row at one side and at least one column at an adjacent side of the array of the first functional region C1, as shown in fig. 3, the plurality of second functional regions C2 are located in one row at one side and one column at an adjacent side of the array of the first functional region C1.

Of course, the present invention is not limited thereto, and in other embodiments, the plurality of first functional regions C1 are arranged in a matrix; the plurality of second functional regions C2 are located in at least one column at one side of the array of the first functional region C1, and as shown in fig. 5, the plurality of second functional regions C2 are located in two columns at one side of the array of the first functional region C1.

Alternatively, the plurality of second functional regions are located in at least one row on one side of the array of the first functional regions, and as shown in fig. 6, the plurality of second functional regions are located in two rows on one side of the array of the first functional regions.

In a specific embodiment, the positions of the first functional region C1 and the second functional region C2 may be set according to needs, and are not described herein again.

It should be noted that, when the second functional region C2 is located on at least one side of the array of the first functional region C1, in order to further increase the available area of the wafer, the distance between the first functional region C1 and the second functional region C2 may be reduced, and considering the dicing process, the distance between the first functional region C1 and the second functional region C2 is preferably greater than 10 μm. At this time, when the dicing street between the first functional region C1 and the second functional region C2 is cut, even if the test circuit is broken by hitting the test circuit in the second functional region C2, the structure of the chip is not affected.

It should be noted that, in the embodiment of the present invention, after the second functional area C2 is disposed on one side of the array of the first functional area C1, the connection between the test circuit and the corresponding chip structure can be realized through the via hole and the metal lead, so as to perform the test through the test circuit and the chip.

In the embodiment of the present invention, the test circuit is placed in the chip region, and is no longer placed in the scribe lane, so that the width D of the scribe lane can be relatively reduced, that is, the width D1 of the first scribe lane P1 and the width D2 of the second scribe lane P2 are reduced, for example, compared with the conventional method, the widths D1 and D2 of the scribe lane can be reduced from the original 80 μm or more to 60 μm or less, including the endpoint value. Wherein, D1 may be equal to D2, or may not be equal to D2. That is, the width D of the scribe lane in the embodiment of the present invention may be less than or equal to 60 μm, that is, the width D1 of the first scribe lane P1 is less than or equal to 60 μm, and/or the width D2 of the second scribe lane P2 is less than or equal to 60 μm, so that the available area on the wafer is increased after the area of the edge region where the test circuit is placed is deducted. Based on this, the number of resulting chips can be relatively increased for the same size wafer.

If a wafer is 8 inches in size and a chip is 1mm by 1mm in size, the width of a scribe lane is 80 μm if there is a 60 μm wide test circuit in the previous scribe lane. When the test circuit is placed in the chip area, a scribe lane width of 60 μm may be used. After one circle of chip area containing the test circuit is deducted from the edge of the exposure area, the number of chips of the whole wafer can be increased by 2%. If a scribe lane with a width of 50 μm is used, the number of chips can be increased by about 4.5% at this time, and the smaller the chip size, the larger the increase ratio.

The utility model provides a wafer, at least one exposure area of wafer is including being a plurality of functional areas of matrix arrangement, chip or test circuit have in the functional area, because first scribing way has between the functional area of adjacent row, second scribing way has between the functional area of adjacent row, consequently, can cut and come to separate the chip to first scribing way and second scribing way, and, because test circuit no longer sets up in the scribing way between the chip, consequently, can not appear leading to blade blunting and chip edge to appear collapsing the scheduling problem because of cutting test circuit yet.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer is characterized by comprising a plurality of exposure areas, wherein at least one exposure area comprises a plurality of functional areas arranged in a matrix, a first scribing channel is arranged between the functional areas in adjacent rows, and a second scribing channel is arranged between the functional areas in adjacent columns;

2. The wafer of claim 1, wherein the functional regions comprise a first functional region and a second functional region, the first functional region having a chip disposed therein, and the second functional region having a test circuit disposed therein.

3. The wafer of claim 2, wherein the first functional regions are arranged in a matrix; a plurality of the second functional regions are located on at least one side of the array of the first functional regions.

4. The wafer of claim 3, wherein a plurality of the second functional regions are located in at least one column on one side of the array of the first functional regions.

5. The wafer of claim 3, wherein a plurality of the second functional regions are located in at least one row on one side of the array of the first functional regions.

6. The wafer of claim 3, wherein a plurality of the second functional regions are located in at least one row on one side and at least one column on an adjacent side of the array of the first functional regions.

7. The wafer of claim 3, wherein a pitch between the first functional region and the second functional region is greater than 10 μm.

8. The wafer of claim 1, wherein the width of the first scribe lane is less than or equal to 60 μ ι η, and/or the width of the second scribe lane is less than or equal to 60 μ ι η.

9. The wafer of claim 2, wherein the first functional area and the second functional area are equal in size.