CN211263591U - Output current sampling and conditioning circuit - Google Patents
Output current sampling and conditioning circuit Download PDFInfo
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- CN211263591U CN211263591U CN201922045660.2U CN201922045660U CN211263591U CN 211263591 U CN211263591 U CN 211263591U CN 201922045660 U CN201922045660 U CN 201922045660U CN 211263591 U CN211263591 U CN 211263591U
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Abstract
The utility model discloses an output current sampling and conditioning circuit, including operational amplifier U4B, the in-phase input end of operational amplifier U4B respectively with electric capacity C39 one end, resistance R108 one end, resistance R103 one end electric connection; the inverting input terminal of the operational amplifier U4B is electrically connected to one end of a resistor R102 and one end of a resistor R113, respectively, wherein one end of the resistor R102 is electrically connected to the other end of the resistor R113 through a capacitor C46, wherein the other end of the resistor R102 is electrically connected to one end of a resistor R99, wherein the other end of the resistor R113 is electrically connected to the output terminal of the operational amplifier U4B, and wherein the output terminal of the operational amplifier U4B is electrically connected to the analog-to-digital converter; the utility model discloses current load current sampling and conditioning circuit have been solved and have been not suitable for in the low voltage electric wire netting to the technical problem of high drift.
Description
Technical Field
The utility model relates to an output current sampling and conditioning circuit.
Background
The sampling circuit has an analog signal input, a control signal input, and an analog signal output. The circuit functions to receive an input voltage at a given time and hold the voltage at the output until the next sampling begins. The sampling circuit is usually composed of an analog switch, a holding capacitor and a non-inverting circuit with a unity gain of 1. The sampling operates in one of two states, a sample state and a hold state. In the sampling state, the switch is turned on, which tracks the level change of the analog input signal as fast as possible until the arrival of the hold signal; in the hold state, the switch is opened and the tracking process is stopped, which keeps the instantaneous value of the input signal until the switch is opened.
Signal conditioning simply means converting various signals detected by the sensing element into standard signals. The signal conditioning in the digital input channel mainly comprises jitter elimination, filtering, protection, level conversion, isolation and the like. Signal conditioning converts your data acquisition device into a complete set of data acquisition systems by helping you connect directly to a wide range of sensors and signal types (from thermocouples to high voltage signals). The critical signal conditioning techniques can improve the overall performance and accuracy of the data acquisition system by a factor of 10. The signal conditioning is simple to say that the signal to be measured is converted into a standard signal which can be identified by the acquisition equipment through operations such as amplification, filtering and the like. It uses internal circuits (such as filter, converter, amplifier, etc. …) to change the input signal type and output it. Since some industrial signals are high voltage, overcurrent, surge, etc., which cannot be correctly identified by the system, they must be conditioned for cleaning.
The existing output current sampling and conditioning circuit is not suitable for a low-voltage power grid and has high drift.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is that current output current sampling and conditioning circuit are not suitable for in the low voltage electric wire netting to the technical problem of high drift provides an output current sampling and conditioning circuit.
In order to solve the technical problem, the utility model provides a following technical scheme:
an output current sampling and conditioning circuit comprises an operational amplifier U4B, wherein a non-inverting input end of the operational amplifier U4B is electrically connected with one end of a capacitor C39, one end of a resistor R108 and one end of a resistor R103 respectively; the inverting input terminal of the operational amplifier U4B is electrically connected to one end of a resistor R102 and one end of a resistor R113, respectively, wherein one end of the resistor R102 is electrically connected to the other end of the resistor R113 through a capacitor C46, wherein the other end of the resistor R102 is electrically connected to one end of a resistor R99, wherein the other end of the resistor R113 is electrically connected to the output terminal of the operational amplifier U4B, and wherein the output terminal of the operational amplifier U4B is electrically connected to the analog-to-digital converter.
Preferably, the positive power terminal of the operational amplifier U4B is connected to a voltage of-8V, and the negative power terminal of the operational amplifier U4B is connected to a voltage of + 8V.
Preferably, the other end of the capacitor C39 and the other end of the resistor R108 are both grounded.
Preferably, the other end of the resistor R99 is grounded.
The utility model discloses the beneficial effect who reaches is:
the utility model adopts HAS 50-S/SP50 Hall current sensor for sampling, the secondary side sampling is converted by current and voltage, output to AD7865AS-1 for analog-to-digital conversion, and sent to DSP (TMS320F28335) controller for comparison with the collected harmonic; the utility model is suitable for low voltage power grid and has low drift; the utility model discloses the direct current of sampling low voltage electric wire netting carries out the difference and enlargies and take care of back output.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention.
In the drawings:
fig. 1 is a circuit diagram of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are presented herein only to illustrate and explain the present invention, and not to limit the present invention.
As shown in fig. 1, an output current sampling and conditioning circuit includes an operational amplifier U4B, wherein a non-inverting input terminal of the operational amplifier U4B is electrically connected to one end of a capacitor C39, one end of a resistor R108, and one end of a resistor R103, respectively, and the other end of the capacitor C39 and the other end of the resistor R108 are both grounded. The inverting input terminal of the operational amplifier U4B is electrically connected to one end of a resistor R102 and one end of a resistor R113, respectively, wherein one end of the resistor R102 is electrically connected to the other end of the resistor R113 through a capacitor C46, wherein the other end of the resistor R102 is electrically connected to one end of a resistor R99, wherein the other end of the resistor R113 is electrically connected to the output terminal of the operational amplifier U4B, wherein the other end of the resistor R99 is grounded, and wherein the output terminal of the operational amplifier U4B is electrically connected to the analog-to-digital converter. The positive power supply end of the operational amplifier U4B is connected with-8V voltage, and the negative power supply end of the operational amplifier U4B is connected with +8V voltage.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. An output current sampling and conditioning circuit, comprising an operational amplifier U4B, characterized in that: the non-inverting input end of the operational amplifier U4B is electrically connected with one end of the capacitor C39, one end of the resistor R108 and one end of the resistor R103 respectively; the inverting input terminal of the operational amplifier U4B is electrically connected to one end of a resistor R102 and one end of a resistor R113, respectively, wherein one end of the resistor R102 is electrically connected to the other end of the resistor R113 through a capacitor C46, wherein the other end of the resistor R102 is electrically connected to one end of a resistor R99, wherein the other end of the resistor R113 is electrically connected to the output terminal of the operational amplifier U4B, and wherein the output terminal of the operational amplifier U4B is electrically connected to the analog-to-digital converter.
2. The output current sampling and conditioning circuit of claim 1, wherein: the positive power supply end of the operational amplifier U4B is connected with-8V voltage, and the negative power supply end of the operational amplifier U4B is connected with +8V voltage.
3. The output current sampling and conditioning circuit of claim 1, wherein: the other end of the capacitor C39 and the other end of the resistor R108 are both grounded.
4. The output current sampling and conditioning circuit of claim 1, wherein: the other end of the resistor R99 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922045660.2U CN211263591U (en) | 2019-11-25 | 2019-11-25 | Output current sampling and conditioning circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922045660.2U CN211263591U (en) | 2019-11-25 | 2019-11-25 | Output current sampling and conditioning circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211263591U true CN211263591U (en) | 2020-08-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922045660.2U Active CN211263591U (en) | 2019-11-25 | 2019-11-25 | Output current sampling and conditioning circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211263591U (en) |
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2019
- 2019-11-25 CN CN201922045660.2U patent/CN211263591U/en active Active
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