CN211239814U - Analog switch circuit based on mainboard design - Google Patents

Abstract

The utility model discloses an analog switch circuit based on mainboard design, which comprises a power input end, a reset input end, a pulse output end, a starting unit and a reset unit; the starting unit comprises a tristate gate U1 and a pull-up resistor R3; the tri-state gate U1 is connected with the power supply input end, the tri-state gate U1 is connected with the reset input end, and the tri-state gate U1 is connected with the pulse output end; the pull-up resistor R3 is connected between the tristate gate U1 and the pulse output end; the reset unit comprises an NMOS tube Q1, an NMOS tube Q2 and a delay circuit; the drain electrode of the NMOS tube Q1 is connected with the tristate gate U1, the source electrode of the NMOS tube Q1 is grounded, and the grid electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2; the source electrode of the NMOS tube Q2 is grounded; two ends of the delay circuit are respectively connected with the grid electrode of the NMOS tube Q2 and the reset input end. The analog switch circuit based on the mainboard design has high reliability, economy and working convenience.

Description

Analog switch circuit based on mainboard design

Technical Field

The utility model relates to a mainboard switch circuit technical field specifically is an analog switch circuit based on mainboard design.

Background

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

When the circuit main board is used, after the circuit main board is electrified, the main board is triggered to be started through a low pulse signal with the pulse width of dozens of milliseconds. In the prior art, a part of the main board realizes the triggering of the low-level pulse signal through a manual switch key, and for the main board needing to be automatically started, the low-level pulse signal is triggered by the programming of software such as an EC/MCU and the like and the addition of hardware collocation, so that the action of a virtual switch is realized, and the main board is started. However, the low-level pulse signal is triggered by a manual switch key, the problem of low timeliness of the mainboard starting mode is caused by the manual triggering mode, the low-level pulse signal is triggered by software programming and hardware matching, the use of software such as an EC/MCU is needed, more hardware matching is needed, a high level and a low level are input at the output end of the mainboard, the mainboard is powered on and the starting is triggered, and the problems of complicated working method steps and low economy of the circuit of the mainboard starting mode and the working method of the circuit are caused.

It should be noted that the above background description is only for the sake of clarity and complete description of the technical solutions of the present invention, and is set forth for facilitating understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present invention.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the above problem, the utility model provides an analog switch circuit based on mainboard design, based on power input end, reset input end, the pulse output end, the analog switch circuit that start unit and reset unit constitute, under the pure hardware collocation that does not adopt software programming, only at power input end and the high level of input that resets, make mainboard CPU acquire a low level pulse, realize mainboard CPU's last electricity and start, improved analog switch circuit reliability and economic nature based on mainboard design.

In order to achieve the above object, the utility model provides an analog switch circuit based on mainboard design, which comprises a power input end, a reset input end, a pulse output end, a starting unit and a reset unit; the starting unit comprises a tristate gate U1 and a pull-up resistor R3; the tri-state gate U1 is connected with the power supply input end, the enable end of the tri-state gate U1 is connected with the reset input end, and the output end of the tri-state gate U1 is connected with the pulse output end; the pull-up resistor R3 is connected between the output end of the tri-state gate U1 and the pulse output end; the reset unit comprises an NMOS transistor Q1, an NMOS transistor Q2 and a delay circuit; the drain of the NMOS transistor Q1 is connected with the input end of the tristate gate U1, the source of the NMOS transistor Q1 is grounded, and the gate of the NMOS transistor Q1 is connected with the drain of the NMOS transistor Q2; the source electrode of the NMOS tube Q2 is grounded; two ends of the delay circuit are respectively connected with the grid electrode of the NMOS transistor Q2 and the reset input end

Based on the structure, the pulse output end outputs high level under the high resistance state of the tristate gate U1, outputs low level when the NMOS tube Q1 is conducted and outputs high level when the NMOS tube Q2 is conducted through the analog switch circuit formed by the tristate gate U1, the NMOS tube Q1 and the NMOS tube Q2, so that a mainboard CPU connected with the pulse output end inputs a pulse signal of high level-low level-high level, under the pure hardware collocation without adopting software programming, the power-on self-starting of the mainboard can be realized only by inputting high level, the structure of the mainboard switch circuit is simplified, the reliability of the analog switch circuit based on the mainboard design is improved, and the use cost of the analog switch circuit based on the mainboard design is reduced.

Preferably, a pull-up resistor R1 is connected between the drain of the NMOS transistor Q1 and the input end of the tristate gate U1; a pull-up resistor R2 is connected between the drain of the NMOS transistor Q2 and the gate of the NMOS transistor Q1.

Furthermore, through the arrangement of the pull-up resistor R1 and the pull-up resistor R2, the switching efficiency of the NMOS tube Q1 and the NMOS tube Q2 between a conducting state and a cut-off state can be improved, the state switching speed of the NMOS tube Q1 and the state switching speed of the NMOS tube Q2 are prevented from being lower than the conducting speed of the delay circuit, the problem that the mainboard is failed to start due to the fact that a pulse output end cannot output low-level pulses is avoided, and the reliability of the analog switch circuit based on the mainboard design is improved.

Preferably, the delay circuit includes a resistor R5 and a capacitor C2 connected in series with each other; the output interface of the delay circuit is arranged between the resistor R5 and the capacitor C2, and the grid electrode of the NMOS tube Q2 is connected with the output interface of the delay circuit; the resistor R5 is connected to the reset input and the capacitor C2 is connected to ground.

Further, constitute delay circuit through condenser C2 and resistor R5, simplified delay circuit's structure, further reduced the utility model discloses virtual switch circuit of mainboard occupation space on the mainboard to can adjust the time of pulse output low level pulse through the size that changes condenser C2 and resistor R5, make this application can adapt to the mainboard starting condition of multiple parameter based on the analog switch circuit of mainboard design, improve this application and based on the ageing and the economic nature of the analog switch circuit of mainboard design.

Preferably, the capacitance value of the capacitor C2 is 10uF, the resistor value of the resistor R5 is 100K Ω, the resistance value of the pull-up resistor R1 is 4.7K Ω, and the resistance value of the pull-up resistor R2 is 4.7K Ω.

Preferably, a pull-down resistor R4 is connected between the input terminal of the tri-state gate U1 and the drain of the NMOS transistor Q1.

Based on the setting of pull-down resistor R4, the low-level generation speed of the drain electrode of NMOS transistor Q1 can be improved, the conduction speed of NMOS transistor Q1 is improved, and the timeliness of the analog switch circuit based on the mainboard design is further improved.

Preferably, the resistance value of the pull-down resistor R4 is 100K Ω, and the pull-down resistor R4 is grounded.

Preferably, a filter capacitor C1 is connected between the tri-state gate U1 and the power supply input terminal, and the filter capacitor C1 is grounded.

In summary, according to the analog switch circuit based on the motherboard design, the motherboard CPU can obtain a high-level-low-level-high-level pulse only through high-level input without adopting pure hardware collocation of software programming, so as to realize power-on start of the motherboard, thereby improving reliability and economy of the analog switch circuit based on the motherboard design, and convenience and economy of a working method of the analog switch circuit based on the motherboard design.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of an analog switch circuit based on a motherboard design according to an embodiment of the present invention;

reference numerals: 100-power input end, 200-reset input end, 300-pulse output end, 400-starting unit and 500-reset unit.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It should be noted that, in the description of the present invention, the terms "first", "second", and the like are used for descriptive purposes only and for distinguishing similar objects, and no order is shown between the two, and no indication or suggestion of relative importance is understood. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Example (b): referring to fig. 1, an analog switching circuit based on a motherboard design includes a power input terminal 100, a reset input terminal 200, a pulse output terminal 300, a start unit 400, and a reset unit 500. The power input terminal 100 is used for connecting to a power supply and providing a voltage signal of ACPI-3V3 for the circuit. The reset input 200 is connected to the motherboard CPU and is used to trigger a reset/boot signal RTC _ RSMRSTN. The pulse output terminal 300 is connected to the motherboard CPU, and is configured to output a pulse signal PWR _ BTN # to the motherboard CPU.

The start-up unit 400 includes a tristate gate U1 and a pull-up resistor R3; the tri-state gate U1 is connected with the power input terminal 100, the enable terminal of the tri-state gate U1 is connected with the reset input terminal 200, and the output terminal of the tri-state gate U1 is connected with the pulse output terminal 300; pull-up resistor R3 is connected between the output of tristate gate U1 and the pulse output terminal 300. Tristate gate U1 and pull-up resistor R3 are based on the prior art. The reset unit 500 comprises an NMOS transistor Q1, an NMOS transistor Q2 and a delay circuit; the drain electrode of the NMOS tube Q1 is connected with the input end of the tristate gate U1, the source electrode of the NMOS tube Q1 is grounded, and the grid electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2; the source electrode of the NMOS tube Q2 is grounded; two ends of the delay circuit are respectively connected with the grid of the NMOS tube Q2 and the reset input end 200. The NMOS transistor Q1 and the NMOS transistor Q2 are both N-channel field effect transistors in the prior art.

Based on the structure, through the analog switch circuit formed by the three-state gate U1, the NMOS tube Q1 and the NMOS tube Q2, the pulse output end 300 outputs high level under the high resistance state of the three-state gate U1, outputs low level when the NMOS tube Q1 is conducted and outputs high level when the NMOS tube Q2 is conducted, so that a mainboard CPU connected to the pulse output end 300 inputs a pulse signal of high level-low level-high level, under the pure hardware collocation without adopting software programming, the power-on self-starting of a mainboard can be realized only by inputting high level, the structure of the mainboard switch circuit is simplified, the reliability of the analog switch circuit based on the mainboard design is improved, and the use cost of the analog switch circuit based on the mainboard design is reduced.

In this embodiment, the model number of the tri-state gate U1 is SGM7SZ126YC5G, the first pin of the tri-state gate U1 is an enable terminal, the second pin is an input terminal, the third pin is grounded, the fourth pin is an output terminal, and the fifth pin is connected to the power input terminal 100. The model of the NMOS tube Q1 and the model of the NMOS tube Q2 are both 2N 7002.

As a preferred implementation manner of this embodiment, a pull-up resistor R1 is connected between the drain of the NMOS transistor Q1 and the input of the tristate gate U1; a pull-up resistor R2 is connected between the drain of the NMOS transistor Q2 and the gate of the NMOS transistor Q1. The advantage of setting up like this is, through the setting of pull-up resistor R1, pull-up resistor R2, can improve NMOS pipe Q1 and NMOS pipe Q2 and switch over efficiency between the on and off state, prevent that the state switching speed of NMOS pipe Q1 and NMOS pipe Q2 is less than the turn-on speed of delay circuit, avoid pulse output 300 can't export the problem that the mainboard start-up fails that low level pulse causes, improve the reliability of this application based on the analog switch circuit of mainboard design. In the present embodiment, both the pull-up resistor R1 and the pull-up resistor R2 are based on the prior art, the resistance value of the pull-up resistor R1 is 4.7K Ω, and the resistance value of the pull-up resistor R2 is 4.7K Ω.

As a preferred implementation manner of this embodiment, the delay circuit includes a resistor R5 and a capacitor C2 connected in series with each other; the output interface of the delay circuit is arranged between the resistor R5 and the capacitor C2, and the grid electrode of the NMOS tube Q2 is connected with the output interface of the delay circuit; resistor R5 is connected to the reset input 200 and capacitor C2 is connected to ground. The benefit that sets up like this is, constitute delay circuit through condenser C2 and resistor R5, has simplified delay circuit's structure, has further reduced the utility model discloses virtual switch circuit of mainboard occupation space on the mainboard to can adjust the time of pulse output 300 output low level pulse through the size that changes condenser C2 and resistor R5, make this application can adapt to the mainboard start-up condition of multiple parameter based on the analog switch circuit of mainboard design, improve this application based on the analog switch circuit's of mainboard design timeliness and economic nature. In the present embodiment, the resistor R5 and the capacitor C2 are based on the prior art, the capacitance of the capacitor C2 is 10uF, and the resistor value of the resistor R5 is 100K Ω.

As a preferred implementation manner of this embodiment, a pull-down resistor R4 is connected between the input terminal of the tri-state gate U1 and the drain of the NMOS transistor Q1. Based on the setting of pull-down resistor R4, the low-level generation speed of the drain electrode of NMOS transistor Q1 can be improved, the conduction speed of NMOS transistor Q1 is improved, and the timeliness of the analog switch circuit based on the mainboard design is further improved. In the present embodiment, the pull-down resistor R4 is based on the prior art, the resistance of the pull-down resistor R4 is 100K Ω, and the pull-down resistor R4 is grounded.

As a preferred implementation manner of this embodiment, a filter capacitor C1 is connected between the tri-state gate U1 and the power input terminal 100, and the filter capacitor C1 is grounded. The advantage of this arrangement is that through the arrangement of the filter capacitor C1, the ripple in the dc power supply input by the tri-state gate U1 can be filtered, thereby improving the signal quality in the circuit. In the present embodiment, the filter capacitor C1 is based on the prior art, and the resistance of the filter capacitor C1 is 10 uF.

Immediately after power-on, when ACPI _3V3 is generated, the RTC _ RSMRST # signal at the reset input 200 remains in a low state, i.e., the first pin of the tri-state gate U1 is in a low state, at this time, the output of the tri-state gate U1 is in a high impedance state, and the PWR _ BTN # signal at the pulse output 300 is pulled up to a high state with the voltage of ACPI _3V 3; when the signal RTC _ RSMRST # of the reset input terminal 200 changes to a high level state, the tri-state gate U1 is in a normal working state at this time, due to the existence of the delay circuit, the NMOS transistor Q2 is kept in a cut-off state first, the NMOS transistor Q1 is in a conducting state, the output terminal of the tri-state gate U1 outputs a low level, and the pulse output terminal 300 outputs a low level PWR _ BTN # pulse signal; when the grid terminal level of the NMOS tube Q2 rises to the MOS tube conducting voltage threshold value, the NMOS tube Q2 is conducted, the NMOS tube Q1 is cut off, then the low level of the output terminal of the three-state gate U1 is pulled high to be changed into high level, the pulse output terminal 300 outputs high level PWR _ BTN # pulse signal, thereby simulating high level-low level-high level pulse signal, the pulse signal is input to a mainboard CPU, the mainboard is powered on to be automatically started, the mainboard starting is realized by pure hardware collocation without adopting software programming, the reliability of the analog switch circuit based on the mainboard design is improved, and the use cost of the analog switch circuit based on the mainboard design is reduced.

The embodiment also discloses a working principle of the analog switch circuit based on the mainboard design, which comprises the following steps that the circuit firstly comprises two working states of normal starting and reset starting:

the normal start-up comprises the following steps:

1. the voltage is input at the power input terminal 100 and flows into the tri-state gate U1;

2. the reset input end 200 is kept in a low level state, the output end of the tri-state gate U1 is in a high resistance state, the NMOS tube Q1 is in a conducting state, and the NMOS tube Q2 is in a cut-off state;

3. the pulse output terminal 300 is pulled up to a high level along with the voltage of the pull-up resistor R3, and outputs a high level to subsequent elements;

the reset starting comprises the following steps:

1. when the reset input end 200 inputs a high level signal, after the input signal passes through the delay circuit, the NMOS transistor Q2 keeps a cut-off state, the NMOS transistor Q1 keeps a conducting state, the output end of the tri-state gate U1 outputs a low level, and the pulse output end 300 is pulled down to be changed into a low level state;

2. with the lapse of time, when the gate voltage of the NMOS transistor Q2 gradually rises and reaches a threshold, the NMOS transistor Q2 is turned on, the NMOS transistor Q1 is turned off, the output terminal of the tri-state gate U1 outputs a high level, and the pulse output terminal 300 is pulled high to be in a high level state;

3. the main board CPU connected to the pulse output terminal 300 obtains a high level-low level-high level pulse signal output from the pulse output terminal 300, and the main board is powered on and started.

Based on the above steps, the high level is input at the reset input end 200 and the power input end 100, and the states of the tri-state gate U1, the NMOS transistor Q1 and the NMOS transistor Q2 are switched, so that the pulse output end 300 outputs a high level-low level-high level pulse, and under the pure hardware collocation without adopting software programming, the power-on self-starting of the mainboard is realized, the working method of the mainboard switching circuit is simplified, and the convenience and reliability of the working method of the analog switching circuit based on the mainboard design for the power-on operation of the mainboard are improved.

In this embodiment, step 1 of resetting and starting specifically includes:

1. when the reset input end 200 inputs a high level signal, the tristate gate U1 is in a normal working state, the gate of the NMOS transistor Q2 is kept in a low level state under the action of the delay circuit, the NMOS transistor Q2 is cut off, and the drain of the NMOS transistor Q2 is pulled up to a high level state under the action of the pull-up resistor R2;

2. the grid electrode of the NMOS tube Q1 is pulled high to be in a high level state, the NMOS tube Q1 is conducted, and the drain electrode of the NMOS tube Q1 is changed into a low level state;

3. the output end of the tri-state gate U1 outputs low level, the pulse output end 300 is pulled down to be changed into a low level state, and the mainboard CPU inputs a section of low level pulse.

In this embodiment, the step 2 of resetting and starting specifically includes:

1. with the energy storage of the capacitor C2, when the voltage value of the capacitor C2 reaches the conduction threshold, the voltage of the gate of the NMOS transistor Q2 rises to the threshold, the NMOS transistor Q2 conducts, and the drain of the NMOS transistor Q2 changes to a low level state;

2. the grid electrode of the NMOS tube Q1 is pulled down under the action of the drain electrode of the NMOS tube Q2 to be changed into a low level state, and the NMOS tube Q1 is cut off;

3. the output end of the tri-state gate U1 outputs high level, the pulse output end 300 is pulled high to be changed into a high level state, and the mainboard CPU obtains a section of high level pulse.

According to the analog switch circuit based on the mainboard design and the working principle thereof, the mainboard CPU can obtain a pulse of high level-low level-high level only through the input of high level without adopting the pure hardware collocation of software programming, the power-on starting of the mainboard is realized, and the convenience and the economical efficiency of the working method of the analog switch circuit based on the mainboard design are improved.

The present invention has been explained by using specific embodiments, and the explanation of the above embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

Claims (7)

1. An analog switch circuit based on a mainboard design is characterized by comprising a power supply input end (100), a reset input end (200), a pulse output end (300), a starting unit (400) and a reset unit (500);

the start-up unit (400) comprises a tristate gate U1 and a pull-up resistor R3; the tri-state gate U1 is connected with the power supply input end (100), the enable end of the tri-state gate U1 is connected with the reset input end (200), and the output end of the tri-state gate U1 is connected with the pulse output end (300); the pull-up resistor R3 is connected between the output terminal of the tristate gate U1 and the pulse output terminal (300);

the reset unit (500) comprises an NMOS tube Q1, an NMOS tube Q2 and a delay circuit; the drain of the NMOS transistor Q1 is connected with the input end of the tristate gate U1, the source of the NMOS transistor Q1 is grounded, and the gate of the NMOS transistor Q1 is connected with the drain of the NMOS transistor Q2; the source electrode of the NMOS tube Q2 is grounded; and two ends of the delay circuit are respectively connected with the grid electrode of the NMOS tube Q2 and the reset input end (200).

2. The analog switch circuit based on mainboard design of claim 1, wherein a pull-up resistor R1 is connected between the drain of the NMOS transistor Q1 and the input terminal of the tristate gate U1; a pull-up resistor R2 is connected between the drain of the NMOS transistor Q2 and the gate of the NMOS transistor Q1.

3. The analog switch circuit based on motherboard design as recited in claim 1, wherein said delay circuit comprises a resistor R5 and a capacitor C2 connected in series with each other; the output interface of the delay circuit is arranged between the resistor R5 and the capacitor C2, and the grid electrode of the NMOS tube Q2 is connected with the output interface of the delay circuit; the resistor R5 is connected to the reset input (200) and the capacitor C2 is connected to ground.

4. Analog switch circuit based on motherboard design according to claim 2 or 3, characterized in that the capacitance of capacitor C2 is 10uF and the resistor value of resistor R5 is 100K Ω.

5. The analog switch circuit based on main board design of claim 4, wherein a pull-down resistor R4 is connected between the input terminal of the tri-state gate U1 and the drain of the NMOS transistor Q1.

6. The analog switch circuit based on motherboard design as recited in claim 5, wherein the resistance value of said pull-down resistor R4 is 100K Ω, and said pull-down resistor R4 is grounded.

7. Analog switch circuit based on motherboard design according to claim 1, characterized in that a filter capacitor C1 is connected between the tri-state gate U1 and the power supply input (100), the filter capacitor C1 being connected to ground.

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