CN211236056U

CN211236056U - Test circuit and electronic equipment

Info

Publication number: CN211236056U
Application number: CN201921719575.3U
Authority: CN
Inventors: 孙声鹏; 曹芝勇
Original assignee: Shenzhen TCL Digital Technology Co Ltd
Current assignee: Shenzhen TCL Digital Technology Co Ltd
Priority date: 2019-10-14
Filing date: 2019-10-14
Publication date: 2020-08-11
Anticipated expiration: 2029-10-14

Abstract

The utility model belongs to the technical field of automatic test, a test circuit and electronic equipment is disclosed, test circuit includes: the system comprises a microcontroller and at least two expansion interfaces, wherein the types of the expansion interfaces are different; the microcontroller is connected with a terminal; the microcontroller is also connected with the at least two expansion interfaces respectively. The test circuit is connected with the terminal to control the expansion interfaces, and meanwhile, the test circuit is provided with a plurality of expansion interfaces to realize function expansion, so that the problem that test equipment with a plurality of different interfaces is required to be used for testing when equipment to be tested has a plurality of different interfaces is solved, the full-automatic test is guaranteed, the test circuit is simple in structure, the operation intensity is reduced, the efficiency is high, and the waste of time and manpower is reduced.

Description

Test circuit and electronic equipment

Technical Field

The utility model relates to an automatic test technical field especially relates to a test circuit and electronic equipment.

Background

In the design and development process of the electronic equipment, in order to verify the stability and matching degree of software and hardware systems in the starting process, a large amount of on-off tests can be carried out, the test times are often thousands of times and ten thousand orders of magnitude, when the current main test method is used for testing a device to be tested, the adopted interface of the test equipment is single, when the device to be tested has more interfaces of different types, the test equipment with a plurality of different interfaces is required to be used for testing, and the problem of complex test resource waste in the test process exists.

The above is only for the purpose of assisting understanding of the technical solutions of the present invention, and does not represent an admission that the above is the prior art.

SUMMERY OF THE UTILITY MODEL

A primary object of the present invention is to provide a test circuit and an electronic device, which can simplify the test process and save the test resources in the prior art.

In order to achieve the above object, the utility model provides a test circuit, test circuit includes: the system comprises a microcontroller and at least two expansion interfaces, wherein the types of the expansion interfaces are different; wherein,

the microcontroller is connected with the terminal; the microcontroller is also connected with the at least two expansion interfaces respectively.

Preferably, the test circuit further comprises a switching interface, the switching interface is connected with the terminal, and the switching interface is further connected with the microcontroller.

Preferably, the switching interface includes a switching chip, a positive data signal end of the switching chip is connected to a positive data signal end of the terminal, a negative data signal end of the switching chip is connected to a negative data signal end of the terminal, a signal transmitting end of the switching chip is connected to a signal receiving end of the microcontroller, and the signal receiving end of the switching chip is connected to the signal transmitting end of the microcontroller.

Preferably, the expansion interface comprises a USB-S interface, the USB-S interface is connected with the microcontroller, and the USB-S interface is further connected with the device to be tested.

Preferably, the extended interface further comprises an HDMI-S interface, the HDMI-S interface is connected with a terminal to be tested, and the HDMI-S interface is further connected with the microcontroller.

Preferably, the HDMI-S interface includes an HDMI-S port and a first current limiting circuit; the HDMI-S port is connected with the first current limiting circuit, the first current limiting circuit is connected with the microcontroller, and the HDMI-S port is further connected with a device to be tested.

Preferably, the expansion interface further includes a local area network interface, the local area network interface is connected to the microcontroller, and the local area network interface is further connected to the device to be tested.

Preferably, the local area network interface includes a local area network port, and a signal receiving end of the local area network port is connected with a signal sending end of the microcontroller; the signal identification end of the local area network port is connected with the signal identification end of the microcontroller; and the grounding end of the local area network port is grounded.

Preferably, the test circuit further comprises an infrared receiving head and a first capacitor; the first end of the infrared receiving head is connected with the microcontroller, the second end of the infrared receiving head is grounded, the third end of the infrared receiving head is connected with the power supply, the third end of the infrared receiving head is also connected with the first end of the first capacitor, and the second end of the first capacitor is grounded.

Furthermore, to achieve the above object, the present invention also provides an electronic device, which includes the test circuit as described above.

The technical scheme of the utility model is that a test circuit is formed by arranging a microcontroller and at least two expansion interfaces, and the types of the expansion interfaces are different; the microcontroller is connected with a terminal; the microcontroller is also connected with the at least two expansion interfaces respectively. The test circuit is connected with the terminal to control the expansion interfaces, and meanwhile, the test circuit is provided with a plurality of expansion interfaces to realize function expansion, so that the problem that test equipment with a plurality of different interfaces is required to be used for testing when equipment to be tested has a plurality of different interfaces is solved, the full-automatic test is guaranteed, the test circuit is simple in structure, the operation intensity is reduced, the efficiency is high, and the waste of time and manpower is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a functional block diagram of an embodiment of a test circuit according to the present invention;

fig. 2 is a schematic diagram of a USB-S interface circuit according to an embodiment of the test circuit of the present invention;

fig. 3 is a schematic diagram of an HDMI-S interface circuit according to an embodiment of the test circuit of the present invention;

FIG. 4 is a schematic diagram of a Micro USB-S interface circuit according to an embodiment of the test circuit of the present invention;

fig. 5 is a schematic diagram of an infrared receiving circuit according to an embodiment of the testing circuit of the present invention;

fig. 6 is a schematic diagram of a flash memory circuit according to an embodiment of the test circuit of the present invention;

fig. 7 is a schematic diagram of a reset circuit according to an embodiment of the test circuit of the present invention;

fig. 8 is a schematic diagram of a power circuit according to an embodiment of the test circuit of the present invention.

The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, it should be considered that the combination of the technical solutions does not exist, and is not within the protection scope of the present invention.

The utility model provides a test circuit.

Referring to fig. 1, fig. 1 is a functional block diagram of an embodiment of a test circuit according to the present invention;

in an embodiment of the present invention, the test circuit includes: the microcontroller 100 and at least two expansion interfaces 200, each of the expansion interfaces 200 being of a different type; wherein,

the microcontroller 100 is connected with a terminal 300; the microcontroller 100 is also connected to the at least two expansion interfaces 200.

In this embodiment, the test circuit includes at least two expansion interfaces 200, each of the expansion interfaces 200 is of a different type, and the expansion interfaces 200 may include a USB-S interface, an HDMI-S interface, a lan interface, a Micro USB-S interface, and the like. The microcontroller 100 is connected to the terminal 300, receives a serial command sent by the terminal 300, and controls the expansion interface 200. For example, the microcontroller 100 receives a serial port command of the terminal 300 and parses a corresponding control object and a corresponding operation in the serial port command, where the serial port command may include a high-low level signal, a time sequence signal, and the like, and if the serial port command requires to control the insertion of the expansion interface 200, an identification signal may be sent to the signal identification end STATE of the expansion interface 200 through the signal identification end STATE of the microcontroller 100 to identify the expansion interface 200 corresponding to the serial port command, and then a high-level signal, a time sequence signal, and the like are sent to the signal receiving end DATA of the corresponding expansion interface 200 through the signal sending end DATA of the microcontroller 100, so that the corresponding expansion interface 200 may be controlled to access, and the insertion and the function expansion of the expansion interface 200 may be achieved; if the serial port instruction requires to control the extension interface 200 to be pulled out, an identification signal may be sent to the signal identification end STATE of the extension interface 200 through the signal identification end STATE of the microcontroller 100 to identify the extension interface 200 corresponding to the serial port instruction, and then a low-level signal, a time-series signal, or the like may be output to the signal receiving end DATA of the corresponding extension interface 200 through the signal sending end DATA of the microcontroller 100, so as to control the corresponding extension interface 200 to be pulled out.

It should be emphasized that the test circuit is suitable for the upper computer side, such as a computer, a mobile phone, a tablet and the like, and is used for testing various electrical equipment, including but not limited to a television, a computer, a refrigerator, a washing machine, an air conditioner and the like. The test circuit takes the test of the air conditioner as an example, the test system comprises an upper computer, a display and a test circuit, wherein the display with touch keys is used for controlling the operation of the air conditioner, the upper computer can be a computer, and the test circuit is respectively connected with the upper computer and the display of the air conditioner and is used for controlling the display according to a test command sent by the upper computer so as to control the operation of the air conditioner. The upper computer can comprise a user operation interface, a tester writes serial port commands according to control logic, writes contents to be tested into the serial port commands and guides the serial port commands into the upper computer, the upper computer calls the serial port commands, and after the execution time is set, the upper computer calls the corresponding serial port commands according to set time and time sequence and sends the serial port commands to the test circuit. Meanwhile, the prepared serial port command can be stored in a serial port command library for direct calling in subsequent tests of the same logic function, and the test efficiency is further improved. Can pass through the communication of Modbus communication protocol between host computer and the test circuit, the host computer can be via switching interface or data line transmission to test circuit's microcontroller 100 to the serial port command, microcontroller 100 can adopt the STM32 chip, carries out analytic processing and sends control signal to the display to the serial port command that receives, reaches the purpose of automated test. When the state of the air conditioner needs to be changed through the display, the state is selected on a corresponding control on a user operation interface of the upper computer, and when different control logics need to be tested, different programs need to be called by the upper computer.

The technical scheme of the utility model is that a test circuit is formed by arranging a microcontroller 100 and at least two expansion interfaces 200, and the types of the expansion interfaces are different; wherein, the microcontroller 100 is connected with a terminal 300; the microcontroller 100 is also connected to the expansion interface 200. The test circuit is connected with the terminal 300 through the microcontroller 100, receives a serial port command of the terminal, realizes control over the expansion interface 200, realizes hot plug of the expansion interface 200, simultaneously, the test circuit designs a plurality of expansion interfaces to realize function expansion, solves the problem that test equipment with a plurality of different interfaces is required to be used for testing when the equipment to be tested has a plurality of different interfaces, and accordingly provides guarantee for full-automatic testing.

Those skilled in the art will appreciate that the configuration shown in fig. 1 does not constitute a limitation of the test circuit, and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.

Further, the test circuit further includes a switching interface, the switching interface is connected to the terminal 300, and the switching interface is further connected to the microcontroller 100.

The switching interface comprises a switching chip, a data positive signal end of the switching chip is connected with a data positive signal end of the terminal 300, a data negative signal end of the switching chip is connected with a data negative signal end of the terminal 300, a signal sending end of the switching chip is connected with a signal receiving end of the microcontroller 100, and the signal receiving end of the switching chip is connected with a signal sending end of the microcontroller 100.

In this embodiment, the switching interface includes a switching chip, the switching interface may further include peripheral circuits such as a current limiting circuit and a clock circuit, the switching chip may be a USB serial-to-serial port chip, and a common USB serial-to-serial port chip includes FT232, PL2303, CH340, and the like. The test circuit realizes serial communication with the terminal 300 through the switching chip, a data positive signal end D + of the switching chip is connected with a data positive signal end D + of a USB port of the terminal 300, a data negative signal end D-of the switching chip is connected with a data negative signal end D-of the USB port of the terminal 300, the switching chip receives a serial command sent by the terminal 300, a signal sending end TXD of the switching chip is connected with a signal receiving end RXD of the microcontroller 100, the signal receiving end RXD of the switching chip is connected with a signal sending end TXD of the microcontroller 100, and the signal receiving end RXD of the microcontroller 100 receives the serial command forwarded by the switching chip. The serial port command may include a high-low level signal, a timing signal, etc., and the microcontroller 100 parses the serial port command and sends a corresponding control signal to the corresponding expansion interface 200.

Further, referring to fig. 2, the expansion interface 200 includes a USB-S interface, the USB-S interface is connected to the microcontroller 100, and the USB-S interface is also connected to the device to be tested.

In this embodiment, referring to fig. 2, fig. 2 is a schematic diagram of a structure of a USB-S interface circuit according to an embodiment of the test circuit of the present invention. The USB-S interface may include a USB-S port P1 and a pull-up circuit; the USB-S port P1 is connected to the pull-up circuit, the pull-up circuit is connected to a power source VCC, and the USB-S port P1 is further connected to the microcontroller 100 and a device to be tested. The USB-S interface may include a USB-S port and a pull-up circuit, the pull-up circuit may include a first resistor R1, a second resistor R2, a third resistor R3, a zener diode D1, a second capacitor C2 and a third capacitor C3, a first end of the first resistor R1 is connected to the USB-S port P1, a second end of the first resistor R1 is connected to an anode of the zener diode D1, a cathode of the zener diode D1 is connected to a power source VCC, a first end of the second resistor R2 is connected to a cathode of the zener diode D1, a second end of the second resistor R2 is connected to the USB-S port P1, a second end of the second resistor R2 is further connected to a first end of the second capacitor C2, a second end of the second capacitor C2 is connected to the USB-S port P1, a first end of the third resistor R3 is connected to a second end of the second resistor R2, a second end of the third resistor R3 is connected to the USB-S port P1, a second end of the third resistor R3 is further connected to a first end of the third capacitor C3, a second end of the third capacitor C3 is connected to the USB-S port P1, and the USB-S port P1 is connected to the microcontroller 100. And the power supply VCC supplies power to the USB-S interface. The USB-S interface is a serial port of a USB interface type, can be matched with equipment to be tested with a USB serial port connection function, achieves a full-automatic startup and shutdown test function, and can synchronously monitor whether the equipment to be tested is abnormal. The method can replace the operation mode in the traditional test, can detect the hidden danger of the product quality and provide test data for further improving and using the equipment to be tested.

Further, the expansion interface 200 further includes an HDMI-S interface, the HDMI-S interface is connected to a terminal to be tested, and the HDMI-S interface is further connected to the microcontroller. The HDMI-S interface comprises an HDMI-S port P2 and a first current limiting circuit; the HDMI-S port P2 is connected to the first current limiting circuit, the first current limiting circuit is connected to the microcontroller 100, and the HDMI-S port P2 is further connected to a device to be tested.

In this embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of an HDMI-S interface circuit according to an embodiment of the test circuit of the present invention. The HDMI-S interface may include: the HDMI-S port P2 and a first current limiting circuit, the first current limiting circuit may include a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9, wherein: a first end of the fourth resistor R4 is connected to the HDMI-S port P2, a second end of the fourth resistor R4 is connected to the microcontroller 100, a first end of the fifth resistor R5 is connected to a first end of the fourth resistor R4, a second end of the fifth resistor R5 is connected to the microcontroller 100, a first end of the sixth resistor R6 is connected to the HDMI-S port P2, a second end of the sixth resistor R6 is connected to the microcontroller 100, a first end of the seventh resistor R7 is connected to a first end of the sixth resistor R6, a second end of the seventh resistor R7 is connected to the microcontroller 100, a first end of the eighth resistor R8 is connected to the HDMI-S port P2, a second end of the eighth resistor R8 is connected to the microcontroller 100, a first end of the ninth resistor R9 is connected to the HDMI-S port P2, a second terminal of the ninth resistor R9 is connected to the microcontroller 100.

It should be noted that the HDMI-S Interface is a serial Interface of an HDMI Interface type, and the HDMI is a High Definition Multimedia Interface (HDMI), which is a full digital video and audio transmission Interface and can transmit uncompressed audio and video signals. The HDMI can be used for set-top boxes, DVD players, personal computers, video players, comprehensive amplifiers, digital audio devices, televisions and other equipment. The HDMI-S interface can be matched with equipment with an HDMI serial port connection function, such as a set top box, a DVD player, a personal computer, a TV game machine, a comprehensive amplifier, a digital sound box, a TV set and the like, can be matched with equipment to be tested with the HDMI-S serial port connection function, realizes the function of full-automatic startup and shutdown testing, and can synchronously monitor whether the equipment to be tested is abnormal. The method can replace the operation mode in the traditional test, can detect the hidden danger of the product quality and provide test data for further improving and using the equipment to be tested.

Further, the expansion interface 200 further includes a local area network interface, the local area network interface is connected to the microcontroller 100, and the local area network interface is further connected to a device to be tested.

The local area network interface comprises a local area network port, and a signal receiving end DATA of the local area network port is connected with a signal sending end DATA of the microcontroller 100; the signal identification terminal STATE of the lan port is connected to the signal identification terminal STATE of the microcontroller 100; and the grounding end GND of the local area network port is grounded.

In this embodiment, the lan interface may include: a first LAN port, a second LAN port, and a third LAN port; the first lan port, the second lan port and the third lan port may be connected to the microcontroller 100, respectively, or the first lan port is connected to the microcontroller 100, the second lan port is connected to the first lan port, and the third lan port is connected to the second lan port; the third lan port is connected to the microcontroller 100. The local area network interface is used for expanding submodules with simple operation and short serial port command, such as submodules for USB switching, network cable switching and the like.

For example, the microcontroller 100 receives a serial port command of the terminal 300 and parses a corresponding control object and a corresponding operation in the serial port command, the local area network port is required to be controlled to be inserted in the serial port command, and the signal identification end STATE of the local area network port is connected to the signal identification end STATE of the microcontroller 100, so that an identification signal can be sent to the signal identification end STATE of the local area network port through the signal identification end STATE of the microcontroller 100 to identify the local area network port corresponding to the serial port command; the signal receiving end DATA of the LAN port is connected with the signal transmitting end DATA of the microcontroller 100, and the signal transmitting end DATA of the microcontroller 100 transmits a high-level signal to the corresponding signal receiving end DATA of the LAN port, so that the access of the corresponding LAN port can be controlled, and the insertion and function expansion of the LAN port are realized; if the serial port instruction requires to control the local area network port to be pulled out, an identification signal can be sent to the signal identification end STATE of the local area network port through the signal identification end STATE of the microcontroller 100 to identify the local area network port corresponding to the serial port instruction, and then a low-level signal is output to the signal receiving end DATA of the corresponding local area network port through the signal sending end DATA of the microcontroller 100, so that the corresponding local area network port can be controlled to be pulled out.

It should be noted that the lan interface may include a first lan port, a second lan port, a third lan port, and the like, where the number of the lan ports is not limited in this embodiment; the connection of each lan port to the microcontroller 100 is also not limited.

Further, the expansion interface 200 may further include a Micro USB-S interface, where the Micro USB-S interface is connected to the microcontroller 100, and the Micro USB-S interface is further connected to a device to be tested. The Micro USB-S interface can comprise a second current limiting circuit and a Micro USB-S port P3; the Micro USB-S port P3 is connected to the second current limiting circuit, the second current limiting circuit is connected to the microcontroller 100, and the Micro USB-S port P3 is further connected to a device to be tested.

In this embodiment, referring to fig. 4, fig. 4 is a schematic diagram of a Micro USB-S interface circuit according to an embodiment of the test circuit of the present invention. The Micro USB-S interface can comprise a second current limiting circuit and a Micro USB-S port P3, wherein the second current limiting circuit can comprise a tenth resistor R10 and an eleventh resistor R11; wherein, tenth resistance R10 'S first end with microcontroller 100 connects, tenth resistance R10' S first end still with Micro USB-S port P3 connects, tenth resistance R10 'S second end is connected with the power VCC, eleventh resistance R11' S first end with Micro USB-S port P3 connects, eleventh resistance R11 'S first end still with microcontroller 100 connects, eleventh resistance R11' S second end is connected with the power VCC, Micro USB-S port P3 with microcontroller 100 connects. And a power supply VCC supplies power to the MicroUSB-S interface. The Micro USB-S interface is used for expanding a submodule with complex operation and long serial port command, such as a Bluetooth submodule; after the Micro USB-S interface is matched with the equipment to be tested with the Bluetooth function, the equipment to be tested can be controlled to carry out full-automatic test, the function of automatic startup and shutdown is realized, and whether the equipment to be tested is abnormal or not can be synchronously monitored. The method can replace the operation mode in the traditional test, can detect the hidden danger of the product quality and provide test data for further improving and using the equipment to be tested.

Further, the test circuit also comprises an infrared receiving head U1 and a first capacitor C1; wherein, infrared ray receiving head U1's first end with microcontroller 100 connects, infrared ray receiving head U1's second end ground connection, infrared ray receiving head U1's third end is connected with the power VCC, infrared ray receiving head U1's third end still with first electric capacity C1's first end is connected, first electric capacity C1's second end ground connection.

In this embodiment, referring to fig. 5, fig. 5 is the infrared receiving circuit schematic diagram of the test circuit according to an embodiment of the present invention, the test circuit further includes an infrared receiving head U1 and a first capacitor C1, the infrared receiving head U1 and the first capacitor C1 constitute an infrared receiving circuit, and the infrared receiving circuit may further include other structures. The first end of infrared ray receiving head U1 with microcontroller 100 connects, infrared ray receiving head U1's second end ground connection, infrared ray receiving head U1's third end is connected with the power VCC. The third terminal of the infrared receiving head U1 is further connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is grounded. And the power supply VCC supplies power to an infrared receiving circuit consisting of the infrared receiving head U1 and the first capacitor C1. For example, the microcontroller 100 receives an infrared signal transmitted by the infrared receiving circuit, the infrared signal comes from a device to be tested, analyzes the infrared signal and transmits the infrared signal to the terminal 300, the terminal 300 may store the infrared signal, and the test circuit calls the stored infrared signal to realize control and test of the device to be tested when the device to be tested needs to be controlled. The shape of the commonly used infrared receiving head U1 has three pins, namely, a positive power supply VDD, a negative power supply GND and a data output Out, corresponding to the third end, the second end and the first end of the infrared receiving head U1, and the pin arrangement of the receiving head is different due to different models and also has the difference of the pins due to different shapes of the receiving head.

Further, the test circuit may further include a flash memory circuit, referring to fig. 6, and fig. 6 is a schematic diagram of a flash memory circuit according to an embodiment of the test circuit of the present invention. The flash memory circuit is connected to the microcontroller 100; the flash memory circuit may include a flash memory chip U2, a twelfth resistor R12 and a thirteenth resistor R13, a first end of the twelfth resistor R12 is connected to the power VCC, a second end of the twelfth resistor R12 is connected to the flash memory chip U2, a second end of the twelfth resistor R12 is connected to a first end of the thirteenth resistor R13, a second end of the thirteenth resistor R13 is connected to the flash memory chip U2, and the flash memory chip U2 is connected to the microcontroller 100. And the power supply VCC supplies power to the flash memory circuit. The flash memory chip U2 stores the product type and the code of the test circuit, which is used by the terminal 300 to distinguish the test circuit from other devices.

Further, the test circuit may further include a reset circuit, referring to fig. 7, and fig. 7 is a schematic diagram of the reset circuit according to an embodiment of the test circuit of the present invention. The microcontroller 100 is connected to the reset circuit; wherein the reset circuit may include: reset switch K1, fourteenth resistance R14, fifteenth resistance R15, sixteenth resistance R16 and first triode DE1, wherein: the first contact of reset switch K1 is connected with the power VCC, reset switch K1 second contact ground connection, reset switch K1 third contact with the first end of fourteenth resistance R14 is connected, the second end ground connection of fourteenth resistance R14, fifteenth resistance R15 first end with the first end of fourteenth resistance R14 is connected, the second end of fifteenth resistance R15 with first triode DE 1's base is connected, first triode DE 1's projecting pole ground connection, first triode DE 1's collecting electrode with the first end of sixteenth resistance R16 is connected, the second end of sixteenth resistance R16 is connected with the power VCC. And the power supply VCC supplies power to the reset circuit. Wherein the microcontroller 100 restores an initial state through the reset circuit. Other devices may be provided for resetting, which is not limited in this embodiment.

Further, the test circuit may further include a power circuit, referring to fig. 8, and fig. 8 is a schematic diagram of the power circuit according to an embodiment of the test circuit of the present invention. The power circuit is connected to the microcontroller 100, the power circuit may include a power chip U3, a third capacitor C3, a fourth capacitor C4, a first polarity capacitor CE1, and a second polarity capacitor CE2, a first end of the fourth capacitor C4 is connected to a power VCC, a first end of the fourth capacitor C4 is further connected to an anode of the first polarity capacitor CE1, a second end of the fourth capacitor C4 is grounded, a cathode of the first polarity capacitor CE1 is connected to the power chip U3, a first end of the fifth capacitor C5 is connected to an anode of the second polarity capacitor CE2, a second end of the fifth capacitor C5 is connected to a cathode of the second polarity capacitor CE2, an anode of the second polarity capacitor CE2 is connected to the power chip U3, and a cathode of the second polarity capacitor CE2 is grounded. And the power supply VCC supplies power to the power supply circuit.

Furthermore, to achieve the above object, the present invention also provides an electronic device, which includes the test circuit as described above. The specific structure of the test circuit refers to the above embodiments, and since the electronic device adopts all the technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.

It should be understood that the above is only an example, and the technical solution of the present invention is not limited in any way, and in the specific application, those skilled in the art can set the solution as required, and the present invention is not limited thereto.

It should be noted that the above-described work flow is only illustrative, and does not limit the scope of the present invention, and in practical applications, a person skilled in the art may select some or all of them to achieve the purpose of the solution of the embodiment according to practical needs, and the present invention is not limited herein.

Further, it is to be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.

The above embodiment numbers of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

The above is only the preferred embodiment of the present invention, and not the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings or the direct or indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A test circuit, wherein the test circuit comprises: the system comprises a microcontroller and at least two expansion interfaces, wherein the types of the expansion interfaces are different; wherein,

2. The test circuit of claim 1, further comprising a patch interface, the patch interface coupled to the terminal, the patch interface further coupled to the microcontroller.

3. The test circuit according to claim 2, wherein the switching interface includes a switching chip, a positive data signal terminal of the switching chip is connected to a positive data signal terminal of the terminal, a negative data signal terminal of the switching chip is connected to a negative data signal terminal of the terminal, a signal transmitting terminal of the switching chip is connected to a signal receiving terminal of the microcontroller, and a signal receiving terminal of the switching chip is connected to a signal transmitting terminal of the microcontroller.

4. The test circuit of claim 1, wherein the expansion interface comprises a USB-S interface, the USB-S interface being connected to the microcontroller, the USB-S interface also being connected to a device under test.

5. The test circuit of claim 1, wherein the expansion interface further comprises an HDMI-S interface, the HDMI-S interface being connected to a terminal to be tested, the HDMI-S interface further being connected to the microcontroller.

6. The test circuit of claim 5, wherein the HDMI-S interface comprises an HDMI-S port and a first current limit circuit; the HDMI-S port is connected with the first current limiting circuit, the first current limiting circuit is connected with the microcontroller, and the HDMI-S port is further connected with a device to be tested.

7. The test circuit of claim 1, wherein the expansion interface further comprises a local area network interface, the local area network interface being connected to the microcontroller, the local area network interface further being connected to a device under test.

8. The test circuit of claim 7, wherein the local area network interface comprises a local area network port, a signal receiving end of the local area network port being connected to a signal sending end of the microcontroller; the signal identification end of the local area network port is connected with the signal identification end of the microcontroller; and the grounding end of the local area network port is grounded.

9. The test circuit of claim 1, wherein the test circuit further comprises an infrared receiving head and a first capacitor; the first end of the infrared receiving head is connected with the microcontroller, the second end of the infrared receiving head is grounded, the third end of the infrared receiving head is connected with the power supply, the third end of the infrared receiving head is also connected with the first end of the first capacitor, and the second end of the first capacitor is grounded.

10. An electronic device, characterized in that it comprises a test circuit according to any one of claims 1 to 9.