CN211236008U - Current signal sending circuit for low-voltage power distribution area - Google Patents
Current signal sending circuit for low-voltage power distribution area Download PDFInfo
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- CN211236008U CN211236008U CN201921754652.9U CN201921754652U CN211236008U CN 211236008 U CN211236008 U CN 211236008U CN 201921754652 U CN201921754652 U CN 201921754652U CN 211236008 U CN211236008 U CN 211236008U
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- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 238000001514 detection method Methods 0.000 claims description 5
- 230000011664 signaling Effects 0.000 claims 9
- 230000001960 triggered effect Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 abstract description 8
- 230000008054 signal transmission Effects 0.000 abstract description 7
- 230000003466 anti-cipated effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
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Abstract
The utility model discloses a current signal transmission circuit for low-voltage power transformer district, including CPU, load resistance R7, silicon controlled rectifier K1, electric capacity C1, resistance R1 and silicon controlled rectifier trigger circuit; a live wire L of the alternating current power supply is connected with one end of a load resistor R7 through a fuse tube F1, the other end of the load resistor R7 is connected with an A pole of a silicon controlled rectifier K1, a K pole of the silicon controlled rectifier K1 is connected with a zero line N of the alternating current power supply, and a capacitor C1 is connected in series with a resistor R1 and then connected between the A pole and the K pole of the silicon controlled rectifier; the silicon controlled trigger circuit comprises a direct current working power supply VCC, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a triode Q1, a triode Q2, a triode Q3 and a triode Q4; when no trigger signal exists, the trigger loop is in a low-resistance state, so that the interference signal can be directly released, and the current signal sending circuit is ensured not to be triggered and started by mistake; the utility model discloses the sending signal is stable, triggers without mistake, and the phenomenon is burnt out to no longer emergence circuit, and it is accurate to draw the topological diagram.
Description
Technical Field
The utility model belongs to the technical field of electric power, a signal transmission circuit that low pressure power line platform district wiring topological graph was drawn is related to, concretely relates to current signal transmission circuit for low pressure power platform district.
Background
With the construction of the smart grid, the drawing of the topological graph of the low-voltage power station area becomes a basic requirement. With the topological graph, functions of accurately calculating the line loss of the transformer area, finding faults, positioning electricity stealing and the like can be realized. The wiring of the low-voltage power line station area is complex, a topological graph is drawn manually, and the workload is large and inaccurate. The technology capable of automatically and accurately drawing the topological graph of the transformer area is urgently needed, and a key link of the technology is a current signal sending circuit, and if the circuit is triggered and started by interference, the circuit can be damaged.
SUMMERY OF THE UTILITY MODEL
In view of the above, in order to solve the above-mentioned deficiencies of the prior art, the present invention provides a current signal transmitting circuit for a low-voltage power distribution room, wherein when there is no trigger signal, a trigger circuit is in a low-resistance state, and can directly release an interference signal, thereby ensuring that the current signal transmitting circuit is not triggered and started by mistake; the utility model discloses the transmitted signal is stable, triggers without mistake, and the phenomenon is burnt out to no longer emergence circuit, and it is accurate to draw the topological diagram, reaches anticipated effect, uses more accurately, extensively in lean on platform district management.
In order to achieve the above object, the utility model adopts the following technical scheme:
a current signal sending circuit for a low-voltage power station area comprises a CPU, a load resistor R7, a thyristor K1, a capacitor C1, a resistor R1 and a thyristor trigger circuit; a live wire L of the alternating current power supply is connected with one end of a load resistor R7 through a fuse tube F1, the other end of the load resistor R7 is connected with an A pole of a controlled silicon K1, a K pole of the controlled silicon K1 is connected with a zero line N of the alternating current power supply, and a capacitor C1 is connected with a resistor R1 in series and then connected between the A pole and the K pole of the controlled silicon;
the silicon controlled trigger circuit comprises a direct current working power supply VCC, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a triode Q1, a triode Q2, a triode Q3 and a triode Q4, wherein the CPU is connected with one end of the resistor R4, the other end of the resistor R4 is connected with the B pole of the triode Q2, the C pole of the triode Q2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the B pole of the triode Q1, and the C pole of the triode Q1 is connected with the resistor R2; the CPU is further connected with one end of a resistor R6, the other end of the resistor R6 is connected with the B pole of a triode Q3, the C pole of the triode Q3 is respectively connected with the B poles of a resistor R5 and a triode Q4, the C pole of the triode Q4 is respectively connected with the G poles of a resistor R2 and a silicon controlled rectifier K1, and the E pole of the triode Q4 is connected with the zero line N of an alternating current power supply.
Further, the thyristor K1 is a power control device, and the thyristor K1 is used for sending on and off of current.
Further, G of the thyristor K1 is a trigger terminal.
Further, the resistor R2 is connected with the G pole of the thyristor K1.
Furthermore, the capacitor C1 is connected with the resistor R1 in series to form a protection circuit, so that the thyristor K1 is prevented from being broken down by a sharp pulse.
Furthermore, the CPU is connected with a low-voltage alternating-current voltage zero-crossing detection device.
Furthermore, an E electrode of the triode Q1 and the resistor R5 are respectively connected to a dc power VCC.
Furthermore, the E pole of the transistor Q2 and the E pole of the transistor Q3 are both grounded.
Further, the triode Q1 is a PNP type triode, and the triode Q2, the triode Q3 and the triode Q4 are NPN type triodes.
The utility model has the advantages that:
the utility model discloses a current signal transmission circuit for low voltage power transformer district, when there is no trigger signal, the trigger circuit is in the low resistance state, can directly release the interference signal, thereby guarantee that current signal transmission circuit can not trigger the start by mistake; the utility model discloses the transmitted signal is stable, triggers without mistake, and the phenomenon is burnt out to no longer emergence circuit, and it is accurate to draw the topological diagram, reaches anticipated effect, uses more accurately, extensively in lean on platform district management. The concrete points are as follows:
firstly, the utility model adopts the zero crossing detection technology of low-voltage alternating voltage to accurately detect the zero crossing point of the alternating voltage;
the thyristor K1 is a power control device, and the thyristor K1 is used for sending on and off of current; the thyristor K1 is adopted, and the thyristor K1 is triggered and conducted near the zero crossing point of the alternating voltage, so that large current is sent;
thirdly, the silicon controlled trigger circuit comprises a direct current working power supply VCC, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a triode Q1, a triode Q2, a triode Q3 and a triode Q4; a silicon controlled trigger circuit with low impedance is adopted, so that the anti-interference capability is improved, and false triggering is prevented;
fourthly, the fuse tube F1 is used for preventing short circuit; a load resistor R7 for determining the current level of the signal transmission circuit; the capacitor C1 is connected with the resistor R1 in series to form a protection circuit, and the thyristor K1 is prevented from being broken down by sharp pulses.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of the present invention;
fig. 2 is a schematic diagram of the waveform of the present invention.
Detailed Description
The following provides specific embodiments, which will further clearly, completely and specifically explain the technical solutions of the present invention. The present embodiment is the best embodiment based on the technical solution of the present invention, but the scope of the present invention is not limited to the following embodiments.
A current signal sending circuit for a low-voltage power station area comprises a CPU, a load resistor R7, a thyristor K1, a capacitor C1, a resistor R1 and a thyristor trigger circuit; the live wire L of the alternating current power supply is connected with one end of a load resistor R7 through a fuse tube F1, the other end of the load resistor R7 is connected with the A pole of a thyristor K1, and the fuse tube F1 is used for preventing short circuit; a load resistor R7 for determining the current level of the signal transmission circuit; the K pole of the controlled silicon K1 is connected with the zero line N of the alternating current power supply, and the capacitor C1 is connected in series with the resistor R1 and then connected between the A pole and the K pole of the controlled silicon; in the utility model, a capacitor C1 is connected in series with a resistor R1 to form a protection circuit, thereby preventing the silicon controlled rectifier K1 from being punctured by sharp pulses;
in the utility model, the silicon controlled trigger circuit with low impedance is adopted, so that the anti-interference capability is improved, and the false triggering is prevented; the silicon controlled trigger circuit comprises a direct current working power supply VCC, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a triode Q1, a triode Q2, a triode Q3 and a triode Q4, wherein the CPU is connected with one end of the resistor R4, the other end of the resistor R4 is connected with the B pole of the triode Q2, the C pole of the triode Q2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the B pole of the triode Q1, and the C pole of the triode Q1 is connected with the resistor R2; the CPU is further connected with one end of a resistor R6, the other end of the resistor R6 is connected with the B pole of a triode Q3, the C pole of the triode Q3 is respectively connected with the B poles of a resistor R5 and a triode Q4, the C pole of the triode Q4 is respectively connected with the G poles of a resistor R2 and a silicon controlled rectifier K1, and the E pole of the triode Q4 is connected with the zero line N of an alternating current power supply. Referring to fig. 2, in fig. 1, when there is no trigger pulse, the junction between the CPU and the resistor R4 is at low level, the transistor Q2 is turned off, the C electrode of the transistor Q2 is at high level, the transistor Q1 is turned off, and the C electrode of the transistor Q1 outputs low level, which means that there is no trigger pulse output; meanwhile, the junction between the CPU and the resistor R6 is also low level, the triode Q3 is cut off, the C pole of the triode Q3 is at high level because the DC power VCC and the resistor R5 provide current, the high level enables the triode Q4 to be conducted, so that the G pole of the trigger end of the controlled silicon K1 is connected to the ground, the G pole of the trigger end of the controlled silicon K1 is at low resistance state to the ground, the external interference signal to the G pole of the trigger end of the controlled silicon K1 is released by the triode Q4, and the controlled silicon K1 is ensured not to be triggered by mistake; when a trigger pulse exists, the connection position of the CPU and the resistor R4 is in a high level, the triode Q2 is conducted, the C pole of the triode Q2 is in a low level, the triode Q1 is conducted, the C pole of the triode Q1 outputs a high level, the current is limited through the resistor R2, and the trigger pulse is provided for the silicon controlled rectifier K1; meanwhile, the junction between the CPU and the resistor R6 is also high level, the triode Q3 is conducted, the C electrode of the triode Q3 is low level, and the low level enables the triode Q4 to be cut off, so that the pulse current provided by the triode Q1 can only flow through the G electrode and the K electrode of the controlled silicon K1, and the controlled silicon K1 is triggered and conducted.
Further, the triode Q1 is a PNP type triode, and the triode Q2, the triode Q3 and the triode Q4 are NPN type triodes.
Furthermore, the capacitor C1 is connected with the resistor R1 in series to form a protection circuit, so that the thyristor K1 is prevented from being broken down by a sharp pulse.
Furthermore, an E electrode of the triode Q1 and the resistor R5 are respectively connected to a dc power VCC.
Furthermore, the E pole of the transistor Q2 and the E pole of the transistor Q3 are both grounded.
Further, the thyristor K1 is a power control device, and the thyristor K1 is used for sending on and off of current. By adopting the thyristor K1, the thyristor K1 is triggered and switched on near the zero crossing point of the alternating voltage, so that large current is sent.
Further, G of the thyristor K1 is a trigger terminal.
Further, the resistor R2 is connected with the G pole of the thyristor K1.
Furthermore, the CPU is connected with a low-voltage alternating-current voltage zero-crossing detection device. The utility model discloses a low pressure alternating voltage zero passage detection technique, the accurate zero crossing point that detects alternating voltage.
As shown in fig. 1, the circuit schematic diagram of the present invention, then the working principle of the present invention is:
the silicon controlled trigger circuit comprises a direct current working power supply VCC, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a triode Q1, a triode Q2, a triode Q3 and a triode Q4; when no trigger pulse exists, the connection position of the CPU and the resistor R4 is in a low level, the triode Q2 is cut off, the C electrode of the triode Q2 is in a high level, the triode Q1 is cut off, and the C electrode of the triode Q1 outputs a low level, namely, the output of the no trigger pulse is represented; meanwhile, the junction between the CPU and the resistor R6 is also low level, the triode Q3 is cut off, the C pole of the triode Q3 is at high level because the DC power VCC and the resistor R5 provide current, the high level enables the triode Q4 to be conducted, so that the G pole of the trigger end of the controlled silicon K1 is connected to the ground, the G pole of the trigger end of the controlled silicon K1 is at low resistance state to the ground, the external interference signal to the G pole of the trigger end of the controlled silicon K1 is released by the triode Q4, and the controlled silicon K1 is ensured not to be triggered by mistake;
when a trigger pulse exists, the connection position of the CPU and the resistor R4 is in a high level, the triode Q2 is conducted, the C pole of the triode Q2 is in a low level, the triode Q1 is conducted, the C pole of the triode Q1 outputs a high level, the current is limited through the resistor R2, and the trigger pulse is provided for the silicon controlled rectifier K1; meanwhile, the junction between the CPU and the resistor R6 is also high level, the triode Q3 is conducted, the C electrode of the triode Q3 is low level, and the low level enables the triode Q4 to be cut off, so that the pulse current provided by the triode Q1 can only flow through the G electrode and the K electrode of the trigger end of the controlled silicon K1, and the controlled silicon K1 is triggered and conducted.
Fig. 2 is a schematic diagram of waveforms of the present invention, in which: the point A is the waveform of alternating current 220V voltage; point B is the zero crossing point of the alternating voltage; the point C is a trigger pulse of the controlled silicon K1, the trigger is started when the positive half cycle of the alternating current voltage is advanced for a certain time from the zero crossing point B of the alternating current, then the controlled silicon K1 starts to be conducted, and the controlled silicon K1 is naturally turned off when the zero crossing point B of the alternating current is reached; the point D is a current waveform after the thyristor K1 is triggered to be turned on, which is a current signal sent by the current signal sending circuit.
To sum up, the current signal transmitting circuit for the low-voltage power transformer area of the utility model has the advantages that when no trigger signal exists, the trigger circuit is in a low-resistance state, and the interference signal can be directly released, so that the current signal transmitting circuit is ensured not to be triggered and started by mistake; the utility model discloses the transmitted signal is stable, triggers without mistake, and the phenomenon is burnt out to no longer emergence circuit, and it is accurate to draw the topological diagram, reaches anticipated effect, uses more accurately, extensively in lean on platform district management.
The essential features, the basic principle and the advantages of the invention have been shown and described above. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only illustrative of the principles of the present invention, and that the present invention can be modified in various ways according to the actual situation without departing from the spirit and scope of the present invention, and these modifications and improvements are all within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A current signaling circuit for a low voltage power station, comprising: the circuit comprises a CPU, a load resistor R7, a thyristor K1, a capacitor C1, a resistor R1 and a thyristor trigger circuit; a live wire L of the alternating current power supply is connected with one end of a load resistor R7 through a fuse tube F1, the other end of the load resistor R7 is connected with an A pole of a controlled silicon K1, a K pole of the controlled silicon K1 is connected with a zero line N of the alternating current power supply, and a capacitor C1 is connected with a resistor R1 in series and then connected between the A pole and the K pole of the controlled silicon;
the silicon controlled trigger circuit comprises a direct current working power supply VCC, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a triode Q1, a triode Q2, a triode Q3 and a triode Q4, wherein the CPU is connected with one end of the resistor R4, the other end of the resistor R4 is connected with the B pole of the triode Q2, the C pole of the triode Q2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the B pole of the triode Q1, and the C pole of the triode Q1 is connected with the resistor R2; the CPU is further connected with one end of a resistor R6, the other end of the resistor R6 is connected with the B pole of a triode Q3, the C pole of the triode Q3 is respectively connected with the B poles of a resistor R5 and a triode Q4, the C pole of the triode Q4 is respectively connected with the G poles of a resistor R2 and a silicon controlled rectifier K1, and the E pole of the triode Q4 is connected with the zero line N of an alternating current power supply.
2. A current signaling circuit for a low voltage power station according to claim 1, wherein: the controllable silicon K1 is a power control device, and the controllable silicon K1 is used for sending on and off of current.
3. A current signaling circuit for a low voltage power station according to claim 1, wherein: the G pole of the thyristor K1 is the trigger terminal.
4. A current signaling circuit for a low voltage power station according to claim 1, wherein: the resistor R2 is connected with the G pole of the thyristor K1.
5. A current signaling circuit for a low voltage power station according to claim 1, wherein: the capacitor C1 is connected with the resistor R1 in series to form a protection circuit, and the thyristor K1 is prevented from being broken down by sharp pulses.
6. A current signaling circuit for a low voltage power station according to claim 1, wherein: and the CPU is connected with a low-voltage alternating-current voltage zero-crossing detection device.
7. A current signaling circuit for a low voltage power station according to claim 1, wherein: and the E pole of the triode Q1 and the resistor R5 are respectively connected with a direct current power supply VCC.
8. A current signaling circuit for a low voltage power station according to claim 1, wherein: the E pole of the triode Q2 and the E pole of the triode Q3 are both grounded.
9. A current signaling circuit for a low voltage power station according to claim 1, wherein: the triode Q1 is a PNP type triode, and the triode Q2, the triode Q3 and the triode Q4 are NPN type triodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921754652.9U CN211236008U (en) | 2019-10-18 | 2019-10-18 | Current signal sending circuit for low-voltage power distribution area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921754652.9U CN211236008U (en) | 2019-10-18 | 2019-10-18 | Current signal sending circuit for low-voltage power distribution area |
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| Publication Number | Publication Date |
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| CN211236008U true CN211236008U (en) | 2020-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921754652.9U Withdrawn - After Issue CN211236008U (en) | 2019-10-18 | 2019-10-18 | Current signal sending circuit for low-voltage power distribution area |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110579640A (en) * | 2019-10-18 | 2019-12-17 | 联桥科技有限公司 | current signal sending circuit for low-voltage power distribution area |
-
2019
- 2019-10-18 CN CN201921754652.9U patent/CN211236008U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110579640A (en) * | 2019-10-18 | 2019-12-17 | 联桥科技有限公司 | current signal sending circuit for low-voltage power distribution area |
| CN110579640B (en) * | 2019-10-18 | 2023-11-28 | 联桥科技有限公司 | Current signal transmitting circuit for low-voltage power station area |
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Effective date of registration: 20230710 Address after: Room 4010-4013, Zone E, Floor 4, Smart Island Building, No. 6, Middle Road East Road, Zhengdong New Area, Zhengzhou City, Henan Province, 450000 Patentee after: Guqiao information technology (Zhengzhou) Co.,Ltd. Address before: 461000 Northeast of the second floor of the main building of Zhongyuan Electric Goosennery Energy Saving Industrial Park, Xuchang City, Henan Province Patentee before: LIANQIAO TECHNOLOGY CO.,LTD. |
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Granted publication date: 20200811 Effective date of abandoning: 20231128 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20200811 Effective date of abandoning: 20231128 |