CN211235981U - Oscilloscope matrix scanning circuit with high reliability - Google Patents
Oscilloscope matrix scanning circuit with high reliability Download PDFInfo
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- CN211235981U CN211235981U CN201922024907.2U CN201922024907U CN211235981U CN 211235981 U CN211235981 U CN 211235981U CN 201922024907 U CN201922024907 U CN 201922024907U CN 211235981 U CN211235981 U CN 211235981U
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Abstract
A high-reliability oscilloscope matrix scanning circuit mainly comprises a matrix switch module, a first scanning module, a second scanning module, a power supply module and a control module. The application provides a matrix scanning circuit has carried out supplementary reinforcing to detecting level, jump signal, control chronogenesis from circuit structure, can improve oscilloscope keyboard scanning panel's reliability effectively under the condition that does not improve the cost, when reinforceing user experience, can also avoid the key string phenomenon that produces easily under the abominable service condition, guarantees effectively that the key-value of button or knob does not take place to lose, has very strong practical value.
Description
Technical Field
The invention relates to the technical field of oscilloscopes, in particular to a high-reliability oscilloscope matrix scanning circuit.
Background
The keyboard is a main man-machine conversation input device in electronic products such as computers, PCs, mobile phones, numerical control devices, testing instruments and the like, and as the functions of the electronic products are increased, the keyboard is required to provide enough keys to complete control of complex and various functions, and the current matrix keyboard mainly scans the keys on the keyboard through an internal matrix scanning circuit so as to determine the positions of the keys.
For example, in an oscilloscope, a key and a knob on a control panel are often used for parameter adjustment and input control, so as to achieve the purpose of man-machine interaction operation. The matrix keyboard can be formed by a plurality of keys and a plurality of knobs on the control panel, the stability of the matrix keyboard directly influences the operation experience of a user, when the keys or the knobs are out of order, correct measurement parameters cannot be set for the oscilloscope, the inaccurate situation of a test result can be caused, and therefore, the technology which is worthy of paying attention to how to improve the input reliability of the oscilloscope matrix keyboard still exists.
Both the traditional oscilloscope and the modern oscilloscope need a control panel to carry out man-machine interaction operation, and under some severe use conditions or long-term high-intensity application states, the phenomenon of key string of individual keys on the control panel and the phenomenon of key value loss of individual knobs can occur, so that the key switching or the knob input process is wrong, the oscilloscope cannot be manually operated and controlled, and the user experience is seriously influenced.
Disclosure of Invention
The invention mainly solves the technical problem of how to enhance the reliability of key switching and knob input of a matrix scanning circuit in an oscilloscope so as to improve the operation experience of a user.
In order to solve the above technical problem, the present application provides a highly reliable oscilloscope matrix scanning circuit, including: the matrix switch module comprises a plurality of switch components distributed according to rows and columns, wherein a first scanning channel is formed on each row of switch components, and a second scanning channel is formed on each column of switch components; the first scanning module comprises a communication end and a plurality of first detection ends, and the first detection ends are connected with the first scanning channels in a one-to-one correspondence manner; the first scanning module is used for connecting each first detection end to the communication end one by one and outputting a signal level detected by the first detection end by using the communication end; the second scanning module comprises a grounding end and a plurality of second detection ends, and the plurality of second detection ends are correspondingly connected with the second scanning channels one by one; the second scanning module is used for connecting each second detection end to the grounding end one by one; the power module outputs high level, the output end of the power module is provided with a plurality of pull-up resistors connected in parallel, each pull-up resistor is connected with each first scanning channel in a one-to-one correspondence mode, and the resistance range of each pull-up resistor in the power module is 3.0-4.0K omega; the control module is in signal connection with the first scanning module and the second scanning module; the control module is configured to configure the second scanning module to switch on each of the first detection ports one by one in a process of switching on any one of the second detection ports.
The switch component comprises at least one input end and one output end, the input end of the switch component is connected with the first scanning channel corresponding to the row, and the output end of the switch component is connected with the second scanning channel corresponding to the column.
The switch component is a key or a knob, and the matrix switch module is a matrix circuit formed by a plurality of keys and/or a plurality of knobs.
The input end of each knob is connected with a diode in series, and the diode is used for assisting to enhance the jump signal of the knob when the knob acts.
The diode is a Schottky diode and is used for reducing the jump time of the knob when the knob acts.
The control module comprises a first counter and a second counter, and the first counter and the second counter comprise a clock end and a sending end; the first scanning module and the second scanning module respectively comprise a chip selection end; the clock end of the first counter is connected with an external clock source, and the sending end is connected with the chip selection end of the first scanning module; the first counter is used for carrying out cycle counting by utilizing the received clock signals, and generating a first chip selection signal after each counting so as to configure the first scanning module, so that the first scanning module is communicated with the corresponding first detection end and the corresponding communication end; the counting value of the first counter is matched with the port number of the first detection end and the serial number of the first scanning channel; the clock end of the second counter is connected with the sending end of the first counter to form a cascade counting state, and the sending end is connected with the chip selection end of the second scanning module; the second counter is used for carrying out cycle counting by utilizing the first chip selection signal, and generating a second chip selection signal after each counting so as to configure the second scanning module, so that the second scanning module is connected with the corresponding second detection end and the grounding end; and the count value of the second counter is matched with the port number of the second detection end and the serial number of the second scanning channel.
The control module further comprises a processor, wherein the processor comprises a clock end, a synchronization end and a receiving end; the first counter and the second counter also comprise synchronous ends; the clock end of the processor is connected with the clock end of the first counter and used for providing a clock signal; the synchronization end of the processor is connected with the synchronization end of the first counter and the synchronization end of the second counter, and is used for providing a synchronization signal, wherein the synchronization signal is used for synchronously starting counting operation and triggering the second counter to perform one-time counting when the first counter performs one-cycle counting; the receiving end of the processor is connected with the communication end of the first scanning module and is used for receiving the signal level output by the first scanning module; and when the signal level is low, the processor determines the count value of the first counter and the count value of the second counter according to the provided clock signal and the synchronization signal, so as to determine the key value of any one switch component in the matrix switch module when the switch component acts.
When the second counter executes a round of circulation counting, the control module completes a round of scanning on the matrix switch module, and the time range for completing the round of scanning is 1ms-20 ms.
The first scanning module and the second scanning module both adopt multiplexers, and the first counter and the second counter both adopt binary counters.
The beneficial effect of this application is:
the matrix scanning circuit of the oscilloscope with high reliability mainly comprises a matrix switch module, a first scanning module, a second scanning module, a power supply module and a control module, wherein the matrix switch module comprises a plurality of switch components distributed according to rows and columns, a first scanning channel is formed on each row of switch components, and a second scanning channel is formed on each column of switch components; the first scanning module comprises a communication end and a plurality of first detection ends, the first detection ends are correspondingly connected with the first scanning channels one by one, and the first scanning module is used for connecting each first detection end to the communication end one by one and outputting a signal level detected by the first detection end by using the communication end; the second scanning module comprises a grounding end and a plurality of second detection ends, the plurality of second detection ends are correspondingly connected with the second scanning channels one by one, and the second scanning module is used for connecting each second detection end to the grounding end one by one; the power supply module outputs high level, the output end of the power supply module is provided with a plurality of pull-up resistors connected in parallel, and each pull-up resistor is connected with each path of first scanning channel in a one-to-one correspondence manner; the control module is in signal connection with the first scanning module and the second scanning module, and the control module is used for configuring the second scanning module to switch on each first detection port one by one in the process of switching on any second detection port. On the first hand, the first scanning module and the second scanning module are adopted to respectively detect the first scanning channel and the second scanning channel formed in the matrix switch module, which is equivalent to respectively scanning the row channel and the column channel, thus being beneficial to improving the scanning efficiency and improving the stable output performance of the scanning result; in the second aspect, because the input end of each knob in the matrix switch module is connected with a diode in series, the jump signal of the knob can be enhanced in an auxiliary manner when the knob acts, the time delay is reduced, and the requirement that the jump signal is triggered in time is favorably met; in the third aspect, because the diode connected in series on each knob is set as the Schottky diode, the voltage drop characteristic of the Schottky diode is fully utilized, the jump time of the knob during action can be reduced to the maximum extent, and the improvement of the response sensitivity of the matrix scanning circuit is facilitated; in the fourth aspect, because the output end of the power supply module is provided with the plurality of pull-up resistors which are connected in parallel and the resistance values of the pull-up resistors are properly set, the detection signal in the matrix scanning module reaches a proper level state, the adverse effect of an interference signal is weakened under the condition that the normal action of a key/knob is not influenced, and the accuracy of switch response is ensured; in a fifth aspect, a first counter and a second counter are cascaded in a control module, and the correct time sequence of chip selection signals generated by the first counter and the second counter is maintained from a hardware structure, so that the control stability of the control module is provided; in a sixth aspect, the matrix scanning circuit provided by the application performs auxiliary enhancement on detection level, hopping signal and control time sequence from the aspect of circuit structure, can effectively improve the reliability of the oscilloscope keyboard scanning panel under the condition of not increasing cost, can avoid the phenomenon of key string easily generated under severe use conditions while enhancing user experience, effectively ensures that the key value of a key or a knob is not lost, and has very high practical value.
Drawings
FIG. 1 is a schematic diagram of a matrix scanning circuit of an oscilloscope according to the present application;
FIG. 2 is a circuit diagram of an oscilloscope matrix scanning circuit in one embodiment;
FIG. 3 is a schematic diagram of a key structure according to an embodiment;
FIG. 4 is a schematic view of a knob according to an embodiment;
FIG. 5 is a schematic diagram illustrating the counting principle of the first counter and the second counter in one embodiment;
FIG. 6 is a signal test chart of a prior art matrix keyboard during a switch actuation;
fig. 7 is a signal test chart of the matrix scanning circuit during the switching operation in the present application.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
Referring to fig. 1 and fig. 2, the present application discloses a highly reliable oscilloscope matrix scanning circuit, which includes a matrix switch module 11, a first scanning module 12, a second scanning module 13, a power supply module 14, and a control module 15, which are described below.
The matrix switch module 11 comprises a plurality of switch blocks (blocks as indicated by reference numerals 111 and 112) arranged in rows and columns, the switch blocks of each row being formed with a first scan channel (row-wise sense lines as indicated by reference numerals W0 to W8) and the switch blocks of each column being formed with a second scan channel (column-wise sense lines as indicated by reference numerals L0-L7).
The first scanning module 12 includes a communication terminal D1 and a plurality of first detecting terminals (as indicated by T0 to T8), which are connected to the first scanning channels one by one. The first scanning module 12 is configured to switch each first detecting terminal (e.g. T0) to the communication terminal D1 one by one, and output the signal level detected by the first detecting terminal through the communication terminal D1, i.e. switch the signal level on one of the first scanning channels to the communication terminal D1, so as to transmit the signal to the control module 15 through the communication terminal D1.
The second scan module 13 includes a ground terminal E1 and a plurality of second detection terminals (e.g., reference symbols Q0 to Q7), which are connected to the respective second scan channels in a one-to-one correspondence. The second scan module 13 is configured to turn on each second detection terminal (e.g., Q0) to the ground terminal E1 one by one, that is, turn on the signal level of one of the second scan channels to the ground terminal E1, so as to set the level of the one of the second scan channels to the ground level, such as a zero level.
The power module 14 outputs the high level VCC, and the output terminal of the power module 14 is provided with a plurality of pull-up resistors (as denoted by reference symbols R1 to R9) connected in parallel, and each pull-up resistor is connected to each of the first scanning channels (as denoted by reference symbols W0 to W8) in a one-to-one correspondence manner, so that the level equal to the high level VCC is maintained on the first scanning channel under normal conditions.
The control module 15 is in signal connection with the first scanning module 12 and the second scanning module 13, where the control module 15 is configured to configure the second scanning module 13 to switch on each of the first detecting ports (e.g. reference numeral T0) one by one during the process of switching on any one of the second detecting ports (e.g. reference numeral Q0). The control sequence can be completed by cascaded timers, the hardware timing function can be realized by only providing an additional clock signal, no special control logic is needed, and the specific principle is explained below.
In the present embodiment, the switching unit illustrated with reference to reference numerals 111 and 112 in fig. 2 should include at least one input terminal and one output terminal, the input terminal of the switching unit is connected to the first scanning channel corresponding to the row, and the output terminal of the switching unit is connected to the second scanning channel corresponding to the column.
In a specific embodiment, the switch component involved in the present embodiment may be a key or a knob, so that the matrix switch module 11 is a matrix circuit formed by a plurality of keys and/or a plurality of knobs. For example, as shown in fig. 2, the matrix switch module 11 includes a plurality of knobs distributed in rows and columns, and a plurality of keys distributed in rows and columns, where the knobs are used for adjusting the size of the switch trigger amount, and the keys are used for realizing one-time triggering.
In one embodiment, the switch unit 111 may be a key illustrated in fig. 3, and has an input terminal connected to the first scanning channel W5 and an output terminal connected to the second scanning channel L5, and the first scanning channel W5 is turned on with the second scanning channel L5 when the key is pressed, so that the level of the first scanning channel W5 follows the level of the second scanning channel L5. Since the key is a common switch device, which belongs to the prior art, the structure and the operation principle thereof will not be explained in detail here.
In one embodiment, the switch assembly 112 may be a knob as illustrated in FIG. 4, with three inputs connected to the first scanning channels W6, W7, W8, respectively, and an output connected to the second scanning channel L6. When the knob is pressed down, the first scanning channel W6 is communicated with the second scanning channel L6, so that the function of a common key is realized; when the knob is rotated, W7 and L6 can be switched on or off, and W8 and L6 can be switched on or off, so that the output effects of Gray codes 11, 01, 00 and 10 are realized, and the rotating direction and the triggering amount of the knob are judged. Since the knob is a common switch device, and belongs to the prior art, the structure and the operation principle thereof will not be described in detail here.
Further, referring to fig. 2 and 4, diodes (e.g., 113, 114) are connected in series to the input terminals (e.g., W7, W8) of each knob, and are used to assist in enhancing the jump signal of the knob when the knob is actuated. In order to generate better jump signals, a diode connected in series with the input end of the knob can adopt a Schottky diode, and the jump time of the knob when action occurs is reduced.
It will be appreciated by those skilled in the art that the use of the low dropout schottky diode can reduce the transition time of the knob from 0 to 1, while it can be seen from fig. 4 that there is a diode drop from the low level of the knob to GND. Taking the level standard of LVCMOS as an example, Vcc=3.3V，VIH>=2.0V，VIL<The voltage drop of the ordinary diode is about 0.6V, and the voltage drop of the Schottky diode is about 0.3V, so that the possibility of logic misjudgment is greatly reduced, and the stability of knob action is improved.
In the present embodiment, referring to fig. 2, the control module 15 may include a first counter 151 and a second counter 152, and each of the first counter 151 and the second counter 152 includes a clock terminal (e.g., reference numerals K1, K2) and a transmitting terminal (e.g., reference numerals S1, S2). In addition, the first scan module 12 and the second scan module 13 each further include a chip select terminal (e.g., N1, N2).
The clock terminal K1 of the first counter 151 is connected to an external clock source through a clock signal line CLK1, and the transmitting terminal S1 is connected to the chip select terminal N1 of the first scan module 12; the first counter 151 is configured to count cycles with the received clock signal, and generate a first chip select signal after each count to configure the first scan module 12, so that the first scan module turns on the corresponding first detection terminal (e.g. any one of the reference symbols T0 to T8) and the communication terminal D1; further, the count value of the first counter 151 matches the port number of the first detection terminal (the port numbers may be denoted by T0 to T8, respectively), the sequence number of the first scan channel (the sequence numbers may be denoted by reference numerals W0 to W8, respectively), so that T0 connects W0, and so on.
The clock terminal K2 of the second counter 152 is connected to one signal line of the transmitting terminals S1 of the first counter 151 through a clock signal line CLK2, so that the two counters form a cascade counting state, and the transmitting terminal S2 of the second counter 152 is connected to the chip select terminal N2 of the second scan module 13. The second counter 152 is configured to count cyclically with the first chip select signal, and generate a second chip select signal after each counting to configure the second scan module 13, so that the second scan module 13 turns on the corresponding second detection terminal (e.g. any one of the ports Q0 to Q7) and the ground terminal E1. Further, the count value of the second counter 152 matches the port number of the second detection terminal (the port numbers may be represented by Q0 to Q7, respectively), the sequence number of the second scan channel (the sequence numbers may be represented by L0 to L7, respectively), so that Q0 connects L0, and so on.
Further, the control module 15 further includes a processor 153, where the processor 153 includes a clock terminal K3, a synchronization terminal C3, and a receiving terminal D2; in addition, the first counter 151 and the second counter 152 each further include a synchronization terminal (e.g., reference numerals C1, C2). The clock terminal K3 of the processor 153 is connected to the clock terminal K1 of the first counter 151 for providing a clock signal; the synchronizing terminal C3 of the processor 153 is connected to the synchronizing terminal C1 of the first counter 151 and the synchronizing terminal C2 of the second counter 152, and is used for providing a synchronizing signal, where the synchronizing signal is used for synchronously starting a counting operation and triggering the second counter 152 to perform a counting operation when the first counter 151 performs a round of counting.
In addition, the receiving end D2 of the processor 153 is connected to the communication end D1 of the first scanning module 12, and is used for receiving the signal level output by the first scanning module 12. The processor 153 determines the count value of the first counter 151 and the count value of the second counter 152 based on the clock signal and the synchronization signal supplied when the received signal level is low, thereby determining the key value of any one of the switching elements in the matrix switching module 11 at the time of the operation.
In the present embodiment, the resistance of each pull-up resistor (e.g., R1-R9) in the power module 14 is in the range of 3.0-10K Ω. The pull-up resistor with 10K omega or even higher resistance value is selected in the conventional scanning circuit, because the higher resistance value can further pull up the level of the line scanning circuit, the signal jump generated when the key acts is more obvious, and the signal jump is easier to be received by the scanning module. However, in order to achieve a good high-level output effect and a good response effect of the switching element, the pull-up resistors are set to 3.0 to 4.0K Ω, and preferably each of the pull-up resistors is set to 3.1K Ω. Therefore, the level on the line scanning line can be effectively reduced, the detection signal in the matrix scanning module reaches a proper level state, the adverse effect of an interference signal is weakened under the condition that the normal action of a key/knob is not influenced, and the accuracy of switch response is ensured.
In this embodiment, the first scanning module 12 and the second scanning module 13 may both adopt a multiplexer, for example, the first scanning module 12 adopts a 16-way analog switch 74HC4067, and the second scanning module 13 adopts an 8-way analog switch 74HC 4051.
In the present embodiment, the first counter 151 and the second counter 152 may each adopt a binary counter, such as the binary counter 74HC 393.
In this embodiment, the processor 153 may be a logic processing chip such as a CPU, an MCU, etc., and since such chips generally have functions of outputting a clock signal, outputting a synchronization signal, and detecting an input level, functions implemented by the clock terminal K3, the synchronization terminal C3, and the receiving terminal D2 of the processor 153 are all in the prior art, and will not be described in detail herein.
In the present application, the second counter 152 performs one counting, only one of the second scanning channels (e.g. reference L7) is turned on with ground, and the first counter 151 counts cyclically during the period that L7 is turned on with ground through Q7, so that the receiving end D2 of the processor 153 is relied on to detect whether there is a low level channel in the first scanning channels W0 to W8, for example, the first scanning channel W0 has a low level, and then the button/knob indicating the intersection position of the first scanning channel W0 and the second scanning channel L7 is pressed. For example, in the counting timing of the first counter 151 and the second counter 152 shown in fig. 5, the second counter 152 has counted 8 times in the process of performing one counting by the first counter 151.
It can be understood that, when the second counter 152 performs one round of cycle counting, the control module 153 completes one round of scanning on the matrix switch module 11, and to achieve better scanning effect, the time range for completing one round of scanning may be set to be 1ms-20ms, which is much shorter than the time of any one switch component of a human.
In the present application, the process of the processor 153 knowing the key values of the switch components in the matrix scanning module can refer to the scanning principle of the existing matrix keyboard: the method comprises the steps of firstly enabling three horizontal rows or three vertical columns to output high level, enabling the other three horizontal rows or the three vertical columns to be input modes, if scanning the high level, indicating that a key is pressed down on the row or the column, then switching input and output, scanning the other three rows to obtain other coordinates, and determining the pressed position of the key.
Those skilled in the art will appreciate that the following advantages can be realized using the teachings provided herein. (1) The first scanning module and the second scanning module are adopted to respectively detect the first scanning channel and the second scanning channel formed in the matrix switch module, which is equivalent to respectively scanning the row channel and the column channel, thus being beneficial to improving the scanning efficiency and improving the stable output performance of the scanning result; (2) the input end of each knob in the matrix switch module is connected with a diode in series, so that a jump signal of the knob during action can be enhanced in an auxiliary manner, time delay is reduced, and the requirement that the jump signal is triggered in time is met; (3) the diode connected in series on each knob is set as a Schottky diode, the voltage drop characteristic of the Schottky diode is fully utilized, the jump time of the knob during action can be reduced to the maximum extent, and the improvement of the response sensitivity of the matrix scanning circuit is facilitated; (4) because the output end of the power supply module is provided with the plurality of pull-up resistors which are connected in parallel and the resistance values of the pull-up resistors are properly set, the detection signal in the matrix scanning module reaches a proper level state, the adverse effect of an interference signal is weakened under the condition that the normal action of a key/knob is not influenced, and the accuracy of switch response is ensured; (5) the first counter and the second counter are cascaded in the control module, and the correct time sequence of chip selection signals generated by the first counter and the second counter is maintained from a hardware structure, so that the control stability of the control module is provided; (6) the application provides a matrix scanning circuit has carried out supplementary reinforcing to detecting level, jump signal, control chronogenesis from circuit structure, can improve oscilloscope keyboard scanning panel's reliability effectively under the condition that does not improve the cost, when reinforceing user experience, can also avoid the key string phenomenon that produces easily under the abominable service condition, guarantees effectively that the key-value of button or knob does not take place to lose, has very strong practical value.
Those skilled in the art can understand that the technical solution of the present application can be regarded as an invention creation generated by improvement of the prior art, the content of the prior art can refer to patent document (CN 200920350704.6), and the essential improvement of the technical solution of the present application is that: (1) the diode connected in series on the existing knob is replaced by a Schottky diode; (2) the 10k omega resistor used in the existing power supply is replaced by a pull-up resistor with the value range of 3.0-3.1k omega. Therefore, the invention concept of the technical scheme of the application is as follows: the matrix scanning circuit of the oscilloscope in the past is improved, and the working stability of the scanning circuit is enhanced mainly by changing the performance parameters and types of some original components, so that the accidental key string phenomenon of a switch component is avoided, the reliability of key switching and knob input of the matrix scanning circuit in the oscilloscope is enhanced, and the operation experience of a user is improved. The reason for such improvement will be described in detail hereinafter.
Aiming at the technical characteristics of the first substantial improvement, the prior art often adopts a common diode without special requirements, and the function of the diode is also only one-way conduction, however, the application clearly defines that the diode connected in series on the knob adopts a schottky diode, the low-voltage drop characteristic of the schottky diode except for single-phase conduction can be fully exerted when the diode is applied, when the low-voltage-difference schottky diode is used, the jump time of the knob from 0 to 1 can be shortened, and the voltage drop of the knob from the low level to the GND can be reduced, for example, the level standard of LVCMOS, Vcc =3.3V, VIH > =2.0V, VIL =0.7V, the common diode drop is about 0.6V, and the voltage drop of the schottky diode is about 0.3V, so that the possibility of logic misjudgment is greatly reduced, and the stability of the knob action is favorably improved. Because the diode connected in series on each knob is set as the Schottky diode, the voltage drop characteristic of the Schottky diode is fully utilized, the jump time of the knob during action can be reduced to the maximum extent, and the improvement of the response sensitivity of the matrix scanning circuit is facilitated. Therefore, the technical characteristics achieve the technical effects which are not achieved by similar characteristics in the prior art.
Aiming at the technical characteristics of the second point substantial improvement, in the prior art, a 10k omega resistor frequently used by technicians is adopted when a pull-up resistor is arranged for a matrix keyboard, so that a higher default level is maintained on a row scanning line, however, in the technical scheme of the application, the 10k omega resistor used on a power supply is replaced by the pull-up resistor with the value range of 3.0-3.1k omega, so that the level on the row scanning line can be reduced, a detection signal in a matrix scanning module reaches a proper level state, the adverse effect of an interference signal is weakened under the condition that the normal action of a key/knob is not influenced, and the accuracy of switch response is ensured.
In order to verify the application advantages of the technical scheme of the present application, a comparative test is performed, in which not only the signal test is performed on the existing matrix keyboard (for example, the keyboard scanning circuit adopted in patent document CN 200920350704.6), but also the signal test is performed on the oscilloscope matrix scanning circuit claimed in the present application.
As can be seen from fig. 6, in the conventional matrix keyboard, under the combined influence of the internal resistance of the switch components (such as keys, knobs, etc.) and the driving capability of the circuit, some switch components may transmit interference signals into the circuit. Normally, after the switch component acts, the detection signal on the scanning channel is pulled low and is smaller than the trigger signal referred by the processor, and the switch component is considered to be pressed. If a knob is stuck in a state of 00 or 10, the circuit needs to recover from 0 to 1, and noise generated by the interference signal during the operation of the knob is added, so that the processor detects a low level lower than the trigger signal again, which may cause a logic misjudgment and cause a phenomenon of loss of the key value of the knob.
However, as can be seen from fig. 7, the matrix scanning circuit disclosed in the present application does not generate a low level again due to the dual effects of the recovery time of the switch component and the interference signal, and can well overcome the phenomenon of key value loss, so that the matrix scanning circuit has the operating characteristics of high reliability and high stability, and is suitable for being popularized and applied in high-precision test instruments such as an oscilloscope. In addition, although the technical scheme disclosed in the application is simpler in improvement compared with the prior art, unexpected technical effects can be achieved, and obvious application advantages are brought.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (5)
1. A highly reliable oscilloscope matrix scanning circuit, comprising:
the matrix switch module comprises a plurality of switch components distributed according to rows and columns, wherein a first scanning channel is formed on each row of switch components, and a second scanning channel is formed on each column of switch components;
the first scanning module comprises a communication end and a plurality of first detection ends, and the first detection ends are connected with the first scanning channels in a one-to-one correspondence manner; the first scanning module is used for connecting each first detection end to the communication end one by one and outputting a signal level detected by the first detection end by using the communication end;
the second scanning module comprises a grounding end and a plurality of second detection ends, and the plurality of second detection ends are correspondingly connected with the second scanning channels one by one; the second scanning module is used for connecting each second detection end to the grounding end one by one;
the power supply module outputs high level, the output end of the power supply module is provided with a plurality of pull-up resistors connected in parallel, and each pull-up resistor is connected with each path of the first scanning channel in a one-to-one correspondence manner; the resistance range of each pull-up resistor in the power module is 3.0-4.0K omega;
the control module is in signal connection with the first scanning module and the second scanning module; the control module is used for configuring the second scanning module to switch on each first detection port one by one in the process of switching on any one second detection port;
the switching component comprises at least one input end and one output end, the input end of the switching component is connected with the first scanning channel corresponding to the row, and the output end of the switching component is connected with the second scanning channel corresponding to the column; the switch component is a key or a knob, and the matrix switch module is a matrix circuit formed by a plurality of keys and/or a plurality of knobs; the input end of each knob is connected with a diode in series, and the diode is used for assisting to enhance a jump signal of the knob when the knob acts; the diode is a Schottky diode and is used for reducing the jump time of the knob when the knob acts.
2. The oscilloscope matrix scanning circuit according to claim 1, wherein said control module comprises a first counter and a second counter, each of said first counter and said second counter comprising a clock terminal and a transmit terminal; the first scanning module and the second scanning module respectively comprise a chip selection end;
the clock end of the first counter is connected with an external clock source, and the sending end is connected with the chip selection end of the first scanning module; the first counter is used for carrying out cycle counting by utilizing the received clock signals, and generating a first chip selection signal after each counting so as to configure the first scanning module, so that the first scanning module is communicated with the corresponding first detection end and the corresponding communication end; the counting value of the first counter is matched with the port number of the first detection end and the serial number of the first scanning channel;
the clock end of the second counter is connected with the sending end of the first counter to form a cascade counting state, and the sending end is connected with the chip selection end of the second scanning module; the second counter is used for carrying out cycle counting by utilizing the first chip selection signal, and generating a second chip selection signal after each counting so as to configure the second scanning module, so that the second scanning module is connected with the corresponding second detection end and the grounding end; and the count value of the second counter is matched with the port number of the second detection end and the serial number of the second scanning channel.
3. The oscilloscope matrix scanning circuit according to claim 2, wherein the control module further comprises a processor, the processor comprising a clock terminal, a synchronization terminal, and a receiving terminal; the first counter and the second counter also comprise synchronous ends;
the clock end of the processor is connected with the clock end of the first counter and used for providing a clock signal;
the synchronization end of the processor is connected with the synchronization end of the first counter and the synchronization end of the second counter, and is used for providing a synchronization signal, wherein the synchronization signal is used for synchronously starting counting operation and triggering the second counter to perform one-time counting when the first counter performs one-cycle counting;
the receiving end of the processor is connected with the communication end of the first scanning module and is used for receiving the signal level output by the first scanning module; and when the signal level is low, the processor determines the count value of the first counter and the count value of the second counter according to the provided clock signal and the synchronization signal, so as to determine the key value of any one switch component in the matrix switch module when the switch component acts.
4. The oscilloscope matrix scanning circuit according to claim 3, wherein said control module performs one scan round on said matrix switch module while said second counter performs one cycle count, the time for completing one scan round being in the range of 1ms to 20 ms.
5. The oscilloscope matrix scanning circuit according to any one of claims 2-4, wherein said first scanning module and said second scanning module each employ a multiplexer, and wherein said first counter and said second counter each employ a binary counter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113792001A (en) * | 2021-09-06 | 2021-12-14 | 西安易朴通讯技术有限公司 | SAS EXP board card, back board and hot plug method |
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| CN113792001A (en) * | 2021-09-06 | 2021-12-14 | 西安易朴通讯技术有限公司 | SAS EXP board card, back board and hot plug method |
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