CN211184098U

CN211184098U - Readout circuit, image sensor, and electronic apparatus

Info

Publication number: CN211184098U
Application number: CN202020015653.8U
Authority: CN
Inventors: 李亮
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2019-06-20
Filing date: 2019-06-20
Publication date: 2020-08-04
Anticipated expiration: 2029-06-20
Also published as: CN210007779U

Abstract

The embodiment of the application provides a reading circuit, an image sensor and electronic equipment, which can effectively reduce the area of the image sensor and the overhead on power consumption. The readout circuit includes: a plurality of capacitors, a switching circuit, and an output circuit; wherein the plurality of capacitors are connected to the output circuit through the switching circuit; a plurality of capacitors for storing output signals of the plurality of pixel circuits, respectively; the output circuit is used for outputting the signals stored by the plurality of capacitors one by one through the switch circuit.

Description

Readout circuit, image sensor, and electronic apparatus

The application is a divisional application of the utility model with application date of 2019, 6 and 20, application number of 201920940140.5, and name of "read-out circuit, image sensor and electronic equipment".

Technical Field

The embodiments of the present application relate to the technical field of readout circuits, and more particularly, to a readout circuit, an image sensor, and an electronic device.

Background

An image sensor is a device that converts an optical signal into an electrical signal. An image sensor generally includes a pixel circuit, a readout circuit, an analog-to-digital conversion circuit, and a digital processing circuit, wherein the pixel circuit can convert a sensed optical signal into an electrical signal and input the electrical signal to the readout circuit, the readout circuit can amplify and read out the electrical signal output by the pixel circuit, the analog-to-digital conversion circuit can convert an analog signal output by the readout circuit into a digital signal, and the digital processing circuit can perform arithmetic processing on the digital signal output by the analog-to-digital conversion circuit.

With the development of society, the area and power consumption of image sensors are receiving more and more attention. Therefore, how to reduce the area and power consumption of the image sensor is an urgent problem to be solved.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a reading circuit, an image sensor and an electronic device, which can effectively reduce the area of the image sensor and the overhead on power consumption.

In a first aspect, a readout circuit is provided, including: a plurality of capacitors, a switching circuit, and an output circuit; wherein the plurality of capacitors are connected to the output circuit through the switching circuit; the plurality of capacitors are used for respectively storing output signals of a plurality of pixel circuits; the output circuit is used for outputting the signals stored by the plurality of capacitors one by one through the switch circuit.

In some possible embodiments, the switch circuit includes a plurality of switches, the plurality of switches correspond to the plurality of capacitors in a one-to-one correspondence, and the output circuit is configured to output the signals stored by the plurality of capacitors one by turning on the plurality of switches one by one.

In some possible embodiments, when the output circuit is configured to output the signal stored in the ith capacitor of the plurality of capacitors, the switch corresponding to the ith capacitor is turned on, and the switches in the switch circuit other than the switch corresponding to the ith capacitor are turned off.

In some possible embodiments, the plurality of pixel circuits are pixel circuits in the same direction.

In some possible embodiments, the number of the plurality of capacitors is less than or equal to the number of pixel circuits in the same direction.

In some possible embodiments, the plurality of capacitors are used to sample and store the output signals of the plurality of pixel circuits at the same time.

In some possible embodiments, all of the switches in the switch circuit are turned on when the plurality of capacitors simultaneously sample the output signals of the plurality of pixel circuits.

In some possible embodiments, the output circuit includes an operational amplifier for amplifying and outputting the signals stored by the plurality of capacitors.

In some possible embodiments, the output circuit further comprises: a feedback capacitor, a first switch, a second switch, and a third switch; the two ends of the first switch are respectively connected to the input end and the output end of the operational amplifier, the left pole plate of the feedback capacitor is connected to the input end of the operational amplifier, the right plate of the feedback capacitor is connected to the output end of the operational amplifier through a third switch, and the two ends of the second switch are respectively connected to the right pole plate of the feedback capacitor and the voltage source.

In a second aspect, an image sensor is provided, comprising the readout circuit of the first aspect or any possible implementation manner of the first aspect.

In a third aspect, an electronic device is provided, which includes the first aspect or the readout circuit in any possible implementation manner of the first aspect.

In the above technical solution, the readout circuit includes a plurality of (e.g., S) capacitors, so that output signals of the S pixel circuits can be independently stored and then output one by one, so that the S pixel circuits can share one readout circuit, and thus, the number of readout circuits in the image sensor can be reduced to 1/S. Due to the small size of the capacitor in the readout circuit, the area of the readout circuit added after adding the capacitor is negligible. In addition, the power consumption in the readout circuit mainly comes from the output circuit, and the power consumption of the readout circuit is almost unchanged after the capacitor is added, so that the area and the power consumption of the image sensor can be reduced to 1/S.

Drawings

Fig. 1 is a schematic diagram of an application of a conventional readout circuit.

Fig. 2 is a schematic diagram of a conventional readout circuit.

Fig. 3 is a timing chart of a control method corresponding to the readout circuit shown in fig. 1 and 2.

FIG. 4 is a schematic diagram of a sensing circuit according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of a readout circuit according to an embodiment of the present application.

Fig. 6 is a schematic diagram of an application of the sensing circuit shown in fig. 5.

Fig. 7 is a timing chart of a control method corresponding to the readout circuit shown in fig. 5 and 6.

Fig. 8 is a schematic structural diagram of another readout circuit according to an embodiment of the present application.

Fig. 9 is a schematic diagram of an application of the sensing circuit shown in fig. 8.

Fig. 10 is a schematic structural diagram of a super-pixel circuit according to an embodiment of the present application.

Fig. 11 is a schematic block diagram of an electronic device of an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of an application of a conventional readout circuit 100. In fig. 1, one readout circuit is connected to n pixel circuits in one row, and the output of the pixel circuit is the input of the readout circuit. The operation of the sensing circuit 100 is described below with reference to fig. 2 and 3. Fig. 2 is a schematic structural diagram of the readout circuit 100 in fig. 1, and fig. 3 is a timing diagram of a control method corresponding to the readout circuit 100.

As shown in FIG. 2, the readout circuit 100 can be mainly composed of 6 parts of (i) an input capacitor C ₁An input capacitor C ₁Has a capacitance of C ₁feedback capacitor C ₂Feedback capacitor C ₂Has a capacitance of C ₂operational amplifier (OPA) having an OPA gain of-A, ideally ∞ A, and an OPA input voltage of V _IOutput voltage of V _OUT④ sampling switch SW ₁，SW₁the control signal of (C) L K _Sone SW of two hold switches ₂，SW₂the control signal is C L K _H1⑥ one SW of two hold switches ₃，SW₃the control signal of (C) L K _H2. For convenience of description, the aforementioned 3 switches are each defined as: the control signal is conducted when the level is high.

As can be seen in connection with the timing diagram of fig. 3:

at time t1, C L K _Schange from low to high, C L K _H1is high level, C L K _H2At a low level, at this time SW ₁Start to conduct, SW ₂On, SW ₃Is turned off, and SW is a period of t1 to t2 ₁、SW₂And SW ₃The state of (2) is maintained and the circuit operates in the sampling phase. The feedback may be such that the input voltage V of the OPA in the ideal case is _IMaintaining at a common mode voltage, and setting the common mode voltage of OPA to V _CMThe input signal of the sensing circuit 100 is V from t1 to t2 _IN1Then input into a capacitor C ₁The charge stored on the memory cell satisfies: (V) _IN1-V_CM)*C₁Feedback capacitor C ₂The charge stored on the memory cell satisfies: (V) _REF-V_CM)*C₂. Wherein, V _REFIs the voltage of the voltage source.

then, in the period from t2 to t3, C L K _SFrom a high level to a low level, CLK_H1from high to low, C L K _H2Changes from low to high, so SW at t3 ₁Is turned off, SW ₂Is turned off, SW ₃Starts to conduct, and SW is a period of t3 to t4 ₁、SW₂And SW _{3 is}The state remains unchanged and the circuit operates in the holding phase. The feedback may be such that the OPA input voltage V in the ideal case is _IMaintained at a common mode voltage V _CMLet the input voltage of OPA be V in the period from t3 to t4 _IN2Then input into a capacitor C ₁The charge stored on the memory cell can satisfy: (V) _IN2-V_CM)*C₁Feedback capacitor C ₂The charge stored on the memory cell can satisfy: (V) _OUT-V_CM)*C₂。

During the switching from the sampling phase to the holding phase, the input capacitor C ₁Right plate and feedback capacitor C ₂The left plate of (2) has no charge path, so according to the charge conservation principle, the following are provided:

(V_IN2-V_CM)*C₁+(V_OUT-V_CM)*C₂＝(V_IN1-V_CM)*C₁+(V_REF-V_CM)*C₂(1)

From equation (1) we can obtain:

finally, in the period t4 to t5, C L K _H2from high to low, C L K _H1change from low to high, C L K _SChanges from low to high, so SW at t5 ₁Start to conduct, SW ₂On, SW ₃Open and the sensing circuit reverts to the state at time t 1.

It should be noted that the sampling phase, the holding phase, the sampling switch, the holding switch, and the like in the foregoing description are only for distinguishing different states from different switches, and they may also be referred to as phase 1, phase 2, switch 1, switch 2, and the like.

For the pixel circuit 1, the image is displayed during the period from t1 to t2 The pixel circuit 1 may output a signal voltage V _sig1The reset voltage V is output during the period t3 to t4 _rst1With the output of the pixel circuit 1 as the input of the readout circuit, the readout circuit can read out the photoelectric signal in the pixel circuit 1:

Alternatively, the pixel circuit 1 may output the reset voltage V during the period t1 to t2 _rst1Output signal voltage V during period t 3-t 4 _sig1With the output of the pixel circuit 1 as the input of the readout circuit, the readout circuit can read out the photoelectric signal in the pixel circuit 1:

Wherein (V) _sig1-V_rst1) Is the effective photo signal of the pixel circuit 1. As can be seen from equations (3) and (4), the input capacitor C is adjusted ₁And a feedback capacitor C ₂The gain of the sensing circuit can be varied.

As described above, in the period from t1 to t5, the readout circuit 100 can read out the effective photoelectric signal of the pixel circuit 1, and in the period from t5 to t6, the readout circuit 100 repeats the operation in the period from t1 to t5, and can read out the effective photoelectric signal of the pixel circuit 2. In this way, the readout circuit 100 can continuously read out the effective photoelectric signals of the pixel circuits 1 to n.

The effective photoelectric signals of the pixel circuits 1 to n read out by the readout circuit may be:

Or:

Wherein n is an integer, and n is 1, 2, 3 … … n.

However, the readout circuit 100 shown in fig. 2 can only continuously read out the effective photo-electric signals of one row (or one column) of pixels. In an image sensor, there are usually m × n pixel circuits, and the control of the pixel circuits is generally performed row by row or column by column, where m is the number of rows and n is the number of columns, and then m (or n) readout circuits are required for an image sensor. It is a huge overhead in area and power consumption for the image sensor.

In view of this, embodiments of the present application provide a readout circuit, which can reduce the area and power consumption overhead of an image sensor.

Fig. 4 shows a schematic diagram of a readout circuit 200 of an embodiment of the present application. As shown in fig. 4, the readout circuit 200 may include a plurality of capacitors 210, a switching circuit 220, and an output circuit 230. Wherein the plurality of capacitors 210 are connected to the output circuit 230 through the switch circuit 220, the plurality of capacitors 210 are used for respectively storing output signals of the plurality of pixel circuits, and the output circuit 230 is used for outputting the signals stored by the plurality of capacitors 210 one by one through the switch circuit 220.

In the embodiment of the present application, the readout circuit includes a plurality of (e.g., S) capacitors, so that output signals of S pixel circuits can be stored independently and then output one by one, so that the S pixel circuits can share one readout circuit, and thus, the number of readout circuits in the image sensor can be reduced to 1/S. Due to the small size of the capacitor in the readout circuit, the area of the readout circuit added after adding the capacitor is negligible. In addition, the power consumption in the readout circuit mainly comes from the output circuit, and the power consumption of the readout circuit is almost unchanged after the capacitor is added, so that the area and the power consumption of the image sensor can be reduced to 1/S.

It should be understood that the readout circuit of the embodiments of the present application can be applied to the field of integrated circuits. Alternatively, the readout circuit of the embodiment of the present application may be applied to an image sensor. For example, the image sensor may be an optical fingerprint sensor. The image sensor may also be referred to as an image sensor chip or other names, and the optical fingerprint sensor may also be referred to as a fingerprint sensor, an optical sensor, or a fingerprint sensor chip.

It should also be understood that the readout circuit of the embodiment of the present application has no particular requirement on the pixel circuit, and also has no particular requirement on the structure of an operational amplifier, which may be, for example, a double-ended input operational amplifier, a rail-to-rail operational amplifier, a fully differential operational amplifier, or the like. Therefore, the readout circuit of the embodiment of the application can be widely applied to the design of the existing image sensor.

In the embodiment of the present application, the plurality of pixel circuits may be pixel circuits in the same direction. Here, the pixel circuits in the same direction mentioned here may be pixel circuits in the same row, or may be pixel circuits in the same column.

Alternatively, the number of the plurality of capacitors 210 may be less than or equal to the number of the pixel circuits. For example, in an image sensor, there are m × n pixel circuits, and if the pixel circuits mentioned above are pixel circuits in the same column, the number of the capacitors 210 may be less than or equal to m; if the pixel circuits are in the same row, the number of the capacitors 210 may be less than or equal to n.

Preferably, the number of the plurality of capacitors 210 is equal to the number of pixel circuits in the same direction. At this time, the number of readout circuits required in the image sensor is minimized, and the area and power consumption of the image sensor are minimized.

Alternatively to the plurality of capacitors 210, in some embodiments, the plurality of capacitors 210 may sample and store output signals of a plurality of pixel circuits at the same time.

For example, if the image sensor has 10 × 5 pixel circuits, and the pixel circuits in the embodiment of the present application are pixel circuits in the same column, the capacitors 210 may simultaneously store the output signals of the 10 pixel circuits in the 1 st column, and then the output circuits output the output signals of the 10 pixel circuits one by one. Next, the plurality of capacitors 210 simultaneously store the output signals of the 10 pixel circuits of the 2 nd column, and then the output circuits output the output signals of the circuits of the 10 pixels of the 2 nd column one by one. By analogy, the plurality of capacitors 210 can simultaneously store the output signals of the 10 pixel circuits of the 5 th column, and thereafter, the output circuits output the output signals of the 10 pixel circuits of the 5 th column one by one.

When the plurality of capacitors 210 simultaneously sample output signals of a plurality of pixel circuits, all switches in the switch circuit 220 in the embodiment of the present application are turned on.

In this implementation, the number of readout circuits can be reduced without changing the control manner of the pixel circuit, thereby reducing the area and power consumption overhead of the image sensor.

Alternatively, in other embodiments, the plurality of capacitors 210 may not sample and store the output signals of the plurality of pixel circuits at the same time. For example, the plurality of capacitors 210 sequentially sample and store output signals of the plurality of pixel circuits; alternatively, the plurality of capacitors 210 may be divided into a plurality of groups, the capacitors in each group sampling and storing the output signal of the pixel circuit at the same time, and the capacitors of different groups sampling and storing the output signal of the pixel circuit at different timings.

Alternatively, in some embodiments, the output circuit 230 may be configured to amplify the signals stored in the plurality of capacitors 210 and output the amplified signals, and provide driving capability for the output signals. The embodiment of the present application does not limit the amplification factor of the signal amplified by the output circuit 230, and for example, the amplification factor may be less than 1, equal to 1, or greater than 1.

In the embodiment of the present application, the output circuit 230 includes: the circuit comprises an operational amplifier, a feedback capacitor, a first switch, a second switch and a third switch. The two ends of the first switch may be connected to the input end and the output end of the operational amplifier, the left plate of the feedback capacitor may be connected to the input end of the operational amplifier, the right plate of the feedback capacitor may be connected to the output end of the operational amplifier through the third switch, and the two ends of the second switch may be connected to the right plate of the feedback capacitor and the voltage source, respectively.

The first switch may also be referred to as a sampling switch, and the second switch and the third switch may also be referred to as a holding switch, respectively. In an exemplary manner, the first and second electrodes are, The operational amplifier, the feedback capacitor, the first switch, the second switch, and the third switch may correspond to OPA, C in fig. 2, respectively ₂、SW₁、SW₂And SW ₃。

It should be understood that, in the embodiments of the present application, the terms "first", "second" and "third" are only used for distinguishing different objects, and do not limit the scope of the embodiments of the present application.

Alternatively to the switching circuit 220, in some embodiments, the switching circuit 220 may include only one switch, which may have multiple contacts. Wherein the number of switch contacts may be the same as the number of pixel circuits.

In this embodiment, when the output circuit 230 outputs the signal stored by the ith capacitor of the plurality of capacitors 210, the switch in the switch circuit 220 may be switched to be connected to the ith capacitor to output the signal stored by the ith capacitor.

Alternatively, in other embodiments, the switching circuit 220 may include a plurality of switches in one-to-one correspondence with the plurality of capacitors 210. At this time, the output circuit 230 may be used to output the signals stored by the plurality of capacitors 210 one by one through the turn-on of the plurality of switches one by one.

In this embodiment, when the output circuit 230 outputs the signal stored in the ith capacitor of the plurality of capacitors 210, the switch corresponding to the ith capacitor is turned on, and the remaining switches, i.e., the switches other than the switch corresponding to the ith capacitor of the switch circuit 220, are turned off.

At this time, the switching circuit 220 and the plurality of capacitors 210 may be integrally formed into an input capacitance array. In this embodiment, a schematic diagram of a possible readout circuit 2100 for the readout circuit 200 can be shown in fig. 5. It can be seen that the readout circuit 2100 can be primarily composed of:

(a) An array of input capacitors. Wherein the input capacitance array may comprise a capacitance group 11 to a capacitance group 1S, the capacitance group 11 comprising an input capacitor C ₁And a switch SW ₁The capacitor bank 12 comprises an input capacitor C ₂And a switch SW ₂… … capacitor bank 1S includes Input capacitor C _SAnd a switch SW _S. Input capacitor C ₁An input capacitor C ₂… … input capacitor C _SRespectively has a capacitance of C ₁、C₂……C_S. Capacitor bank switch SW ₁the control signal of (C) L K _P1Capacitor bank switch SW ₂the control signal of (C) L K _P2… … capacitor bank switch SW _Sthe control signal of (C) L K _PS。

(b) And an output circuit. Wherein the output circuit can be composed of a feedback capacitor C _FOperational amplifier, first switch SW _S+1A second switch SW _S+2And a third switch SW _S+3And (4) forming. Feedback capacitor C _FHas a capacitance of C _F. The gain of the operational amplifier is-A, ideally A ∞ and the input voltage of the operational amplifier is V _IOutput voltage of V _OUT. First switch SW _S+1the control signal of (C) L K _SA second switch SW _S+2the control signal of (C) L K _H1A third switch SW _S+3the control signal of (C) L K _H2。

Fig. 6 is a schematic diagram of one possible application of the readout circuit 2100. As shown in fig. 6, the image sensor includes S × n pixel circuits, and the number of the plurality of capacitors 210 is the same as that of the pixel circuits in the same column, so that only 1 readout circuit may be required for one image sensor.

Fig. 7 is a timing chart of a control method corresponding to the readout circuit 2100 shown in fig. 5 and 6. The operation of the readout circuit 2100 is described below in conjunction with fig. 6. For ease of description, all of the foregoing switches are defined as: the control signal is conducted when the level is high.

first, at time t1, C L K _Schange from low to high, C L K _H1is high level, C L K _H2at a low level, C L K _P1to C L K _PSAre all high. At this time, SW _S+1Start to conduct, SW _S+2On, SW _S+3Is turned off, SW ₁To SW _SAre on and all switch states remain unchanged during the period t1 to t2, the readout circuit 2100 operates in the sampling phase. The feedback may be such that Input voltage V of operational amplifier under ideal condition _IIs maintained at a common mode voltage.

Let the common-mode voltage of the operational amplifier be V _CMLet the input voltages of the readout circuit 2100 in the time period t 1-t 2 be V _IN11To V _INS1Then input into a capacitor C ₁To C _SThe stored charges respectively satisfy: (V) _IN11-V_CM)*C₁To (V) _INS1-V_CM)*C_SFeedback capacitor C _FThe charge stored on the memory cell satisfies: (V) _REF-V_CM)*C_F. Wherein, V _REFIs the voltage of the voltage source.

then, in the period from t2 to t3, C L K _P1to C L K _PSwhile changing from high to low, C.L.K _Sfrom high to low, C L K _H1from high to low, C L K _H2change from low to high, C L K _P1From low to high. Therefore, SW at time t3 _S+1Is turned off, SW _S+2Is turned off, SW _S+3Start to conduct, SW ₁Starting to conduct, the remaining switches are turned off, and all switch states remain unchanged during the period t3 to t4, the circuit operates in the holding phase 1.

The feedback can make the input voltage V of the operational amplifier under ideal conditions _IMaintained at a common mode voltage V _CMLet t 3-t 4 be the period C ₁The input signal of the left polar plate is V _IN12Then input into a capacitor C ₁The charge stored on the memory cell satisfies: (V) _IN12-V_CM)*C₁Feedback capacitor C _FThe charge stored on the memory cell satisfies: (V) _OUT-V_CM)*C_F。

During the switching from the sampling phase to the holding phase 1, the capacitor C is input ₁Right plate and feedback capacitor C _FThe left plate of (2) has no charge path, so according to the charge conservation principle, the following are provided:

(V_IN12-V_CM)*C₁+(V_OUT-V_CM)*C_F＝(V_IN11-V_CM)*C₁+(V_REF-V_CM)*C_F(7)

From equation (7), we can obtain:

Next, in the period of t4 to t5, C L K _Schange from low to high, C L K _H2from high to low, C L K _H1change from low to high, C L K _P1Changes from high to low, so at time t5, SW _S+1On, SW _S+2On, SW _S+3Is turned off, SW ₁The turn-off is started, and the readout circuit 2100 returns to the state at time t2, and the feedback capacitor C _FThe charge on the capacitor is changed into (V) again _REF-V_CM)*C_F。

then, in the period from t5 to t6, C L K _P1from high to low, C L K _Sfrom high to low, C L K _H1from high to low, C L K _H2change from low to high, C L K _P2From low to high. Therefore, SW at time t6 _S+1Is turned off, SW _S+2Is turned off, SW _S+3Start to conduct, SW ₂Starting to conduct, the remaining switches are opened, and the switch states remain unchanged during the period t6 to t7, the circuit operates in holding phase 2. The feedback can make the input voltage V of the operational amplifier under ideal conditions _IMaintained at a common mode voltage V _CM. Let the time period t 6-t 7 input the capacitor C ₂The input signal of the left polar plate is V _IN22Then input into a capacitor C ₂On stored charge satisfies (V) _IN22-V_CM)*C₂Feedback capacitor C _FThe charge stored on the memory cell satisfies: (V) _OUT-V_CM)*C_F。

During the switching from the sampling phase to the holding phase 2, the capacitor C is input ₂Has no charge path, and during the switching from time t5 to holding phase 2, feedback capacitor C _FThe left plate of (2) has no charge path, so according to the principle of charge conservation:

(V_IN22-V_CM)*C₂+(V_OUT-V_CM)*C_F＝(V_IN21-V_CM)*C₂+(V_REF-V_CM)*C_F(9)

Can be solved to obtain:

Then, in the period t7 to t9, the readout circuit may continuously perform S-2 times of operations like the period t4 to t7, and may obtain:

finally, in the period t 9-t 10, C L K _H1change from low to high, C L K _H2from high to low, C L K _P1to C L K _P(S-1)all change from low level to high level, C L K _SChanges from low to high, so SW at t10 _S+1Start to conduct, SW _S+2On, SW _S+3Is turned off, SW ₁To SW _SAre both on and the sensing circuit reverts to the state at time t 1.

For the pixel circuits 11 to S1, in the period t1 to t2, the pixel circuits 11 to S1 may output the signal voltage V, respectively _sig11The pixel circuit 11 outputs the reset voltage V during the period t3 to t4 _rst11With the output of the pixel circuit 11 as the input of the readout circuit 2100, the readout circuit 2100 can read out the photoelectric signal of the pixel circuit 11:

Alternatively, in the period from t1 to t2, the pixel circuits 11 to S1 may output the signal voltage V, respectively _rst11The pixel circuit 11 outputs the reset voltage V during the period t3 to t4 _sig11By using the output of the pixel circuit 11 as the input of the readout circuit 2100, the readout circuit 2100 can read out the photoelectric signal of the pixel circuit 11 ：

Wherein (V) _sig11-V_rst11) Is the effective photo signal of the pixel circuit 11. As can be seen from equations (12) and (13), the input capacitor C is adjusted ₁And a feedback capacitor C _FThe ratio of (d) may change the gain of the readout circuit 2100.

Similarly to the pixel circuit 11, in the period from t6 to t7, if the pixel circuit 21 outputs the reset voltage V _rst21(or signal voltage V _sig21) The readout circuit 2100 can read out the photoelectric signal of the pixel circuit 21 by using the output of the pixel circuit 21 as the input of the readout circuit 2100, and there are:

Or:

Likewise, in the period from t8 to t9, the readout circuit 2100 can read out the photoelectric signal of S1 in the pixel circuit by:

Or:

As described above, in the period from t1 to t10, the readout circuit 2100 successively reads out the effective photoelectric signals of the pixel circuits 11 to S1 (i.e., the pixel circuits of the first column of the image sensor), and in the period from t10 to t11, the readout circuit 2100 repeats the operations in the period from t1 to t10, and can successively read out the effective photoelectric signals of the pixel circuits of the second column of the image sensor, i.e., the pixel circuits 12 to S2. In this manner, the readout circuit 2100 can successively read out the effective photoelectric signals of the pixel circuits 11 to Sn successively. It is possible to obtain:

Or:

Wherein n is an integer, and n is more than or equal to 1 and less than or equal to S.

It should be noted that the sampling phase, the holding phase 1, and the holding phase 2 in the description of the readout circuit 2100 are only for distinguishing different phase states, and do not limit the scope of the embodiments of the present application in any way, and they may also be referred to as phase 1, phase 2, phase 3, and so on.

The readout circuit of the embodiment of the present application can be applied simultaneously with the existing image sensor technology, and there is no limitation on the image sensor technology, for example, the image sensor technology may be a multi-pixel averaging technology.

Fig. 8 is a schematic structural diagram of a possible readout circuit 2200 according to an embodiment of the present disclosure. The readout circuit 2200 incorporates pixel averaging techniques and the operational amplifier in the output circuit is a two-terminal input operational amplifier.

Fig. 9 is a schematic diagram of a possible application of the readout circuit 2200. The pixel circuit in fig. 9 is a super pixel circuit, and the structural schematic diagram of the super pixel circuit can refer to fig. 10. As can be seen from FIG. 10, a super-pixel circuit may include a plurality of sub-pixel circuits, and a super-pixel circuit may have X output signals V _PO1To V _POXIn which V is _PO1Is the output signal of the sub-pixel circuit 1, V _POXIs the output signal of the sub-pixel X.

As can be seen from fig. 8, the readout circuit 2200 may be mainly composed of:

(a) An array of input capacitors. Wherein the input capacitor array may comprise a capacitor bank 11 to Capacitor bank 1S, capacitor bank 11 includes input capacitor C ₁₁To C _X1And a switch SW ₁₁To SW _X1An input capacitor C ₁₁To C _X1Respectively has a capacitance of C ₁₁To C _X1(ii) a The capacitor bank 12 comprises an input capacitor C ₁₂To C _X2And a switch SW ₁₂To SW _X2An input capacitor C ₁₂To C _X2Respectively has a capacitance of C ₁₂To C _X2… … capacitance bank 1S includes an input capacitor C _1STo C _XSAnd a switch SW _1STo SW _XSAn input capacitor C _1STo C _XSRespectively has a capacitance of C _1STo C _XS. Capacitor bank 11 switch SW ₁₁To SW _X1the control signal of (C) L K _P1Capacitor bank 12 switch SW ₁₂To SW _X2the control signal of (C) L K _P2… … capacitor bank 1S switch SW _1STo SW _XSthe control signal of (C) L K _PS。

Alternatively, the number of capacitors included in each capacitance group may be the same as the number of sub-pixel circuits in each super-pixel circuit. For example, each super pixel circuit includes X sub-pixel circuits, and each capacitor group includes X capacitors and switches corresponding to the X capacitors.

It can be seen that in fig. 8, a plurality of capacitors 210 and a switching circuit 220 integrally form an input capacitance array.

(b) And an output circuit. Wherein the output circuit can be composed of a feedback capacitor C _FOperational amplifier, first switch SW _S+1A second switch SW _S+2And a third switch SW _S+3And (4) forming. Feedback capacitor C _FHas a capacitance of C _F. The gain of the operational amplifier is A, ideally A is ∞, and the negative input voltage of the operational amplifier is V _IOutput voltage of V _OUTPositive phase input voltage of V _CM. First switch SW _S+1the control signal of (C) L K _SA second switch SW _S+2the control signal of (C) L K _H1A third switch SW _S+3the control signal of (C) L K _H2。

The operation of the readout circuit 2200 is described below in conjunction with fig. 7. For convenience of description, all switches in fig. 8 are defined as: the control signal is conducted when the level is high.

first, at time t1, C L K _Schange from low to high, C L K _H1is high level, C L K _H2at a low level, C L K _P1to C L K _PSAre all high. Therefore SW _S+1Start to conduct, SW _S+2On, SW _S+3Is turned off, SW ₁₁To SW _XSAre on and all switch states remain unchanged during the period t1 to t2, the circuit operates in the sampling phase.

The feedback can be such that the negative phase input voltage V of the operational amplifier in the ideal case is _IAnd a positive phase input voltage V _CMAre equal. Let the input voltage of the sensing circuit 2200 in the period t 1-t 2 be V _IN111To V _INXS1Then input into a capacitor C ₁₁To C _XSRespectively, the charges stored thereon are (V) _IN111-V_CM)*C₁₁To (V) _INXS1-V_CM)*C_XSFeedback capacitor C _FThe charge stored on the memory cell satisfies: (V) _REF-V_CM)*C_F。

then, in the period from t2 to t3, C L K _P1to C L K _PSwhile changing from high to low, C.L.K _Sfrom high to low, C L K _H1from high to low, C L K _H2change from low to high, C L K _P1From low to high. Therefore SW at time t3 _S+1Is turned off, SW _S+2Is turned off, SW _S+3Start to conduct, SW ₁₁To SW _X1Starting to conduct, the remaining switches are turned off, and all switch states remain unchanged during the period t3 to t4, the circuit operates in the holding phase 1.

The feedback can be such that the negative phase input voltage V of the operational amplifier in the ideal case is _IAnd a positive phase input voltage V _CMAre equal. Let the time period t 3-t 4 input the capacitor C ₁₁To C _X1The input signal of the left polar plate is V _IN112To V _INX12Then input into a capacitor C ₁₁To C _X1On stored electricity Each of the two lotus roots is (V) _IN112-V_CM)*C₁₁To (V) _INX12-V_CM)*C_X1Feedback capacitor C _FHas a stored charge of (V) _OUT-V_CM)*C_F。

During the switching from the sampling phase to the holding phase 1, the capacitor C is input ₁₁To C _X1Right plate and feedback capacitor C _FThe left plate of (2) has no charge path, so according to the charge conservation principle, the following are provided:

Can be solved to obtain:

Next, in the period of t4 to t5, C L K _Schange from low to high, C L K _H2from high to low, C L K _H1change from low to high, C L K _P1Changes from high to low, so at time t5, SW _S+1On, SW _S+2On, SW _S+3Is turned off, SW ₁₁To SW _X1Starts to open, and the sensing circuit returns to the state at time t2, feeding back capacitor C _FThe charge on the capacitor is changed into (V) again _REF-V_CM)*C_F。

then, in the period from t5 to t6, C L K _P1from high to low, C L K _Sfrom high to low, C L K _H1from high to low, C L K _H2change from low to high, C L K _P2From low to high. Therefore, SW at time t6 _S+1Is turned off, SW _S+2Is turned off, SW _S+3Start to conduct, SW ₁₂To SW _X2Starting to conduct, the remaining switches are opened, and the switch states remain unchanged during the period t6 to t7, the circuit operates in holding phase 2.

The feedback may be such that the OPA negative phase input voltage V in the ideal case _IAnd the positive phase Input voltage V _CMAre equal. Let the time period t 6-t 7 input the capacitor C ₁₂To C _X2The input signal of the left polar plate is V _IN122To V _INX22Then input into a capacitor C ₁₂To C _X2Respectively, the charges stored thereon are (V) _IN122-V_CM)*C₁₂To (V) _INX22-V_CM)*C_X2Feedback capacitor C _FHas a stored charge of (V) _OUT-V_CM)*C_F。

During the switching from the sampling phase to the holding phase 2, the capacitor C is input ₁₂To C _X2The right plate has no charge path, and the feedback capacitor C is switched to hold phase 2 from time t5 _FThe left plate of (2) has no charge path, so according to the principle of charge conservation:

Can be solved to obtain:

finally, in the period t 9-t 10, C L K _H1change from low to high, C L K _H2from high to low, C L K _P1to C L K _P(S-1)all change from low level to high level, C L K _SFrom low to high. Therefore SW at time t10 _S+1Start to conduct, SW _S+2On, SW _S+3Is turned off, SW ₁₁To SW _XSAre both on and the sensing circuit reverts to the state at time t 1.

For the super pixel circuit 11 to the super pixel circuit S1, in the period of t1 to t2, the super pixel circuit 11 to the super pixel circuit S1 may output signal voltages respectively <V_sig111:V_sigX11>To <V_sig1S1:V_sigXS1>The super pixel circuit 11 may output the reset voltage in the period of t3 to t4 <V_rst111:V_rstX11>The readout circuit 2200 can read out the photoelectric signal of the super pixel circuit 11 by using the output of the super pixel circuit 11 as the input of the readout circuit 2200:

Alternatively, in the period from t1 to t2, the super pixel circuit 11 to the super pixel circuit S1 may output the reset voltage respectively <V_rst111:V_rstX11>To <V_rst1S1:V_rstXS1>The period t3 to t4 the pixel circuit 11 outputs a signal voltage <V_sig111:V_sigX11>The readout circuit 2200 can read out the photoelectric signal of the pixel circuit 11 by using the output of the pixel circuit 11 as the input of the readout circuit 2200:

Wherein (V) _sigm11-V_rstm11) Is the effective photo signal of the mth sub-pixel circuit in the super-pixel circuit 11. As can be seen from equations (25) and (26), the input capacitor C is adjusted _m1And a feedback capacitor C _FCan change the gain of the sensing circuit 2200.

Similar to the pixel circuit 11, the super pixel circuit 21 may output the reset voltage during the period t6 to t7 <V_rst121:V_rstX21>(or signal voltage) <V_sig121:V_sigX21>) The readout circuit 2200 can read out the photoelectric signal of the super pixel circuit 21 by using the output of the super pixel circuit 21 as the input of the readout circuit 2200, and includes:

Or:

Likewise, in the period from t8 to t9, the readout circuit 2200 may read out the photoelectric signal of S1 in the super pixel circuit, with:

Or:

As described above, the readout circuit 2200 continuously reads out the effective photoelectric signals of the super-pixel circuits 11 to S1 (i.e., the super-pixel circuits of the first column of the image sensor) during the period t1 to t10, and the readout circuit 2200 repeats the operations during the periods t1 to t10 during the period t10 to t11, so that the effective photoelectric signals of the super-pixel circuits of the second column of the image sensor, i.e., the super-pixel circuits 12 to S2, can be continuously read out. In this manner, the readout circuit 2200 can successively read out the effective photoelectric signals of the super pixel circuits 11 to Sn. It is possible to obtain:

Or:

It should be noted that the sampling phase, the holding phase 1, and the holding phase 2 in the description of the readout circuit 2200 are only for distinguishing different phase states, and do not limit the scope of the embodiments of the present application in any way, and they may also be referred to as phase 1, phase 2, phase 3, and so on.

In the embodiment of the application, the readout circuit includes a plurality of (e.g., S) capacitors, so that output signals of S pixel circuits can be stored independently and then output one by one, so that the S pixel circuits can share one readout circuit, and thus, the number of readout circuits in the image sensor can be reduced to 1/S. Due to the small size of the capacitor in the readout circuit, the area of the readout circuit added after adding the capacitor is negligible. In addition, the power consumption in the readout circuit mainly comes from the output circuit, and the power consumption of the readout circuit is almost unchanged after the capacitor is added, so that the area and the power consumption of the image sensor can be reduced to 1/S.

The embodiment of the application also provides an image sensor which is used for converting optical signals into electric signals.

Optionally, the image sensor may include a readout circuit. The readout circuit may be the readout circuit 200 in the foregoing embodiment, and corresponding operations of the readout circuit 200 may be implemented, which is not described herein again for brevity.

It should be understood that the readout circuit of the embodiments of the present application may be applied to various electronic devices, such as portable or mobile computing devices, such as smart phones, notebook computers, tablet computers, and game devices, and other electronic devices, such as electronic databases, automobiles, and Automated Teller Machines (ATMs), and the embodiments of the present application are not limited thereto.

The embodiment of the present application further provides an electronic device 300, as shown in fig. 11, the electronic device 300 may include a readout circuit 310. The readout circuit 310 may be the readout circuit 200 in the foregoing embodiment, and corresponding operations of the readout circuit 200 may be implemented, which are not described herein for brevity.

the display screen 320 may be a display screen having a self-luminous display unit, such as an Organic light-Emitting Diode (O L ED) display screen or a Micro light-Emitting Diode (Micro-L ED) display screen.

It should be understood that the specific examples in the embodiments of the present application are for the purpose of promoting a better understanding of the embodiments of the present application and are not intended to limit the scope of the embodiments of the present application.

It is to be understood that the terminology used in the embodiments of the present application and the appended claims is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. For example, as used in the examples of this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A sensing circuit, comprising:

An input capacitance array including a plurality of capacitance groups for storing output signals of the plurality of pixel circuits, respectively;

And the output circuit is used for outputting the output signals stored by the plurality of capacitor groups one by one.

2. A readout circuit according to claim 1, wherein the plurality of pixel circuits are pixel circuits in a same direction, the same direction is a same row or a same column, and the number of the plurality of capacitance groups is equal to the number of the plurality of pixel circuits.

3. The sensing circuit of claim 2, wherein each of the plurality of capacitance groups comprises a capacitor and a switch, the capacitors of the plurality of capacitance groups being configured to store the output signal respectively.

4. The sensing circuit of claim 2, wherein each of the capacitance groups comprises X capacitors and X switches, and wherein the capacitors of the plurality of capacitance groups are configured to store the output signals, respectively.

5. A readout circuit according to claim 4, wherein the pixel circuit is a super pixel circuit comprising X sub-pixel circuits.

6. A readout circuit according to any of claims 3 to 5, wherein the capacitors of the plurality of capacitance groups are used to sample and store the output signals of the plurality of pixel circuits simultaneously.

7. A readout circuit according to claim 6, wherein all switches in the plurality of capacitance groups are turned on when the capacitors in the plurality of capacitance groups simultaneously sample the output signals of the plurality of pixel circuits.

8. A readout circuit according to any one of claims 3 to 5, wherein the output circuit is configured to output the output signals stored in the plurality of capacitance groups one by sequentially turning on the switches in the plurality of capacitance groups.

9. A sensing circuit according to any one of claims 3 to 5, wherein when the output circuit is configured to output the output signal stored by an ith capacitor bank of the plurality of capacitor banks, the switch in the ith capacitor bank is turned on and the switches in the plurality of capacitor banks other than the switch in the ith capacitor bank are turned off.

10. A sensing circuit of claim 3, wherein the output circuit comprises:

An operational amplifier, a feedback capacitor, a first switch, a second switch, and a third switch;

Wherein the operational amplifier is used for amplifying and outputting the output signals stored by the plurality of capacitor banks;

The two ends of the first switch are respectively connected to the input end of the operational amplifier and the output end of the operational amplifier, the left pole plate of the feedback capacitor is connected to the input end of the operational amplifier, the right pole plate of the feedback capacitor is connected to the output end of the operational amplifier through the third switch, and the two ends of the second switch are respectively connected to the right pole plate of the feedback capacitor and the voltage source.

11. A sensing circuit according to claim 4 or 5, wherein the output circuit comprises:

The two ends of the first switch are respectively connected to the negative phase input end of the operational amplifier and the output end of the operational amplifier, the left pole plate of the feedback capacitor is connected to the negative phase input end of the operational amplifier, the right pole plate of the feedback capacitor is connected to the output end of the operational amplifier through the third switch, the two ends of the second switch are respectively connected to the right pole plate of the feedback capacitor and the voltage source, and the positive phase input end of the operational amplifier is connected to the positive phase input voltage.

12. An image sensor, comprising: the readout circuit of any of claims 1-11.

13. An electronic device, comprising: the readout circuit of any of claims 1-11.