CN211127195U

CN211127195U - Novel B2MS storage battery equalization management system

Info

Publication number: CN211127195U
Application number: CN201922115986.8U
Authority: CN
Inventors: 康琳祥
Original assignee: Chongqing Rongkai Chuanyi Meter Co ltd
Current assignee: Chongqing Rongkai Chuanyi Meter Co ltd
Priority date: 2019-12-02
Filing date: 2019-12-02
Publication date: 2020-07-28
Anticipated expiration: 2029-12-02

Abstract

The utility model relates to the technical field of batteries, a novel B is disclosed²MS battery equalization management system, its characterized in that, including the group battery GB that N single cell establish ties into, group battery GB connects on the major loop, still includes CPU monitoring unit, control interface unit, balanced control circuit, N battery data acquisition unit and N bypass unit, battery data acquisition unit with the single cell is parallelly connected for gather each single cell's data, the bypass unit with the single cell is parallelly connected, just battery data acquisition unit, bypass unit all with control interface unit electricity is connected, control interface unit with CPU monitoring unit electricity is connected, CPU monitoring unit with the group battery GB that N single cell establish ties into, the group battery GB connects on the major loop for gather each single cell's data, the bypass unit with the single cellAnd the balance control circuit is electrically connected with the N bypass power supplies. According to the difference of the single batteries, the inconsistency among the storage battery packs GB is shortened, the overall balance performance of the storage battery packs GB is improved, and the service life is prolonged.

Description

Novel B2MS storage battery equalization management system

Technical Field

The utility model relates to a battery technology field especially relates to a novel B²MS battery balance management system.

Background

The principle of the existing battery equalizing charge is that the capacity and the running state parameters of a single battery are rapidly and accurately measured and analyzed by monitoring the voltage, the internal resistance and the surface temperature of the single battery on line, and when the single battery is found to be abnormal (the internal resistance is increased and the charging and discharging performance is deteriorated), the system can adjust the dynamic switching of the equalizing, floating charge and battery discharge modes of the whole storage battery in real time, so that the problem battery is activated to the maximum extent, and the equalizing management among batteries is realized. However, since the whole group of storage batteries connected in series is charged in whole group, the discharge is carried out together in whole group, and the charge and discharge of each single battery is not controlled independently, so that in the floating state, even if the floating charge voltage of the battery pack is set strictly according to the required voltage and is compensated according to the temperature, the actual bearing voltage of each single storage battery deviates from the required floating charge voltage due to the inconsistency of the internal resistance capacity and other performances of the single storage batteries, the charging voltage of part of the batteries is over-high and is in an over-charge state, and the charging voltage of part of the batteries is under-low and is in an under-charge state. After multiple charging and discharging, the difference of the single batteries is further amplified, and the difference of the single batteries causes that any battery in the battery pack is not overcharged or undercharged, so that the performance of the single batteries is further deteriorated, a vicious circle is formed, and the service life of the battery pack is shortened.

SUMMERY OF THE UTILITY MODEL

To the deficiency of the prior art, the utility model provides a novel B²After the balance management system is started, the overcharged battery can transfer redundant electric quantity to the battery which is not fully charged, and dynamic balance is realized. The efficiency is high, the loss is less, and all the battery voltages are monitored by the balance management system in the whole process.

In order to solve the technical problem, the utility model discloses a following technical scheme:

novel B²MS battery equalization management system, its characterized in that, including the group battery GB that N single cell establish ties into, group battery GB connects on the major loop, still includes CPU monitoring unit, control interface unit, balanced control circuit, N battery data acquisition unit and N bypass unit, battery data acquisition unit with the single cell is parallelly connected for gather each single cell's data, the bypass unit with the single cell is parallelly connected, just battery data acquisition unit, bypass unit all with instituteThe monitoring interface unit is electrically connected with the CPU monitoring unit, the CPU monitoring unit is electrically connected with the balance control circuit, the balance control circuit is electrically connected with the N bypass units, and N is a positive integer between 1 and 128.

In the technical scheme, data (voltage, internal resistance, current and temperature parameters) collected by each single battery is uploaded to a CPU monitoring unit through a monitoring interface unit, and the CPU sends an instruction to an equalization control circuit to adjust the on-off of each bypass unit power tube after operation processing so as to realize the function of equalizing charging.

Preferably, the bypass unit is an equalizing bypass P connected in parallel to the unit cells, the N equalizing bypasses P correspond to the N unit cells GBn one to one, wherein an input end of a first equalizing bypass P1 is electrically connected with a positive electrode of a first unit cell GB1, and an output end of the first equalizing bypass P1 is electrically connected with a negative electrode of the first unit cell GB 1; the input end of the Mth equalizing bypass Pm is electrically connected with the positive electrode of the Mth single battery GBm, the output end of the Mth equalizing bypass Pm is electrically connected with the positive electrode of the first single battery GB1, the control end of the equalizing bypass is electrically connected with the equalizing control circuit, wherein M is a positive integer of 2-128.

Thus, the main loop charges the battery group GB, and the equalization bypass does not work; when the voltage of the single battery of the battery pack GB is overcharged, the equalization control circuit triggers the equalization bypass to perform equalization charging processing on the corresponding battery.

Preferably, the first equalizing bypass P1 includes a first diode VD1, a first inductor L1 and a first mos tube S1, the anode of the first diode VD1 is connected to the cathode of the M-th cell GBm, the cathode of the first diode VD1 is electrically connected to the source of the first mos tube S1, the drain of the first mos tube S1 is electrically connected to the anode of the first cell GB1, the gate of the first mos tube S1 is electrically connected to the equalization control circuit, the first inductor L1 is electrically connected to the source of the first mos tube S1 and the cathode of the first cell GB1, respectively, and the first mos tube S1 is an Nmos tube.

Thus, the cathode of the first diode VD1 is electrically connected with the source of the first mos tube S1, current can be prevented from flowing through the first diode VD1, when the main loop charges the battery pack GB, the equalization control circuit does not supply grid current to the first mos tube, the first mos tube S1 is not conducted, when the first single battery is in an undercharge state, the downstream equalization bypass charges the first single battery, when the first single battery GB1 is in an overcharging state, the equalization control circuit supplies the grid current to the first mos tube, the first mos tube S1 is conducted, and the current flows through the first inductor L1 and flows to the downstream single battery.

Preferably, the mth equalizing bypass Pm includes an mth diode VDm, an mth inductor L M, and an mth mos tube Sm, a cathode of the mth diode VDm is connected to an anode of the first cell GB1, an anode of the mth diode VDm is electrically connected to a drain of the mth mos tube Sm, a source of the mth mos tube Sm is electrically connected to a cathode of the mth cell GBm, a gate of the mth mos tube Sm is electrically connected to the equalizing control circuit, the mth inductor L M is electrically connected to a drain of the mth mos tube Sm and an anode of the mth cell GBm, respectively, and the mth diode Sm is an Nmos tube.

Thus, when the battery pack GB is charged, the equalization control circuit does not give grid current to the Mmos tube, the Mmos tube Sm is not conducted, part of current of the main loop passes through the Mth single battery GBm, part of current flows to the first single battery GB1 from the Mth inductor and the Mth diode, the Mth inductor stores energy, when the Mth single battery GBm overshoots, redundant electric quantity flows to the first single battery GB1 through the Mth inductor and the Mth diode in the equalization charging stage, the redundant electric quantity is transmitted to the single battery which is undercharged at the upstream through the main loop, when the Mth single battery GBm undershoots, the equalization control circuit gives grid current to the Mth single battery GBm, the Mmos tube Sm is conducted, and the electric quantity stored by the Mth inductor L M flows to the source electrode from the drain electrode of the Mth single battery GBm to charge the ground.

Preferably, the equalization control circuit is an 89C51 chip.

The utility model has the advantages that:

1. the utility model discloses according to battery cell's difference, shorten the nonconformity between the storage battery GB, make storage battery GB's whole equilibrium performance obtain improving, the life-span extension.

Drawings

Figure 1 is the utility model²The structure schematic diagram of the MS storage battery balance management system;

FIG. 2 is a circuit diagram of the monitor interface unit of FIG. 1;

FIG. 3 is a circuit diagram of the bypass power supply of FIG. 1;

FIG. 4 is a control flow diagram of the present system;

FIG. 5 is a test circuit diagram of the system under test;

fig. 6 is a graph of battery terminal voltage during charging for the system tests.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings. In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the orientation words such as "upper, lower, front, rear, left, right" and "top, bottom" etc. are usually based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of description, and in the case of not making a contrary explanation, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be interpreted as limiting the scope of the present invention; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

As shown in fig. 1, a new type B²MS battery equalization management system, including group battery GB that N monomer batteries establish ties and form, group battery GB connects on the major loop, still include CPU monitor cell 5, control interface unit 4, equalization control circuit 3, N battery data acquisition unit 1 and N bypass unit 2, battery data acquisition unit 1 connects in parallel with the monomer battery, be used for gathering the data of each monomer battery, bypass unit 2 connects in parallel with the monomer battery, and battery data acquisition unit 1, bypass unit 2 all are connected with control interface unit 4 electricity, control interface unit 4 is connected with CPU monitor cell 5 electricity, CPU monitor cell 5 is connected with equalization control circuit 3 electricity, equalization control circuit 3 is connected with N bypass unit 2 electricity, wherein, N is 1-128 between-interval group battery GB, group battery GB connects in parallel, be used for gathering the data of each monomer battery, bypass unit 2 is connected with the monomer battery electricityIs a positive integer of (1).

As shown in fig. 2, the monitoring interface unit is also an interface circuit of the measurement and control bus. The P3 port of the singlechip 87C196KB is expanded into a measurement and control bus driving circuit by a latch 74HC574, and after the conversion of the 8-path level converter, the data of the P3 port is used as function expansion control signals (DC 0-DC 7) of the measurement and control bus interface X1, namely common control signals of all function expansion boards. Analog quantity (Analog) and Digital quantity (Digital) sampled by each function expansion board are respectively connected to pins 8# and 7# of X1 (as a common data input channel), the Analog quantity is processed by a 12-bit high-speed A/D converter MAX120 and then input to ports P0 and P2 of 87C196KB, and the Digital quantity is input to pin P2.3 of 87C196 KB. The function expansion boards are electrically connected with the battery data acquisition unit and the bypass unit, and are connected from +5V in fig. 2, and input and output pins (not shown in the figure) of 87C196KB are connected with the CPU monitoring unit, which is common knowledge in the art and will not be described again here. The battery data acquisition unit can refer to patent documents with patent number "201821575598.7" and patent name "a battery pack GB each single battery data acquisition circuit", and the CPU monitoring unit can refer to the CPU in patent documents with patent number "201180049787.5" and patent name "voltage monitoring device for battery pack".

In a charging cycle, the circuit working process is divided into two phases: a voltage detection phase (time is Tv) and a charge equalization phase (time is Tc). In the voltage detection stage, the bypass unit does not work, the main power supply charges the battery pack GB, the voltage of the single battery in the battery pack GB is detected, and the duty ratio of the MOSFET is calculated according to a control algorithm. And in the equalizing charge stage, the MOSFET triggered in the bypass controls the switch state according to the calculated duty ratio, and the equalizing charge treatment is carried out on the corresponding battery. In this phase, the main loop current is INPUT, which flows through the battery GB formed by the series connection of the individual cells.

As shown in fig. 3, in the present embodiment, the bypass unit is an equalizing bypass P connected in parallel to the unit cells, and N equalizing bypasses P correspond to N unit cells one to one, where an input end of the first equalizing bypass P1 is electrically connected to a positive electrode of the first unit cell GB1, and an output end of the first equalizing bypass P1 is electrically connected to a negative electrode of the first unit cell GB 1; the input end of the Mth equalizing bypass Pm is electrically connected with the positive electrode of the Mth single battery GBm, the output end of the Mth equalizing bypass Pm is electrically connected with the positive electrode of the first single battery GB1, and the control end of the equalizing bypass is electrically connected with the equalizing control circuit, wherein N is a positive integer between 1 and 128, and M is a positive integer between 2 and 128.

In this embodiment, the first equalizing bypass P1 includes a first diode VD1, a first inductor L1, and a first mos tube S1, an anode of the first diode VD1 is connected to a cathode of the M-th cell GBm, a cathode of the first diode VD1 is electrically connected to a source of the first mos tube S1, a drain of the first mos tube S1 is electrically connected to an anode of the first cell GB1, a gate of the first mos tube S1 is electrically connected to the equalizing control circuit, the first inductor L1 is electrically connected to a source of the first mos tube S1 and the cathode of the first cell GB1, respectively, and the first mos tube S1 is an Nmos tube.

In this embodiment, the mth equalizing bypass Pm includes an mth diode VDm, an mth inductor L M, and an Mmos tube Sm, a cathode of the mth diode VDm is connected to an anode of the first cell GB1, an anode of the mth diode VDm is electrically connected to a drain of the mth mos tube Sm, a source of the mth diode Sm is electrically connected to a cathode of the mth cell GBm, a gate of the mth tube Sm is electrically connected to the equalizing control circuit, the mth inductor L M is electrically connected to a drain of the mth mos tube Sm and an anode of the mth cell GBm, respectively, and the mth diode VDm is an N mos tube.

In the equalization bypass, all the shunt modules (mos tube Sm, inductor L m and diode VDm) of other equalization bypasses transfer redundant electric quantity from the corresponding battery to the upstream battery, and the first equalization bypass transfers redundant electric quantity to the downstream battery due to the unidirectional conduction function of the diode VD.

In this embodiment, the equalization control circuit is an 89C51 chip.

Calculation of switching tube duty ratio

The state of charge soc (state of charge) of the battery at the time of charging can be obtained by the following empirical formula, where V is the terminal voltage of the battery.

SOC＝-0.24V 2+7.218V-53.088 (1)

The SOC is the ratio of the current capacity to the rated capacity of the battery, and is Q/Q TOTA L× 100%.

The storage capacity Q of the single battery is determined by converting the battery voltage detected at the end of the voltage detection phase into a state of charge_est，nHaving a corresponding relation to SOC, Q_est，nCan be estimated, n is the number of cells.

In the charge balance stage, the electric quantity charged into the single battery from the main charger is I_chT_cep. Wherein, T_cepIs the time of the equalizing charge phase in a charge cycle, I_chThe charging efficiency of the single battery. Target Q of uniform charge for balancing storage capacity of single batteries in uniform charge stage_tarThe method comprises the following steps:

however, the charge transfer between the activated bypass and the other battery is mutually affected, and the current output from the single battery to the other battery through the bypass and the received charge current are difficult to calculate by a simple formula. However, Gauss-Seidel iterative methods can solve this problem.

Desired storage capacity Q_nCan be calculated using the following equation:

Q_n＝Q_est，n+(I_obt，n-I_dis，n+I_ch)T_cep(3)

wherein, I_dis，nIs the average current in a switching cycle, I_obt，nIs the current drawn from the other triggered bypass. Q_tarIs that the battery is charged in an ideal state for a period T_sAmount of charge, Q, at the time of uniform charge_nIs the desired storage capacity, take Q_tar＝Q_nI.e., (2), (3) are equal. And obtaining a calculation formula of the duty ratio through corresponding conversion:

function f here_nIs only a schematic function, representing D_nAnd D₁...D_NThere is a relationship.

Fig. 4 shows a control flow. In order to verify the self-adaptive equalizing charge method, an experiment and analysis are carried out by taking a storage battery group GB consisting of two single battery groups GB as an example, and the regulating effect of a switching tube in a bypass on voltage is mainly verified.

As shown in fig. 5-6, since there is no existing battery, the experiment was performed with a replacement battery. The internal resistance and terminal voltage of the accumulator are changed continuously in the charging process, the accumulator accumulates energy in the charging process, and the experiment is carried out by adopting 'resistor series capacitance' to replace a single accumulator according to the physical property analysis and related data of the accumulator.

In the experiment, two low-power NPN transistors C1815(Q1, Q2) are used to replace the switching transistor, and the P1.0 and P1.1 pins of the 89C51 chip are used to control the switching of Q1 and Q2. Meanwhile, the terminal voltages V1 and V2 of the storage battery are collected by a differential amplifying circuit and are transmitted to the CPU through A/D conversion. In the whole process, the voltage is sampled once every 20ms, and the upper computer is uploaded every 1s and stored and automatically drawn.

The utility model relates to a novel B²The MS battery equalization management system may be implemented by using a practical software, but the software used is the software most commonly used by those skilled in the art, and is not the scope of the claims.

Finally, it should be noted that: various modifications and alterations of this invention may be made by those skilled in the art without departing from the spirit and scope of this invention. Thus, to the extent that such modifications and variations of the present invention fall within the scope of the present claims and their equivalents, it is intended that the present invention encompass such modifications and variations as well.

Claims

1. Novel B²An MS storage battery balance management system is provided,the battery pack is characterized by comprising a battery pack GB formed by connecting N single batteries in series, wherein the battery pack is connected on a main loop, and the battery pack further comprises a CPU monitoring unit, a monitoring interface unit, a balance control circuit, N battery data acquisition units and N bypass units, wherein the battery data acquisition units are connected with the single batteries in parallel and used for acquiring data of each single battery, the bypass units are connected with the single batteries in parallel, the battery data acquisition units and the bypass units are electrically connected with the monitoring interface unit, the monitoring interface unit is electrically connected with the CPU monitoring unit, the CPU monitoring unit is electrically connected with the balance control circuit, the balance control circuit is electrically connected with the N bypass power supplies, and N is a positive integer between 1 and 128.

2. A novel compound of claim 1²The MS storage battery equalization management system is characterized in that the bypass unit is an equalization bypass P connected in parallel on the single battery, the N equalization bypasses correspond to the N single batteries GBn one to one, wherein the input end of a first equalization bypass P1 is electrically connected with the anode of a single battery GB1, and the output end of the first equalization bypass P1 is electrically connected with the cathode of the single battery GB 1; the input end of the Mth equalizing bypass Pm is electrically connected with the positive electrode of the Mth single battery GBm, the output end of the Mth equalizing bypass Pm is electrically connected with the positive electrode of the first single battery GB1, the control end of the equalizing bypass P is electrically connected with the equalizing control circuit, wherein M is a positive integer between 2 and 128.

3. A novel compound of claim 2²The MS storage battery equalization management system is characterized in that the first equalization bypass P1 comprises a first diode VD1, a first inductor L1 and a first mos tube S1, the anode of the first diode VD1 is connected with the cathode of the M single battery GBm, the cathode of the first diode VD1 is electrically connected with the source of the first mos tube S1, the drain of the first mos tube S1 is electrically connected with the anode of the first single battery GB1, the gate of the first mos tube S1 is electrically connected with the equalization control circuit, and the first inductors L1 are respectively and electrically connected with the first mos tubeA source electrode of S1 and a cathode electrode of the first unit cell GB1, and the first mos tube S1 is an Nmos tube.

4. A novel compound of claim 2²The MS storage battery equalization management system is characterized in that the mth equalization bypass Pm includes an mth diode VDm, an mth inductor L M, and an mth mos tube Sm, a cathode of the mth diode VDm is connected to an anode of the first cell GB1, an anode of the mth diode VDm is electrically connected to a drain of the mth mos tube Sm, a source of the mth mos tube Sm is electrically connected to a cathode of the mth cell GBm, a gate of the mth mos tube Sm is electrically connected to the equalization control circuit, the mth inductor L M is electrically connected to a drain of the mth mos tube Sm and an anode of the mth cell GBm, respectively, and the mth mos tube Sm is an Nmos tube.

5. A novel compound of claim 1²The MS storage battery balance management system is characterized in that the balance control circuit is an 89C51 chip.