CN211125693U - L ED packaging support and packaging structure - Google Patents
L ED packaging support and packaging structure Download PDFInfo
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- CN211125693U CN211125693U CN201922252769.3U CN201922252769U CN211125693U CN 211125693 U CN211125693 U CN 211125693U CN 201922252769 U CN201922252769 U CN 201922252769U CN 211125693 U CN211125693 U CN 211125693U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 77
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052737 gold Inorganic materials 0.000 claims abstract description 39
- 239000010931 gold Substances 0.000 claims abstract description 39
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 31
- 229910003306 Ni3Sn4 Inorganic materials 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 124
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 37
- 239000010949 copper Substances 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 22
- 229910000765 intermetallic Inorganic materials 0.000 claims description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002344 surface layer Substances 0.000 claims description 6
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 16
- 238000005538 encapsulation Methods 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 3
- 239000006071 cream Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000005476 soldering Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000004090 dissolution Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 206010066054 Dysmorphism Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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Abstract
The utility model provides an L ED encapsulation support and packaging structure, the support includes the base plate, set up in pad on the base plate is connected with the electrode of L ED chip, the area of pad is greater than the electrode area of L ED chip, the pad top layer is the gold layer, the thickness on gold layer is less than or equal to 25nm, through setting up the gold layer thickness on pad top layer at 25nm and following within range for in the welding chip in-process, the difficult diffusion of tin cream, and can be abundant dissolve into the nickel layer, thereby form good Ni with nickel and form good Ni3Sn4The firm degree of welding of L ED chip is effectively guaranteed on the IMC layer, and the chip is difficult for droing, and packaging structure's reliability promotes greatly.
Description
Technical Field
The utility model relates to a device encapsulation technical field especially relates to an L ED encapsulates support and packaging structure.
Background
With the increasing demand for pixels on display screens, the pixel pitch is required to be smaller, the L ED chips and the packaging devices thereof have smaller sizes, and the manufacturing process is difficult and challenging more and more.
During welding, the gold layer can be quickly dissolved into a main body of the soldering tin at a speed which is tens of thousands of times faster than nickel (Ni) (the dissolution speed is 117 microinches/second) to form a dispersed interface intermetallic compound (IMC) AuSn at four positions4And the interface intermetallic compound (IMC) Ni formed at a slower rate by the nickel under the gold layer and the solder3Sn4It is the key to determine the weld strength, only good Ni formation3Sn4The IMC layer of (a) can ensure the firmness of the welding. If the gold layer is too thick, it will cause solder to diffuse and not dissolve well into the nickel layer to form good Ni3Sn4The IMC layer even causes 'gold brittleness', and finally reduces the welding strength; if the gold layer is too thin, the gold layer cannot completely cover the nickel layer, and a nickel leakage phenomenon is generated, so that the nickel layer is oxidized to influence the performance of the packaging structure. Therefore, the packaging support with the thickness suitable for the gold layer is also the focus of the current research.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an L ED package support, which can effectively solve the problems of low welding strength, easy chip falling off and nickel leakage caused by poor thickness of the gold layer of the bonding pad in the prior art, and also provide a L ED package structure using the package support.
In order to achieve the above and other related objects, the present invention provides an L ED package support, which includes a substrate, a pad disposed on the substrate and connected to an electrode of a L ED chip, wherein the area of the pad is larger than that of the electrode of the L ED chip, the surface layer of the pad is a gold layer, and the thickness of the gold layer is smaller than or equal to 25 nm.
As an optimized proposal of the utility model, the thickness of the gold layer is 10-20 nm.
As an optimized proposal of the utility model, the area of the bonding pad is 1.2 to 200 times of the area of the L ED chip electrode.
As a preferable scheme of the present invention, the L ED includes Mini L ED and Micro L ED.. Mini L ED usually refers to L ED chip with at least one side length less than 300 μm, such as 150 μm × 150 μm, and Micro L ED usually refers to L ED chip with a side length of 1-100 μm.
As an optimized scheme of the utility model, the pad is the laminated structure including titanium layer, copper layer, nickel layer and golden layer.
As a preferred scheme of the utility model, the titanium layer does the bottom of pad, the copper layer set up in on the titanium layer, the nickel layer set up in on the copper layer, the gold layer does the top layer of pad.
As a preferred scheme of the utility model, the thickness of titanium layer is 50nm ~ 500nm, the thickness of copper layer is 20 mu m ~ 50 mu m.
As an optimized proposal of the utility model, the thickness of the nickel layer is 500-5000 nm.
As a preferred embodiment of the present invention, the copper layer includes at least three layers of copper structures.
As a preferred scheme of the utility model, the copper layer includes three-layer copper structure, wherein bottom copper structure thickness in the copper layer is 300nm ~ 500nm, and intermediate level copper structure thickness is 3 mu m ~ 5 mu m, and upper copper structure thickness is 20 mu m ~ 30 mu m.
As an optimized scheme of the utility model, the shape of pad is rectangle, step form or dysmorphism structure, the step form pad includes the one-level step at least.
As an optimized scheme of the utility model, the encapsulation support is two-sided distribution encapsulation support or single face distribution encapsulation support.
As a preferable aspect of the present invention, the pad includes a first pad and a second pad, and a gap between the first pad and the second pad is 50 μm or less.
As a preferable embodiment of the present invention, the first pad and the second pad are perpendicular to the width of the gap is 1mm or less.
The utility model provides an L ED packaging structure, packaging structure includes above-mentioned arbitrary L ED encapsulation support, be fixed in L ED chip on the encapsulation support and cover in the solid glue of sealing on the L ED chip.
As a preferred scheme of the utility model, include Ni between L ED chip and the encapsulation support3Sn4The interface intermetallic compound layer has a thickness of 1 to 3 μm.
As a preferred scheme of the utility model, the nickel-plating device also comprises a nickel layer which is positioned on the Ni3Sn4An interfacial intermetallic layer and the substrate of the scaffold.
As a preferred embodiment of the present invention, Ni3Sn4The cross-sectional area of the interface intermetallic compound layer is 1.2 to 1.5 times of the area of the L ED chip electrode.
As a preferable proposal of the utility model, one side of the L ED chip is less than 300 μm.
As mentioned above, the utility model has the following beneficial effects:
the utility model discloses a packaging support, including the base plate, set up in pad on the base plate is connected with the electrode of L ED chip, the area of pad is greater than the electrode area of L ED chip, the pad top layer is the gold layer, the thickness on gold layer is less than or equal to 25nm, through the gold layer thickness setting with the pad top layer at 25nm and following within range for among the welding chip process, the difficult diffusion of tin cream, and can be abundant dissolve into the nickel layer, thereby form good Ni with nickel3Sn4The IMC layer effectively ensures the welding firmness of the L ED chip, the chip is not easy to fall off, the reliability of the packaging structure is greatly improved, and furthermore, the IMC layer is practicalThe novel gold layer thickness optimization range is 10-20 nm, the gold layer within the thickness range can ensure the welding firmness degree and avoid nickel leakage, and the nickel layer is effectively prevented from being oxidized.
Drawings
Fig. 1 is a state diagram of solder paste of a conventional package support after reflow soldering in a die bonding state.
Fig. 2 is a state diagram of solder paste of a conventional package support after reflow soldering in an unfixed state.
Fig. 3 is a diagram showing a reliability test of a package structure using a conventional support.
Fig. 4 is a schematic view of an L ED package support according to an embodiment of the present invention.
Fig. 5 is a state diagram of solder paste after reflow soldering of an L ED package support according to an embodiment of the invention.
Fig. 6 shows a reliability test chart of a package structure using a bracket according to an embodiment of the present invention.
Fig. 7 is a schematic view of an L ED package support according to an embodiment of the present invention.
The reference numbers illustrate:
1. substrate
2. Bonding pad
3. Gold layer
4. Titanium layer
5. Copper layer
6. Nickel layer
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
Please refer to fig. 1 to 7. It should be understood that the drawings provided in the embodiments of the present application are only for illustrating the basic concept of the present invention, and although only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated. The structure, ratio, size and the like shown in the drawings are only used for matching with the content disclosed in the specification, so that those skilled in the art can understand and read the description, and do not limit the limit conditions that the present application can be implemented, so that the present invention has no technical essence, and any structural modification, ratio relationship change or size adjustment still falls within the scope that the technical content disclosed in the present application can cover without affecting the efficacy and the achievable purpose of the present invention.
The thickness of a gold layer of an existing common packaging support is generally more than 50nm, the size of an existing L ED chip is gradually reduced, the area of a bonding pad is much larger than that of the chip, the influence degree of the gold layer on the diffusion and dissolution of solder paste is further increased in the welding process, as shown in figures 1 and 2, the solder paste states of the existing packaging support after reflow soldering in a die bonding state and an unfixed state are respectively shown, the fact that the solder paste is diffused in a large range and is not dissolved sufficiently in the two cases can be obviously seen, and meanwhile, when the relation between the ratio (delta VF) of the voltage of the existing packaging structure and the initial voltage value of the packaging structure and the change of the initial voltage value along with time is tested to judge the reliability of the packaging structure, as shown in figure 3, the delta VF of the existing packaging structure is increased, the situation that the L ED chip is loosened or even falls off along with the increase of time, the voltage is abnormally increased, so that the packaging structure fails, and the problem that the firmness of.
The first embodiment is as follows:
as shown in fig. 4, the present embodiment provides an L ED package support, where the support includes a substrate 1, a pad 2 disposed on the substrate 1 and connected to an electrode of a L ED chip, an area of the pad 2 is larger than an area of the electrode of the L ED chip, a surface layer of the pad 1 is a gold layer 3, and a thickness w of the gold layer 3 is less than or equal to 25 nm.
Optionally, the thickness w of the gold layer 3 is 10-20 nm.
Optionally, the area of the bonding pad 2 is 1.2-200 times that of the L ED chip electrode, for example, a 5 mil-9 mil chip has an area ratio of preferably 1.2-2, and as the chip size is smaller, the area ratio will increase, for example, 2 mil-4 mil, and the area ratio may be 50-200.
Optionally, the bonding pad 2 is a laminated structure including a titanium layer 4, a copper layer 5, a nickel layer 6 and a gold layer 3.
Optionally, the titanium layer 4 is a bottom layer of the pad 2, the copper layer 5 is disposed on the titanium layer 4, the nickel layer 6 is disposed on the copper layer 5, and the gold layer 3 is a surface layer of the pad 2.
Optionally, the thickness of the titanium layer 4 is 50nm-500nm, and the thickness of the copper layer 5 is 20 μm-50 μm.
Optionally, the thickness of the nickel layer 6 is 500-5000 nm.
In the package support in this embodiment, the diffusion condition and the dissolution condition of the solder paste after reflow soldering are shown in fig. 5, and bright spots in the drawing represent the solder paste, so that it can be obviously seen that the solder paste is not diffused and is fully dissolved, which indicates that in the thickness range of the gold layer provided in this embodiment, the package support can effectively avoid the diffusion of the solder paste after reflow soldering, and ensure that the solder paste is fully dissolved into the nickel layer, so as to form good Ni3Sn4Furthermore, the preferred range of the thickness of the gold layer is 10-20 nm, the gold layer within the thickness range can not only ensure the welding firmness, but also avoid the occurrence of nickel leakage, and effectively prevent the nickel layer from being oxidized.
Meanwhile, the packaging structure using the packaging support of the embodiment is also subjected to corresponding reliability verification, as shown in fig. 6, it can be seen that the reliability of the packaging structure after the packaging support of the embodiment is applied is greatly improved, and the voltage is in a stable state for a long time, which indicates that the packaging support of the embodiment can be well welded with an L ED chip and ensures the stability of the welding strength.
Optionally, the L ED includes Mini L ED and Micro L ED., the Mini L ED generally refers to L ED chips with at least one side length of less than 300 μm, such as 150 μm × 150 μm, and the Micro L ED generally refers to L ED chips with a side length of 1-100 μm.
Optionally, the pad 2 is shaped as a rectangle, a step or a special-shaped structure, and the step-shaped pad includes at least one step.
Optionally, the package support is a double-sided wiring package support or a single-sided wiring package support.
Optionally, the pad 2 includes a first pad and a second pad, and a gap between the first pad and the second pad is 50 μm or less.
Optionally, a width of the first pad and the second pad perpendicular to the gap is 1mm or less.
In the package support in this embodiment, the thickness of the gold layer on the surface layer of the pad is less than or equal to 25nm, so that in the welding process, the solder paste is not easy to diffuse, and can be fully dissolved into the nickel layer, thereby forming good Ni with the nickel3Sn4The firm degree of welding of L ED chip is effectively guaranteed on the IMC layer, and the chip is difficult for droing, and packaging structure's reliability promotes greatly.
Example two:
the present embodiment provides an L ED package support, which has the same basic structure as that of the first embodiment, and therefore, the description thereof is omitted, and the difference from the first embodiment is that the copper layer 5 in the present embodiment includes at least three layers of copper structures.
Alternatively, the copper layer 5 comprises a three-layer copper structure, as shown in fig. 7, wherein the thickness of the bottom layer copper structure in the copper layer 5 is 300nm-500nm, the thickness of the middle layer copper structure is 3 μm-5 μm, and the thickness of the upper layer copper structure is 20 μm-30 μm.
Example three:
the present embodiment provides an L ED package structure, which includes the L ED package support, the L ED chip fixed on the package support, and the sealing glue covering the L ED chip described in any of the above embodiments.
Optionally, Ni is included between the L ED chip and the packaging support3Sn4The interface intermetallic compound layer has a thickness of 1 to 3 μm.
Optionally, the nickel coating is positioned on the Ni3Sn4An interfacial intermetallic layer and the substrate of the scaffold.
Alternatively, the Ni3Sn4The cross-sectional area of the interface intermetallic compound layer is 1.2 to 1.5 times of the area of the L ED chip electrode.
Optionally, one side of the L ED chip is 300 μm or less.
To sum up, the utility model provides an L ED encapsulation support and packaging structure, the support includes the base plate, set up in pad on the base plate is connected with the electrode of L ED chip, the area of pad is greater than the electrode area of L ED chip, the pad top layer is the gold layer, the thickness of gold layer is less than or equal to 25nm3Sn4The IMC layer, effectively guarantee L ED chip's the firm degree of welding, the chip is difficult for droing, and packaging structure's reliability promotes greatly, and furtherly, the utility model also provides the preferred scope of golden layer thickness is 10 ~ 20nm, and the golden layer of this thickness scope not only can guarantee that the firm degree of welding still can avoid leaking the condition of nickel and take place, effectively prevents that the nickel layer from being oxidized the utility model provides an include among the L ED packaging structure encapsulation support, so, the utility model discloses effectively overcome all kinds of shortcomings among the prior art and possess high industrial value.
The above embodiments are merely exemplary to illustrate the structure and efficacy of the present invention, and are not intended to limit the present invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (19)
1. An L ED packaging support is characterized by comprising a substrate, a bonding pad arranged on the substrate and connected with an electrode of a L ED chip, wherein the area of the bonding pad is larger than that of the electrode of the L ED chip, the surface layer of the bonding pad is a gold layer, and the thickness of the gold layer is smaller than or equal to 25 nm.
2. The L ED package support according to claim 1, wherein the gold layer has a thickness of 10-20 nm.
3. The L ED package support of claim 1, wherein the land area is 1.2-200 times the area of the L ED chip electrodes.
4. The L ED package holder of claim 1, wherein the L ED includes Mini L ED and Micro L ED.
5. The L ED package support of claim 1, wherein the bonding pad is a laminate comprising a titanium layer, a copper layer, a nickel layer and a gold layer.
6. The L ED package support of claim 5, wherein the titanium layer is an underlayer of the bonding pad, the copper layer is disposed over the titanium layer, the nickel layer is disposed over the copper layer, and the gold layer is a surface layer of the bonding pad.
7. The L ED package support according to claim 5, wherein the titanium layer has a thickness of 50nm-500nm and the copper layer has a thickness of 20 μm-50 μm.
8. The L ED package support according to claim 5, wherein the nickel layer has a thickness of 500-5000 nm.
9. The L ED package support according to claim 5, wherein the copper layer comprises at least three layers of copper structure.
10. The L ED package support of claim 9, wherein the copper layer comprises a three-layer copper structure, wherein the copper layer has a bottom copper structure thickness of 300nm-500nm, a middle copper structure thickness of 3 μm-5 μm, and an upper copper structure thickness of 20 μm-30 μm.
11. An L ED package support according to claim 1, wherein the pads are rectangular, stepped or shaped, and the stepped pads include at least one step.
12. An L ED package holder according to claim 1, wherein the package holder is a double-sided wire-harness package holder or a single-sided wire-harness package holder.
13. An L ED package support according to claim 1, wherein the pads comprise a first pad and a second pad, and the gap between the first pad and the second pad is 50 μm or less.
14. An L ED package support according to claim 13, wherein the first and second pads have a width perpendicular to the gap of 1mm or less.
15. An L ED package structure, wherein the package structure comprises the L ED package support of any one of claims 1-14, a L ED chip mounted on the package support, and an encapsulant covering the L ED chip.
16. The L ED package structure of claim 15, wherein the L ED chip and package support include Ni therebetween3Sn4The interface intermetallic compound layer has a thickness of 1 to 3 μm.
17. The L ED package structure of claim 16, further comprising a nickel layer on the Ni layer3Sn4An interfacial intermetallic layer and the substrate of the scaffold.
18. The L ED package structure of claim 16, wherein the Ni is Ni3Sn4The cross-sectional area of the interface intermetallic compound layer is 1.2 to 1.5 times of the area of the L ED chip electrode.
19. The L ED package structure of claim 15, wherein a side of the L ED chip is less than 300 μm.
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|---|---|---|---|
| CN201922252769.3U CN211125693U (en) | 2019-12-16 | 2019-12-16 | L ED packaging support and packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922252769.3U CN211125693U (en) | 2019-12-16 | 2019-12-16 | L ED packaging support and packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023159387A1 (en) * | 2022-02-23 | 2023-08-31 | 京东方科技集团股份有限公司 | Array substrate and light-emitting device |
| CN117317113A (en) * | 2023-11-27 | 2023-12-29 | 江西兆驰半导体有限公司 | LED chip capable of improving chip solder joint interface reliability and preparation method thereof |
-
2019
- 2019-12-16 CN CN201922252769.3U patent/CN211125693U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023159387A1 (en) * | 2022-02-23 | 2023-08-31 | 京东方科技集团股份有限公司 | Array substrate and light-emitting device |
| CN117317113A (en) * | 2023-11-27 | 2023-12-29 | 江西兆驰半导体有限公司 | LED chip capable of improving chip solder joint interface reliability and preparation method thereof |
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