CN211125641U

CN211125641U - Semiconductor structure for maximum pooling, chip and apparatus for maximum pooling

Info

Publication number: CN211125641U
Application number: CN201922350766.3U
Authority: CN
Inventors: 余兴; 蒋维楠
Original assignee: ZHEJIANG TSINGHUA YANGTZE RIVER DELTA RESEARCH INSTITUTE; ICLeague Technology Co Ltd
Current assignee: ZHEJIANG TSINGHUA YANGTZE RIVER DELTA RESEARCH INSTITUTE; ICLeague Technology Co Ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2020-07-28
Anticipated expiration: 2029-12-24

Abstract

A semiconductor structure for maximum pooling, a chip and an apparatus for maximum pooling, wherein the semiconductor structure for maximum pooling comprises: the first substrate comprises a plurality of control areas, and each control area comprises a plurality of control modules arranged in parallel to the first surface; the second substrate is bonded with the first substrate and comprises a plurality of operation areas, and each operation area comprises a plurality of operation modules which are arranged in parallel to the third surface; and a third substrate bonded to the first substrate or the second substrate, the third substrate including a plurality of storage regions, the storage regions including a plurality of storage modules arranged in parallel to the fifth surface. The semiconductor structure for maximum pooling can improve the performance of a chip for maximum pooling.

Description

Semiconductor structure for maximum pooling, chip and apparatus for maximum pooling

Technical Field

The utility model relates to a semiconductor field especially relates to a semiconductor structure, chip and device are used to biggest pooling processing for the biggest pooling processing.

Background

Nowadays, the application of artificial intelligence is occurring in more and more fields such as automatic driving, image recognition, medical diagnosis, games, financial data analysis and search engines, etc., and especially the use of neural network algorithms is becoming more and more widespread. The method is well applied to the fields of image recognition, voice recognition, natural language processing and the like. However, as the complexity of the neural network algorithm is higher and higher, the types and the number of the related data operations are increased continuously, and higher requirements are put forward on the performance of the chip.

However, in the conventional chip, the circuits of the various functional modules are formed on the same wafer, so that not only the data transmission between the functional modules is limited by the bandwidth and the data transmission speed of the chip is reduced, thereby reducing the operation speed of the chip, but also the circuits of the functional modules occupy a larger area, thereby reducing the integration level of the chip, and therefore, the performance of the conventional chip still needs to be improved.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem provide a semiconductor structure, chip and device are used to biggest pooling processing for the biggest pooling processing to improve the performance that is used for the chip of the biggest pooling processing.

In order to solve the technical problem, the technical scheme of the utility model a semiconductor structure for processing of biggest pooling is provided, include: the first substrate is provided with a first face and a second face which are opposite, the first substrate comprises a plurality of control areas, and the control areas comprise a plurality of control modules which are arranged in parallel to the first face; a second substrate bonded to the first substrate, the second substrate having a third surface and a fourth surface opposite to each other, the first surface facing the third surface, the second substrate including a plurality of operation regions, each of the control regions overlapping with one of the operation regions, the operation regions including a plurality of operation modules arranged in parallel to the third surface, the circuits of the control modules and the circuits of the operation modules being electrically interconnected in the control regions and the operation regions overlapping with each other; a third substrate bonded to the first substrate or the second substrate, the third substrate having a fifth surface facing the second surface if the third substrate is bonded to the first substrate, the fifth surface facing the fourth surface if the third substrate is bonded to the second substrate, the third substrate including a plurality of storage areas, each of the storage areas overlapping one of the control area and one of the operation area, the storage areas including a plurality of memory modules arranged in parallel to the fifth surface, in the mutually overlapping storage area, control area and operation area, circuits of the memory modules being electrically interconnected to circuits of the operation module, and circuits of the memory modules being electrically interconnected to circuits of the control module.

Optionally, in the control area and the operation area which overlap each other, the circuit of each control module is electrically interconnected with the circuit of more than one operation module.

Optionally, in the storage area, the control area and the operation area which overlap with each other, the circuit of each control module is electrically interconnected with the circuit of more than 1 memory module, and the circuit of the memory module which is electrically interconnected with the circuit of the control module is also electrically interconnected with the circuit of the operation module, and the circuit of the operation module is electrically interconnected with the circuit of the control module.

Optionally, the circuit of the operation module includes more than 1 comparator.

Optionally, the circuit of the operation module further includes 1 or more operators.

Optionally, the arithmetic unit includes one or more of an adder, a multiplier, a divider and a comparator.

Optionally, the circuit of the storage module includes one or both of a buffer and a register.

Optionally, the buffer includes one or both of a cache buffer and a neuron buffer.

Optionally, the control module is configured to obtain and analyze a maximum pooling instruction to obtain data to be operated, a pooling core, and a target address; after the data to be operated, the pooling core and the target address are obtained, the control module is further used for transmitting the data to be operated and the pooling core to the operation module.

Optionally, the operation module is configured to obtain the data to be operated and a pooling core, perform maximum pooling operation on the data to be operated according to the pooling core to obtain an operation result, and store the operation result in the target address.

Optionally, the control module is further configured to transmit the data to be operated and the pooled core to the storage module; the storage module is used for acquiring the data to be operated and the pooling core and storing the data to be operated and the pooling core.

Optionally, the control area further includes a plurality of memory addressing modules arranged parallel to the first substrate surface, and a circuit of each memory addressing module is electrically interconnected with a circuit of one control module.

Optionally, the control module has a first projection on the first surface, the operation module has a second projection on the first surface, the storage module has a third projection on the first surface, and in the storage area, the control area, and the operation area that overlap with each other, the second projection of the operation module and the third projection of the storage module, which are electrically interconnected between circuits, are both within the range of the first projection of the control module.

Optionally, the first substrate further includes a first metal interconnection layer, the first metal interconnection layer is electrically interconnected with the circuit of the control module, the first surface exposes the surface of the first metal interconnection layer, the second substrate further includes a second metal interconnection layer, the second metal interconnection layer is electrically interconnected with the circuit of the operation module, the third surface exposes the surface of the second metal interconnection layer, and in the control area and the operation area which are overlapped with each other, the first metal interconnection layer and the second metal interconnection layer are bonded to each other.

Optionally, if the third substrate is bonded to the first substrate, the first substrate further includes a third metal interconnection layer, the third metal interconnection layer is electrically interconnected to the circuit of the control module, the second surface exposes the surface of the third metal interconnection layer, the third substrate further includes a fifth metal interconnection layer, the fifth metal interconnection layer is electrically interconnected to the circuit of the storage module, the fifth surface exposes the surface of the fifth metal interconnection layer, and the third metal interconnection layer and the fifth metal interconnection layer are bonded to each other.

Optionally, if the third substrate with the second substrate bonding, still include fourth metal interconnect layer in the second substrate, fourth metal interconnect layer with the circuit electricity interconnection of operation module, the fourth face exposes fourth metal interconnect layer surface, still include fifth metal interconnect layer in the third substrate, fifth metal interconnect layer with the circuit electricity interconnection of storage module, the fifth face exposes fifth metal interconnect layer surface, and fourth metal interconnect layer with fifth metal interconnect layer interbonding.

Correspondingly, the technical scheme of the utility model a chip based on above-mentioned arbitrary biggest pooling is handled and is used semiconductor construction is still provided, include: the device comprises a control area, storage areas and an operation area, wherein each control area is overlapped with one operation area, and each storage area is overlapped with one control area and one operation area.

Correspondingly, the technical scheme of the utility model a device is used in the biggest pooling still is provided to technical scheme, a serial communication port, include: the above chip; and the interface device is used for realizing data transmission between the chip and external equipment, and is connected with the chip.

Optionally, the method further includes: the control device is used for monitoring the state of the chip and is connected with the chip; a memory device for storing data in the chip, the memory device being connected to the chip.

Compared with the prior art, the utility model discloses technical scheme has following beneficial effect:

in the semiconductor structure for maximum pooling processing of the technical solution of the present invention, on the one hand, in the storage area, the control area and the operation area overlapped with each other, the circuit of the control module and the circuit of the operation module are electrically interconnected through bonding, the circuit of the storage module and the circuit of the operation module are electrically interconnected, and the circuit of the storage module and the circuit of the control module are electrically interconnected, so that data can be directly transmitted among the circuit of the operation module, the circuit of the control module and the circuit of the storage module, thereby increasing the speed of transmitting data, increasing the bandwidth of the semiconductor structure for maximum pooling processing, further increasing the operation processing speed of the chip for maximum pooling processing, improving the performance of the chip for maximum pooling processing, and reducing the operation time of the chip for maximum pooling processing, the power consumption of the chip for the maximum pooling process is reduced; on the other hand, since the first substrate is bonded to the second substrate, the third substrate is bonded to the first substrate or the second substrate, and the control region, the operation region, and the storage region overlap, the area of the semiconductor structure for maximum pooling is reduced with a simple structure, thereby improving the integration of the chip for maximum pooling.

Furthermore, the control area further comprises a plurality of memory addressing modules which are arranged in parallel to the first surface, and the circuit of each memory addressing module is electrically interconnected with the circuit of one control module, so that the control modules can more quickly address through the circuits of the memory addressing modules, and the operation speed of the chip for maximum pooling is increased.

Further, the control module is provided with a first projection on the first surface, the operation module is provided with a second projection on the first surface, the storage module is provided with a third projection on the first surface, and the second projection of the operation module and the third projection of the storage module which are electrically interconnected are formed between circuits and are within the range of the first projection of the control module, so that the mutual bonding among the control area, the storage area and the operation area is facilitated, and the area occupied by the storage module, the control module and the operation module is reduced, so that the area of the semiconductor structure for maximum pooling processing is reduced by a simple structure, and the integration level of a chip for maximum pooling processing is improved.

Drawings

Fig. 1 to 4 are schematic cross-sectional views illustrating steps of forming a semiconductor structure for maximum pooling according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a semiconductor structure for maximum pooling in accordance with an embodiment of the present invention;

fig. 6 is a schematic cross-sectional structure diagram of a chip according to an embodiment of the present invention;

FIG. 7 is a schematic structural view of an apparatus for maximum pooling in accordance with an embodiment of the present invention;

fig. 8 to 11 are schematic cross-sectional views of respective steps of forming a semiconductor structure for maximum pooling according to another embodiment of the present invention;

fig. 12 is a schematic structural diagram of a semiconductor structure for maximum pooling in accordance with another embodiment of the present invention;

fig. 13 is a schematic cross-sectional view of a chip according to another embodiment of the present invention;

fig. 14 is a schematic structural view of a maximum pooling treatment apparatus according to another embodiment of the present invention.

Detailed Description

As described in the background art, since the circuits of the various functional modules are formed on the same wafer in the conventional chip, not only is the data transmission between the functional modules limited by the bandwidth and the data transmission speed of the chip reduced, and thus the operation speed of the chip is reduced, but also the circuits of the functional modules occupy a larger area, and thus the integration level of the chip is low, and thus the performance of the conventional chip still needs to be improved.

For solving the technical problem, an embodiment of the utility model provides a semiconductor structure is used in biggest pooling treatment, include: the first substrate is provided with a first face and a second face which are opposite, the first substrate comprises a plurality of control areas, and the control areas comprise a plurality of control modules which are arranged in parallel to the first face; a second substrate bonded to the first substrate, the second substrate having a third surface and a fourth surface opposite to each other, the first surface facing the third surface, the second substrate including a plurality of operation regions, each of the control regions overlapping with one of the operation regions, the operation regions including a plurality of operation modules arranged in parallel to the third surface, the circuits of the control modules and the circuits of the operation modules being electrically interconnected in the control regions and the operation regions overlapping with each other; a third substrate bonded to the first substrate or the second substrate, the third substrate having a fifth surface facing the second surface if the third substrate is bonded to the first substrate, the fifth surface facing the fourth surface if the third substrate is bonded to the second substrate, the third substrate including a plurality of storage areas, each of the storage areas overlapping one of the control area and one of the operation area, the storage areas including a plurality of memory modules arranged in parallel to the fifth surface, in the mutually overlapping storage area, control area and operation area, circuits of the memory modules being electrically interconnected to circuits of the operation module, and circuits of the memory modules being electrically interconnected to circuits of the control module. Thus, the semiconductor structure for maximum pooling can improve the performance of the chip for maximum pooling.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Fig. 1 to 4 are schematic cross-sectional views of respective steps of forming a semiconductor structure for maximum pooling according to an embodiment of the present invention.

Referring to fig. 1, a first substrate 100 is provided, the first substrate 100 has a first side 101 and a second side 102 opposite to each other, the first substrate 100 includes a plurality of control areas a, the control areas a include a plurality of control modules 110 arranged parallel to the first side 101, and the control modules 110 have circuits 111 of the control modules therein.

The material of the first substrate 100 includes a semiconductor material.

In this embodiment, the material of the first substrate 100 includes silicon.

In other embodiments, the material of the first substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the first substrate 100 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the control module 110 is configured to obtain and analyze a maximum pooling instruction to obtain data to be operated, a pooling kernel and a target address; after the data to be operated, the pooled cores and the target address are obtained, the control module 110 is further configured to transmit the data to be operated and the pooled cores to a subsequent operation module electrically interconnected with the circuit 111 of the control module 110. The control module is further configured to transmit the data to be computed and the pooled cores to a storage module that is subsequently electrically interconnected with the control module 110.

In this embodiment, each of the control areas a includes one control module 110.

In other embodiments, 2 or more than 2 control modules are included in each control zone.

In this embodiment, the first substrate 100 further includes a first metal interconnection layer 120, the first metal interconnection layer 120 is electrically interconnected with the circuit 111 of the control module 110, and the first surface 101 exposes a surface of the first metal interconnection layer 120.

In this embodiment, the first substrate 100 further includes a third metal interconnection layer 130, the third metal interconnection layer 130 is electrically interconnected with the circuit 111 of the control module 110, and the second surface 102 exposes a surface of the third metal interconnection layer 130.

In another embodiment, a third metal interconnect layer is not included in the first substrate.

In this embodiment, the control area a further includes a plurality of memory addressing modules 150 arranged parallel to the first surface 101, the memory addressing modules 150 have circuits 151 of the memory addressing modules therein, and each of the circuits 151 of the memory addressing modules is electrically interconnected with the circuit 111 of one of the control modules.

Specifically, in this embodiment, each of the control areas a includes a memory addressing module 150.

In another embodiment, each control area includes 2 or more than 2 memory addressing modules.

In other embodiments, the control region does not include a memory addressing module.

In this embodiment, the first substrate 100 further includes a first dielectric layer (not shown) surrounding the circuit 111 of the control module, the circuit 151 of the memory addressing module, the first metal interconnection layer 120, and the third metal interconnection layer 130.

Referring to fig. 2, a second substrate 200 is provided, the second substrate 200 has a third surface 203 and a fourth surface 204 opposite to each other, the second substrate 200 includes a plurality of operation regions B, the operation regions B include a plurality of operation modules 210 arranged parallel to the third surface 203, and the operation modules 210 have circuits 211 of the operation modules therein.

The material of the second substrate 200 includes a semiconductor material.

In this embodiment, the material of the second substrate 200 includes silicon.

In other embodiments, the material of the second substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the second substrate 200 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In the present embodiment, the circuit 211 of the operation module 210 includes more than 1 comparator (not shown).

In this embodiment, the circuit 211 of the operation module 210 further includes 1 or more operators (not shown).

In this embodiment, the arithmetic unit includes one or more of an adder, a multiplier, a divider, and a comparator.

The operation module 210 is configured to obtain the data to be operated and the pooling core, perform maximum pooling operation on the data to be operated according to the pooling core to obtain an operation result, and store the operation result in the target address.

In this embodiment, each operation area B includes an operation module 210.

In other embodiments, each of the operation regions includes 2 or more than 2 operation modules.

In this embodiment, the second substrate further includes a second metal interconnection layer 220, the second metal interconnection layer 220 is electrically interconnected with the circuit 211 of the operation module 210, and the third surface 203 exposes the surface of the second metal interconnection layer 220.

In this embodiment, the second substrate 200 further includes a second dielectric layer (not shown) surrounding the second metal interconnection layer 220 and the circuit 211 of the operation module 210.

Referring to fig. 3, a third substrate 300 is provided, the third substrate has a fifth surface 301, the third substrate 300 includes a plurality of memory blocks C, the memory blocks C include a plurality of memory modules 310 arranged parallel to the fifth surface 301, and the memory modules 310 have circuits 311 of the memory modules therein.

The material of the third substrate 300 includes a semiconductor material.

In this embodiment, the material of the third substrate 300 includes silicon.

In other embodiments, the material of the third substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the third substrate 300 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit 311 of the memory module includes one or both of a buffer and a register. The buffer includes one or both of a cache buffer and a neuron buffer.

In this embodiment, the storage module 310 is configured to obtain the data to be operated and the pooled core, and store the data to be operated and the pooled core.

In this embodiment, each of the memory areas C includes a memory module 310 therein.

In other embodiments, each of the memory areas includes 2 or more than 2 memory modules.

In this embodiment, the third substrate 300 further includes a fifth metal interconnection layer 320, the fifth metal interconnection layer 320 is electrically interconnected with the circuit 311 of the memory module, and the fifth surface 301 exposes the surface of the fifth metal interconnection layer 320.

In this embodiment, a third dielectric layer (not labeled) surrounding the fifth metal interconnection layer 320 and the circuit 311 of the memory module is further included in the third substrate 300.

Referring to fig. 4, the first substrate 100 and the second substrate 200 are bonded, the first surface 101 faces the third surface 203, each of the control regions a overlaps one of the operation regions B, and the circuits 111 of the control module and the circuits 211 of the operation module are electrically interconnected in the control regions a and the operation regions B that overlap each other; and, the first substrate 100 and the third substrate 300 are bonded, the fifth surface 301 faces the second surface 102, each of the memory areas C overlaps one of the control areas a and one of the operation areas B, and in the memory area C, the control area a, and the operation area B overlapping each other, the circuit 311 of the memory module and the circuit 211 of the operation module are electrically interconnected, and the circuit 311 of the memory module and the circuit 111 of the control module are electrically interconnected.

Specifically, in the control area a, the operation area B, and the memory area C, which overlap each other, the first metal interconnection layer 120 and the second metal interconnection layer 220 are bonded to each other, and the third metal interconnection layer 130 and the fifth metal interconnection layer 320 are bonded to each other.

In the present embodiment, in the control area a and the operation area B overlapping each other, the circuit 111 of each of the control modules is electrically interconnected with the circuit 211 of one operation module.

In another embodiment, the circuits of each of said control modules are electrically interconnected with the circuits of 2 or more than 2 operational modules in mutually overlapping control and operational zones.

In the present embodiment, in the memory area C, the control area a, and the operation area B overlapping each other, the circuit 111 of each control module and the circuit 311 of 1 memory module are electrically interconnected, and the circuit 311 of the memory module electrically interconnected with the circuit 111 of the control module is also electrically interconnected with the circuit 211 of the operation module, and the circuit 211 of the operation module is electrically interconnected with the circuit 111 of the control module.

In another embodiment, in the memory area, the control area and the operation area overlapped with each other, the circuit of each control module and the circuit of 2 or more memory modules are electrically interconnected, and the circuit of the memory module electrically interconnected with the circuit of the control module is also electrically interconnected with the circuit of the operation module, and the circuit of the operation module is electrically interconnected with the circuit of the control module.

In this embodiment, the control module 110 has a first projection (not shown) on the first surface 101, the computing module 210 has a second projection (not shown) on the first surface 101, the storage module 310 has a third projection (not shown) on the first surface 101, and in the storage area C, the control area a, and the operation area B that overlap with each other, the second projection of the computing module 210 and the third projection of the storage module 310 that are electrically interconnected among circuits are both within the range of the first projection of the control module 110.

Fig. 5 is a schematic structural diagram of a semiconductor structure for maximum pooling in accordance with an embodiment of the present invention.

Accordingly, the present invention also provides a semiconductor structure for maximum pooling formed by the above-mentioned forming method, please refer to fig. 5 on the basis of fig. 4, fig. 4 is a schematic cross-sectional view along the direction X-X1 in fig. 5, which includes: a first substrate 100, the first substrate 100 having a first side 101 and a second side 102 opposite to each other, the first substrate 100 including a plurality of control zones a, the control zones a including a plurality of control modules 110 arranged parallel to the first side 101; a second substrate 200 bonded to the first substrate 100, the second substrate 200 having a third face 203 and a fourth face 204 opposite to each other, the first face 101 facing the third face 203, the second substrate 200 including a plurality of operation regions B, each of the control regions a overlapping with one of the operation regions B, the operation region B including a plurality of operation modules 210 arranged parallel to the third face 203, the circuits 111 of the control modules and the circuits 211 of the operation modules being electrically interconnected in the control regions a and the operation regions B overlapping with each other.

The semiconductor structure for maximum pooling further includes a third substrate 300 bonded to the first substrate 100 or the second substrate 200, the third substrate 300 having a fifth surface 301, the third substrate 300 including a plurality of memory areas C, each of the memory areas C overlapping one of the control areas a and one of the operation areas B, the memory area C including a plurality of memory modules 310 arranged parallel to the fifth surface 301, the circuits 311 of the memory modules being electrically interconnected with the circuits 211 of the operation modules in the memory area C, the control area a, and the operation area B overlapping each other, and the circuits 311 of the memory modules being electrically interconnected with the circuits 111 of the control module.

On the one hand, in the memory area C, the control area A and the operation area B which overlap each other, the electrical interconnection between the circuit 111 of the control module and the circuit 211 of the operation module, the electrical interconnection between the circuit 311 of the memory module and the circuit 211 of the operation module, and the electrical interconnection between the circuit 311 of the memory module and the circuit 111 of the control module are made by bonding, therefore, the data can be directly transmitted among the circuit 211 of the operation module, the circuit 111 of the control module and the circuit 311 of the memory module, thereby increasing the speed of transmitting data, increasing the bandwidth of the semiconductor structure for maximum pooling processing, thereby increasing the operation processing speed of the chip for maximum pooling, improving the performance of the chip for maximum pooling, the operation time of the chip for the maximum pooling processing is reduced, and the power consumption of the chip for the maximum pooling processing is reduced; on the other hand, since the first substrate 100 is bonded to the second substrate 200, the third substrate 300 is bonded to the first substrate 100 or the second substrate 200, and the control region a, the operation region B, and the memory region C overlap, the area of the semiconductor structure for maximum pooling is reduced with a simple structure, thereby improving the integration of the chip for maximum pooling.

In this embodiment, the third substrate 300 is bonded to the first substrate 100, and the fifth surface 301 faces the second surface 102.

Since the control area a further includes a plurality of memory addressing modules 150 arranged parallel to the first surface 101, and the circuit 151 of each memory addressing module is electrically interconnected with the circuit 111 of one control module, the control module 110 can address through the memory addressing modules 150 more quickly, thereby increasing the operation speed of the chip for maximum pooling.

In this embodiment, each operation area B includes an operation module 210.

In this embodiment, the circuit 211 of the operation module 210 further includes 1 or more operators (not shown). The arithmetic unit comprises one or more combinations of an adder, a multiplier, a divider and a comparator.

In this embodiment, the control module 110 is configured to obtain and analyze a maximum pooling instruction to obtain data to be operated, a pooling kernel and a target address; after obtaining the data to be operated, the pooled core, and the target address, the control module 110 is further configured to transmit the data to be operated, the pooled core, and the operation module 210 electrically interconnected with the circuit 111 of the control module.

The control module 110 is further configured to transmit the data to be operated and the pooled cores to a storage module 310 electrically interconnected with the circuitry of the control module 110.

The storage module 310 is configured to obtain the data to be operated and the pooled core, and store the data to be operated and the pooled core.

In this embodiment, the second substrate further includes a second metal interconnection layer 220, the second metal interconnection layer 220 is electrically interconnected with the circuit 211 of the operation module 210, the third surface 203 exposes a surface of the second metal interconnection layer 220, and the first metal interconnection layer 120 and the second metal interconnection layer 220 are bonded to each other in the control area a and the operation area B that overlap each other.

In this embodiment, the third substrate 300 further includes a fifth metal interconnection layer 320, the fifth metal interconnection layer 320 is electrically interconnected with the circuit 311 of the memory module, the fifth surface 301 exposes the surface of the fifth metal interconnection layer 320, and the third metal interconnection layer 130 and the fifth metal interconnection layer 320 are bonded to each other in the control area a, the operation area B and the storage area C which overlap with each other.

Since the control module 110 has a first projection on the first surface 101, the operation module 210 has a second projection on the first surface 101, the memory module 310 has a third projection on the first surface 101, and the second projection of the operation module 210 and the third projection of the memory module 310, which form an electrical interconnection between circuits, are all within the range of the first projection of the control module 110, on one hand, mutual bonding between the control area a, the memory area C, and the operation area B is facilitated, and on the other hand, the area occupied by the memory module 310, the control module 110, and the operation module 210 in common is reduced, thereby reducing the area of the semiconductor structure for maximum pooling processing with a simple structure, and improving the integration of the chip for maximum pooling processing.

Fig. 6 is a schematic cross-sectional structure diagram of a chip according to an embodiment of the present invention.

Correspondingly, an embodiment of the present invention further provides a chip forming method, please refer to fig. 6, including: dicing the semiconductor structure for maximum pooling to form a plurality of chips, each of the chips comprising: the device comprises a control area A, storage areas C and an operation area B, wherein each control area A is overlapped with one operation area B, and each storage area C is overlapped with one control area A and one operation area B.

Accordingly, an embodiment of the present invention further provides a chip formed based on the semiconductor structure for maximum pooling, please refer to fig. 6, including: the device comprises a control area A, storage areas C and an operation area B, wherein each control area A is overlapped with one operation area B, and each storage area C is overlapped with one control area A and one operation area B.

The control area a comprises a plurality of control modules 110 arranged parallel to the first face 101; each of the control areas a overlaps one of the operation areas B, the operation area B includes a plurality of operation modules 210 arranged parallel to the third face 203, and in the control area a and the operation area B overlapping each other, the circuits 111 of the control modules and the circuits 211 of the operation modules are electrically interconnected.

Each of the storage areas C overlaps one of the control area a and one of the operation area B, the storage area C includes a plurality of storage modules 310 arranged parallel to the fifth surface 301, in the mutually overlapping storage area C, control area a and operation area B, the circuits 311 of the storage modules are electrically interconnected with the circuits 211 of the operation module, and the circuits 311 of the storage modules are electrically interconnected with the circuits 111 of the control module.

Fig. 7 is a schematic structural view of a device for maximum pooling treatment according to an embodiment of the present invention.

Accordingly, an embodiment of the present invention further provides a device for maximum pooling, please refer to fig. 7 on the basis of fig. 6, where the device 700 for maximum pooling includes: the above chip (as shown in fig. 6); an interface device 710, where the interface device 710 is used to implement data transmission between the chip and an external device, and the interface device 710 is connected to the chip.

In this embodiment, the apparatus 700 for maximum pooling further comprises: a control device 720, wherein the control device 720 is used for monitoring the state of the chip, and the control device 720 is connected with the chip; a memory device 730, the memory device 730 being used to store data in the chip, the memory device 730 being connected to the chip.

Fig. 8 to 11 are schematic cross-sectional views of the semiconductor structure for maximum pooling according to another embodiment of the present invention.

Referring to fig. 8, a first substrate 400 is provided, the first substrate 400 has a first side 401 and a second side 402 opposite to each other, the first substrate 400 includes a plurality of control areas a, the control areas a include a plurality of control modules 410 arranged parallel to the first side 401, and the control modules 410 have circuits 411 of the control modules therein.

The material of the first substrate 400 includes a semiconductor material.

In this embodiment, the material of the first substrate 400 includes silicon.

In this embodiment, the first substrate 400 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the control module 410 is configured to obtain and analyze a maximum pooling instruction to obtain data to be operated, a pooling core, and a target address; after acquiring the data to be operated, the pooled core and the target address, the control module 410 is further configured to transmit the data to be operated and the pooled core to a subsequent operation module electrically interconnected with the circuit 411 of the control module 410. The control module is also configured to transmit the data to be computed and the pooled cores to a storage module that is subsequently electrically interconnected with the control module 410.

In this embodiment, each of the control areas a includes a control module 410.

In this embodiment, the first substrate 400 further includes a first metal interconnection layer 420, the first metal interconnection layer 420 is electrically interconnected with the circuit 411 of the control module 410, and the first surface 401 exposes a surface of the first metal interconnection layer 420.

In this embodiment, the control area a further includes a plurality of memory addressing modules 450 arranged parallel to the first surface 401, the memory addressing modules 450 have memory addressing module circuits 451 therein, and each memory addressing module circuit 451 is electrically interconnected with one of the control module circuits 411.

Specifically, in the present embodiment, each of the control areas a includes a memory addressing module 450.

In this embodiment, the first substrate 400 further includes a first dielectric layer (not shown) surrounding the circuit 411 of the control module, the circuit 451 of the memory addressing module, and the first metal interconnection layer 420.

Referring to fig. 9, a second substrate 500 is provided, the second substrate 500 has a third surface 503 and a fourth surface 504 which are opposite to each other, the second substrate 500 includes a plurality of operation regions B, the operation regions B include a plurality of operation modules 510 arranged parallel to the third surface 503, and the operation modules 510 have circuits 511 of the operation modules therein.

The material of the second substrate 500 includes a semiconductor material.

In this embodiment, the material of the second substrate 500 includes silicon.

In this embodiment, the second substrate 500 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In the present embodiment, the circuit 511 of the operation module 510 includes more than 1 comparator (not shown).

In this embodiment, the circuit 511 of the operation module 510 further includes 1 or more operators (not shown).

The operation module 510 is configured to obtain the data to be operated and the pooling core, perform maximum pooling operation on the data to be operated according to the pooling core to obtain an operation result, and store the operation result in the target address.

In this embodiment, each operation area B includes an operation module 510.

In this embodiment, the second substrate 500 further includes a second metal interconnection layer 520, the second metal interconnection layer 520 is electrically interconnected with the circuit 511 of the operation module 510, and the third surface 503 exposes the surface of the second metal interconnection layer 520.

In this embodiment, the second substrate 500 further includes a fourth metal interconnection layer 530, the fourth metal interconnection layer 530 is electrically interconnected with the circuit 511 of the operation module 510, and the fourth surface 504 exposes a surface of the fourth metal interconnection layer 530.

In this embodiment, the second substrate 500 further includes a second dielectric layer (not shown) surrounding the second metal interconnection layer 520, the fourth metal interconnection layer 530 and the circuit 511 of the operation module 510.

Referring to fig. 10, a third substrate 600 is provided, where the third substrate 600 has a fifth surface 601, the third substrate 600 includes a plurality of memory areas C, the memory areas C include a plurality of memory modules 610 arranged parallel to the fifth surface 601, and the memory modules 610 have circuits 611 of the memory modules therein.

The material of the third substrate 600 includes a semiconductor material.

In this embodiment, the material of the third substrate 600 includes silicon.

In this embodiment, the third substrate 600 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit 611 of the storage module includes one or both of a buffer and a register. The buffer includes one or both of a cache buffer and a neuron buffer.

In this embodiment, the storage module 610 is configured to obtain the data to be operated and the pooled core, and store the data to be operated and the pooled core.

In this embodiment, each of the memory areas C includes a memory module 610 therein.

In this embodiment, the third substrate 600 further includes a fifth metal interconnection layer 620, the fifth metal interconnection layer 620 is electrically interconnected with the circuit 611 of the memory module, and the fifth surface 601 exposes the surface of the fifth metal interconnection layer 620.

In this embodiment, a third dielectric layer (not labeled) surrounding the fifth metal interconnection layer 620 and the circuit 611 of the memory module is further included in the third substrate 600.

Referring to fig. 11, the first substrate 400 is bonded to the second substrate 500, the first surface 401 faces the third surface 503, each of the control areas a overlaps one of the operation areas B, and the circuits 411 of the control module and the circuits 511 of the operation module are electrically interconnected in the control areas a and the operation areas B that overlap each other; and, the second substrate 500 and the third substrate 600 are bonded, the fifth surface 601 faces the fourth surface 504, each of the memory areas C overlaps one of the control areas a and one of the operation areas B, and in the memory area C, the control area a, and the operation area B overlapping each other, the circuits 611 of the memory module and the circuits 511 of the operation module are electrically interconnected, and the circuits 611 of the memory module and the circuits 411 of the control module are electrically interconnected.

Specifically, in the control area a, the operation area B, and the memory area C, which overlap each other, the first metal interconnection layer 420 and the second metal interconnection layer 520 are bonded to each other, and the fourth metal interconnection layer 530 and the fifth metal interconnection layer 620 are bonded to each other.

In the present embodiment, in the control area a and the operation area B overlapping each other, the circuit 411 of each of the control modules is electrically interconnected with the circuit 511 of one operation module.

In the present embodiment, in the storage area C, the control area a, and the operation area B overlapping each other, the circuit 411 of each control module and the circuit 611 of 1 memory module are electrically interconnected, and the circuit 611 of the memory module electrically interconnected with the circuit 411 of the control module is also electrically interconnected with the circuit 511 of the operation module, and the circuit 511 of the operation module is electrically interconnected with the circuit 411 of the control module.

In this embodiment, the control module 410 has a first projection (not shown) on the first surface 401, the computing module 510 has a second projection (not shown) on the first surface 401, the memory module 610 has a third projection (not shown) on the first surface 401, and in the memory area C, the control area a, and the operation area B that overlap each other, the second projection of the computing module 510 and the third projection of the memory module 610, which are electrically interconnected among circuits, are within the range of the first projection of the control module 410.

Fig. 12 is a schematic structural diagram of a semiconductor structure for maximum pooling according to another embodiment of the present invention.

Accordingly, the present invention also provides a semiconductor structure for maximum pooling formed by the above-mentioned forming method, please refer to fig. 12 on the basis of fig. 11, fig. 11 is a schematic cross-sectional view taken along the direction X-X1 in fig. 12, which includes: a first substrate 400, said first substrate 400 having opposing first and

second sides

401, 402, said first substrate 400 comprising a plurality of control zones a, said control zones a comprising a plurality of control modules 410 arranged parallel to said first side 401; a second substrate 500 bonded to the first substrate 400, the second substrate 500 having a third surface 503 and a fourth surface 504 opposite to each other, the first surface 401 facing the third surface 503, the second substrate 500 including a plurality of operation regions B, each of the control regions a overlapping with one of the operation regions B, the operation region B including a plurality of operation modules 510 arranged parallel to the third surface 503, in the control region a and the operation region B overlapping with each other, circuits 411 of the control modules and circuits 511 of the operation modules being electrically interconnected.

The semiconductor structure for maximum pooling further includes a third substrate 600 bonded to the first substrate 400 or the second substrate 500, the third substrate 600 having a fifth surface 601, the third substrate 600 including a plurality of storage areas C, each of the storage areas C overlapping one of the control areas a and one of the operation areas B, the storage area C including a plurality of memory modules 610 arranged in parallel to the fifth surface 601, the circuits 611 of the memory modules and the circuits 511 of the operation modules being electrically interconnected in the storage areas C, the control areas a and the operation areas B overlapping each other, and the circuits 611 of the memory modules and the circuits 411 of the control modules being electrically interconnected.

On the one hand, in the memory area C, the control area A and the operation area B which overlap each other, the electrical interconnection between the circuit 411 of the control module and the circuit 511 of the operation module, the electrical interconnection between the circuit 611 of the memory module and the circuit 511 of the operation module, and the electrical interconnection between the circuit 611 of the memory module and the circuit 411 of the control module are made by bonding, therefore, between the circuit 511 of the operation module, the circuit 411 of the control module and the circuit 611 of the memory module, data can be directly transferred, thereby increasing the speed of transmitting data, increasing the bandwidth of the semiconductor structure for maximum pooling processing, thereby increasing the operation processing speed of the chip for maximum pooling, improving the performance of the chip for maximum pooling, the operation time of the chip for the maximum pooling processing is reduced, and the power consumption of the chip for the maximum pooling processing is reduced; on the other hand, since the first substrate 400 is bonded to the second substrate 500, the third substrate 600 is bonded to the first substrate 400 or the second substrate 500, and the control region a, the operation region B, and the memory region C overlap, the area of the semiconductor structure for maximum pooling is reduced with a simple structure, thereby improving the integration of the chip for maximum pooling.

In this embodiment, the third substrate 600 is bonded to the second substrate 500, and the fifth surface 601 faces the fourth surface 504.

In this embodiment, each of the control areas a includes a control module 410.

In this embodiment, each operation area B includes an operation module 510.

In this embodiment, the circuit 511 of the operation module 510 further includes 1 or more operators (not shown). The arithmetic unit comprises one or more combinations of an adder, a multiplier, a divider and a comparator.

In this embodiment, the control module 410 is configured to obtain and analyze a maximum pooling instruction to obtain data to be operated, a pooling core, and a target address; after obtaining the data to be operated, the pooled core, and the target address, the control module 410 is further configured to transmit the data to be operated, the pooled core, and the operation module 510 electrically interconnected with the circuit 411 of the control module.

The control module 410 is also configured to transmit the data to be computed and the pooled cores to a storage module 610 electrically interconnected with the circuitry of the control module 410.

The storage module 610 is configured to obtain the data to be operated and the pooled core, and store the data to be operated and the pooled core.

In this embodiment, the second substrate 500 further includes a second metal interconnection layer 520, the second metal interconnection layer 520 is electrically interconnected with the circuit 511 of the operation module 510, the third surface 503 exposes the surface of the second metal interconnection layer 520, and the first metal interconnection layer 420 and the second metal interconnection layer 520 are bonded to each other in the control area a and the operation area B that overlap each other.

In this embodiment, the third substrate 600 further includes a fifth metal interconnection layer 620, the fifth metal interconnection layer 620 is electrically interconnected with the circuit 611 of the memory module, the fifth surface 601 exposes the surface of the fifth metal interconnection layer 620, and the fourth metal interconnection layer 530 and the fifth metal interconnection layer 620 are bonded to each other in the control area a, the operation area B and the storage area C which overlap with each other.

Since the control module 410 has a first projection on the first surface 401, the operation module 510 has a second projection on the first surface 401, the memory module 610 has a third projection on the first surface 401, and the second projection of the operation module 510 and the third projection of the memory module 610, which form an electrical interconnection between circuits, are all within the range of the first projection of the control module 410, on one hand, mutual bonding between the control area a, the memory area C, and the operation area B is facilitated, and on the other hand, the area occupied by the memory module 610, the control module 410, and the operation module 510 together is reduced, thereby realizing a reduction in the area of the semiconductor structure for maximum pooling processing with a simple structure, and improving the integration of the chip for maximum pooling processing.

Fig. 13 is a schematic cross-sectional view of a chip according to another embodiment of the present invention.

Accordingly, another embodiment of the present invention further provides a method for forming a chip, please refer to fig. 6, which includes: dicing the semiconductor structure for maximum pooling to form a plurality of chips, each of the chips comprising: the device comprises a control area A, storage areas C and an operation area B, wherein each control area A is overlapped with one operation area B, and each storage area C is overlapped with one control area A and one operation area B.

Accordingly, another embodiment of the present invention further provides a chip formed on the semiconductor structure for maximum pooling, referring to fig. 13, including: the device comprises a control area A, storage areas C and an operation area B, wherein each control area A is overlapped with one operation area B, and each storage area C is overlapped with one control area A and one operation area B.

The control area a comprises a plurality of control modules 410 arranged parallel to the first face 401; each of the control areas a overlaps one of the calculation areas B, the calculation area B includes a plurality of calculation modules 510 arranged parallel to the third face 503, and in the control area a and the calculation area B overlapping each other, the circuits 411 of the control modules and the circuits 511 of the calculation modules are electrically interconnected.

Each of the storage areas C overlaps one of the control area a and one of the operation area B, the storage area C includes a plurality of storage modules 610 arranged parallel to the fifth surface 601, in the storage area C, the control area a, and the operation area B overlapping each other, the circuits 611 of the storage modules and the circuits 511 of the operation modules are electrically interconnected, and the circuits 611 of the storage modules and the circuits 411 of the control modules are electrically interconnected.

Accordingly, another embodiment of the present invention further provides a device for maximum pooling, please refer to fig. 14 on the basis of fig. 13, wherein the device 800 for maximum pooling comprises: the above chip (as shown in fig. 13); an interface device 810, where the interface device 810 is used to implement data transmission between the chip and an external device, and the interface device 810 is connected to the chip.

In this embodiment, the apparatus 800 for maximum pooling further comprises: a control device 820, wherein the control device 820 is used for monitoring the state of the chip, and the control device 820 is connected with the chip; a memory device 830, the memory device 830 for storing data in the chip, the memory device 830 being connected to the chip.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A semiconductor structure for maximum pooling processing, comprising:

the first substrate is provided with a first face and a second face which are opposite, the first substrate comprises a plurality of control areas, and the control areas comprise a plurality of control modules which are arranged in parallel to the first face;

a second substrate bonded to the first substrate, the second substrate having a third surface and a fourth surface opposite to each other, the first surface facing the third surface, the second substrate including a plurality of operation regions, each of the control regions overlapping with one of the operation regions, the operation regions including a plurality of operation modules arranged in parallel to the third surface, the circuits of the control modules and the circuits of the operation modules being electrically interconnected in the control regions and the operation regions overlapping with each other;

a third substrate bonded to the first substrate or the second substrate, the third substrate having a fifth surface facing the second surface if the third substrate is bonded to the first substrate, the fifth surface facing the fourth surface if the third substrate is bonded to the second substrate, the third substrate including a plurality of storage areas, each of the storage areas overlapping one of the control area and one of the operation area, the storage areas including a plurality of memory modules arranged in parallel to the fifth surface, in the mutually overlapping storage area, control area and operation area, circuits of the memory modules being electrically interconnected to circuits of the operation module, and circuits of the memory modules being electrically interconnected to circuits of the control module.

2. The semiconductor structure for maximum pooling of processing of claim 1 wherein the circuits of each of said control modules are electrically interconnected to the circuits of more than one operational module in the control area and operational area that overlap each other.

3. The semiconductor structure for maximum pooling processing of claim 1 or 2, wherein in the storage area, the control area and the operation area overlapped with each other, the circuit of each control block and the circuit of 1 or more memory blocks are electrically interconnected, and the circuit of the memory block electrically interconnected with the circuit of the control block is further electrically interconnected with the circuit of the operation block and the circuit of the operation block is electrically interconnected with the circuit of the control block.

4. The semiconductor structure for maximum pooling of claim 1 wherein said computing module circuit includes more than 1 comparator.

5. The semiconductor structure for maximum pooling of processing of claim 4 wherein said computing module circuit further includes more than 1 operator.

6. The semiconductor structure for maximum pooling of claim 5 wherein said operator comprises a combination of one or more of an adder, a multiplier, a divider, and a comparator.

7. The semiconductor structure for maximum pooling of processing of claim 1 wherein said memory module circuitry includes one or both of buffers and registers.

8. The semiconductor structure for maximum pooling processing of claim 7 wherein said buffer comprises one or both of a cache buffer and a neuron buffer.

9. The semiconductor structure for maximum pooling of processing of claim 1 wherein said control area further includes a plurality of memory addressing modules arranged parallel to said first substrate surface, the circuitry of each of said memory addressing modules being electrically interconnected with the circuitry of one of said control modules.

10. The semiconductor structure for maximum pooling of processing of claim 1 wherein said control module has a first projection at said first side, said calculation module has a second projection at said first side, said memory module has a third projection at said first side, and said second projection of the calculation module and said third projection of the memory module electrically interconnected between the circuits are within the range of the first projection of the control module in the memory, control and calculation areas that overlap each other.

11. The semiconductor structure for maximum pooling of processing of claim 1 further comprising a first metal interconnect layer within said first substrate, said first metal interconnect layer being electrically interconnected to circuitry of said control module, said first side exposing a surface of said first metal interconnect layer, further comprising a second metal interconnect layer within said second substrate, said second metal interconnect layer being electrically interconnected to circuitry of said operational module, said third side exposing a surface of said second metal interconnect layer, and wherein said first metal interconnect layer and said second metal interconnect layer are bonded to each other in overlapping control and operational areas.

12. The semiconductor structure for maximum pooling of claim 11 wherein if said third substrate is bonded to said first substrate, said first substrate further comprises a third metal interconnect layer therein, said third metal interconnect layer is electrically interconnected to said control module circuitry, said second side exposes a surface of said third metal interconnect layer, said third substrate further comprises a fifth metal interconnect layer therein, said fifth metal interconnect layer is electrically interconnected to said memory module circuitry, said fifth side exposes a surface of said fifth metal interconnect layer, and said third metal interconnect layer and said fifth metal interconnect layer are bonded to each other.

13. The semiconductor structure for maximum pooling of claim 11 wherein if said third substrate is bonded to said second substrate, said second substrate further comprises a fourth metal interconnection layer therein, said fourth metal interconnection layer is electrically interconnected to said circuitry of said computing module, said fourth surface exposes a surface of said fourth metal interconnection layer, said third substrate further comprises a fifth metal interconnection layer therein, said fifth metal interconnection layer is electrically interconnected to said circuitry of said memory module, said fifth surface exposes a surface of said fifth metal interconnection layer, and said fourth metal interconnection layer and said fifth metal interconnection layer are bonded to each other.

14. A chip based on the semiconductor structure for maximum pooling according to any of claims 1 to 13, comprising:

the device comprises a control area, storage areas and an operation area, wherein each control area is overlapped with one operation area, and each storage area is overlapped with one control area and one operation area.

15. An apparatus for maximum pooling treatment comprising:

the chip of claim 14;

and the interface device is used for realizing data transmission between the chip and external equipment, and is connected with the chip.

16. The apparatus for maximum pooling of treatment of claim 15 further comprising: the control device is used for monitoring the state of the chip and is connected with the chip; a memory device for storing data in the chip, the memory device being connected to the chip.