CN211125641U - Semiconductor structure for maximum pooling, chip and apparatus for maximum pooling - Google Patents

Abstract

A semiconductor structure for maximum pooling processing, a chip and a device for maximum pooling processing, wherein the semiconductor structure for maximum pooling processing comprises: a first substrate, the first substrate includes a plurality of control regions, and the control regions include parallel a plurality of control modules arranged on the first surface; a second substrate bonded to the first substrate, the second substrate includes a plurality of operation areas, and the operation area includes a plurality of operation areas arranged parallel to the third surface a plurality of operation modules; a third substrate bonded to the first substrate or the second substrate, the third substrate includes a plurality of storage areas, and the storage area includes a plurality of storage areas arranged parallel to the fifth surface storage module. The semiconductor structure for max-pooling processing can improve the performance of a chip for max-pooling processing.

Description

Semiconductor structures, chips and devices for max-pooling processing

technical field

The utility model relates to the field of semiconductors, in particular to a semiconductor structure, a chip and a device for maximum pooling treatment.

Background technique

Today, the application of artificial intelligence is appearing in more and more fields, such as autonomous driving, image recognition, medical diagnosis, games, financial data analysis and search engines, etc., especially the use of neural network algorithms is becoming more and more extensive. It has been well used in image recognition, speech recognition, natural language processing and other fields. However, due to the increasing complexity of the neural network algorithm, the types and quantities of data operations involved continue to increase, which puts forward higher requirements for the performance of the chip.

However, in the existing chip, the circuits of various functional modules are formed on the same wafer, so not only is the data transmission between the functional modules limited by the bandwidth, the data transmission speed of the chip is reduced, and the operation of the chip is reduced. In addition, the circuit of each functional module occupies a large area, so the integration degree of the chip is low. Therefore, the performance of the existing chip still needs to be improved.

Utility model content

The technical problem solved by the present invention is to provide a semiconductor structure, a chip and a device for maximum pooling processing, so as to improve the performance of the chip used for maximum pooling processing.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure for maximum pooling treatment, comprising: a first substrate, the first substrate has an opposite first surface and a second surface, the first substrate Including a plurality of control areas, the control area includes a plurality of control modules arranged parallel to the first surface; a second substrate bonded with the first substrate, the second substrate has an opposite third surface and a first surface Four sides, the first side faces the third side, the second substrate includes a plurality of operation areas, each of the control areas overlaps with one of the operation areas, and the operation area includes parallel to the third side A plurality of operation modules are arranged on the surface, in the overlapping control area and operation area, the circuit of the control module and the circuit of the operation module are electrically interconnected; with the first substrate or the second substrate A bonded third substrate, the third substrate has a fifth surface, if the third substrate is bonded to the first substrate, the fifth surface faces the second surface, if the third substrate Bonded with the second substrate, the fifth surface faces the fourth surface, the third substrate includes a plurality of storage areas, each of the storage areas overlaps with one of the control areas and one of the operation areas , the storage area includes a plurality of storage modules arranged parallel to the fifth surface, and in the overlapping storage area, control area and operation area, the circuit of the storage module and the circuit of the operation module are electrically connected to each other. interconnection, the circuit of the storage module and the circuit of the control module are electrically interconnected.

Optionally, in the overlapping control area and operation area, the circuit of each control module is electrically interconnected with the circuit of more than one operation module.

Optionally, in the overlapping storage area, control area and operation area, the circuit of each control module is electrically interconnected with the circuit of more than one storage module, and the circuit is electrically interconnected with the circuit of the control module. The circuit of the storage module is also electrically interconnected with the circuit of the arithmetic module, and the circuit of the arithmetic module and the circuit of the control module are electrically interconnected.

Optionally, the circuit of the operation module includes more than one comparator.

Optionally, the circuit of the arithmetic module further includes more than one arithmetic unit.

Optionally, the operator includes one or a combination of an adder, a multiplier, a divider and a comparator.

Optionally, the circuit of the storage module includes one or both of a buffer and a register.

Optionally, the buffer includes one or both of a temporary buffer and a neuron buffer.

Optionally, the control module is used to obtain and parse the maximum pooling instruction to obtain the data to be calculated, the pooled core and the target address; after obtaining the data to be calculated, the pooled core and the target address, the control The module is further configured to transmit the data to be operated and the pooling core to the operation module.

Optionally, the operation module is used to obtain the data to be calculated and the pooling core, perform a maximum pooling operation on the data to be calculated according to the pooling core to obtain the operation result, and store the operation result in the the target address.

Optionally, the control module is further configured to transmit the data to be computed and the pooling core to the storage module; the storage module is configured to acquire the data to be computed, the pooled core and the storage module. the data to be operated and the pooling kernel.

Optionally, the control area further includes a plurality of memory addressing modules arranged parallel to the surface of the first substrate, and a circuit of each of the memory addressing modules is electrically interconnected with a circuit of one of the control modules.

Optionally, the control module has a first projection on the first surface, the computing module has a second projection on the first surface, the storage module has a third projection on the first surface, and In the overlapping storage area, control area and operation area, the second projection of the operation module and the third projection of the storage module which are electrically interconnected between the circuits are all within the range of the first projection of the control module.

Optionally, the first substrate further includes a first metal interconnection layer, the first metal interconnection layer is electrically interconnected with the circuit of the control module, and the first metal is exposed on the first surface the surface of the interconnection layer, the second substrate further includes a second metal interconnection layer, the second metal interconnection layer is electrically interconnected with the circuit of the operation module, the third surface exposes the second metal interconnection layer The surface of the metal interconnection layer, and in the mutually overlapping control region and the operation region, the first metal interconnection layer and the second metal interconnection layer are bonded to each other.

Optionally, if the third substrate is bonded to the first substrate, the first substrate further includes a third metal interconnection layer, and the third metal interconnection layer is electrically connected to the circuit of the control module. interconnection, the second surface exposes the surface of the third metal interconnection layer, the third substrate further includes a fifth metal interconnection layer, the fifth metal interconnection layer and the circuit of the memory module For electrical interconnection, the fifth surface exposes the surface of the fifth metal interconnection layer, and the third metal interconnection layer and the fifth metal interconnection layer are bonded to each other.

Optionally, if the third substrate is bonded to the second substrate, the second substrate further includes a fourth metal interconnection layer, and the fourth metal interconnection layer is electrically connected to the circuit of the operation module. interconnection, the fourth surface exposes the surface of the fourth metal interconnection layer, the third substrate further includes a fifth metal interconnection layer, the fifth metal interconnection layer and the circuit of the memory module For electrical interconnection, the fifth surface exposes the surface of the fifth metal interconnection layer, and the fourth metal interconnection layer and the fifth metal interconnection layer are bonded to each other.

Correspondingly, the technical solution of the present invention also provides a chip based on any one of the above-mentioned semiconductor structures for maximum pooling processing, comprising: a control area, a storage area and an operation area, and each of the control areas and one of the The operation areas overlap, and each of the storage areas overlaps with one of the control areas and one of the operation areas.

Correspondingly, the technical solution of the present invention also provides a device for maximum pooling processing, which is characterized by comprising: the above-mentioned chip; and an interface device, the interface device is used to realize data transmission between the chip and an external device , the interface device is connected to the chip.

Optionally, it further includes: a control device, which is used for monitoring the state of the chip, the control device is connected to the chip; a storage device, which is used for storing the data in the chip. data, the storage device is connected to the chip.

Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

In the semiconductor structure for maximum pooling processing according to the technical solution of the present invention, on the one hand, in the overlapping storage area, control area and operation area, the circuit of the control module and the circuit of the operation module are connected by bonding. The electrical interconnection between, the electrical interconnection between the circuit of the storage module and the circuit of the arithmetic module, and the electrical interconnection between the circuit of the storage module and the circuit of the control module, therefore, the circuit of the arithmetic module , Between the circuit of the control module and the circuit of the storage module, data can be directly transmitted, thereby improving the speed of data transmission, increasing the bandwidth of the semiconductor structure for maximum pooling processing, and thus improving the maximum pooling processing chip. The operation processing speed improves the performance of the chip used for max pooling processing, reduces the operation time of the chip used for max pooling processing, and reduces the power consumption of the chip used for max pooling processing; on the other hand, Since the first substrate is bonded to the second substrate, the third substrate is bonded to the first substrate or the second substrate, and the control area, the operation area, and the storage area are overlapped, so simple The structure reduces the area of the semiconductor structure for max-pooling processing, thereby improving the integration degree of the chip for max-pooling processing.

Further, since the control area further includes a plurality of memory addressing modules arranged parallel to the first surface, and the circuit of each of the memory addressing modules is electrically interconnected with the circuit of one of the control modules, therefore, the The control module can be addressed faster through the circuit of the memory addressing module, thereby improving the operation speed of the chip used for maximum pooling processing.

Further, since the control module has a first projection on the first surface, the computing module has a second projection on the first surface, the storage module has a third projection on the first surface, and, The second projection of the arithmetic module and the third projection of the storage module that form electrical interconnection between the circuits are all within the range of the first projection of the control module. Therefore, on the one hand, it is beneficial to the control area, the storage area and the operation area. On the other hand, the area occupied by the storage module, the control module and the operation module is reduced, so that the area of the semiconductor structure for maximum pooling processing can be reduced with a simple structure, and the use of The level of integration of the chip for max pooling.

Description of drawings

1 to 4 are schematic cross-sectional structural diagrams of each forming step of the semiconductor structure for maximum pooling processing according to an embodiment of the present invention;

5 is a schematic structural diagram of a semiconductor structure for maximum pooling processing according to an embodiment of the present invention;

6 is a schematic cross-sectional structure diagram of a chip according to an embodiment of the present invention;

7 is a schematic structural diagram of a device for maximum pooling processing according to an embodiment of the present invention;

8 to 11 are schematic cross-sectional structural views of each forming step of the semiconductor structure for maximum pooling processing according to another embodiment of the present invention;

12 is a schematic structural diagram of a semiconductor structure for maximum pooling processing according to another embodiment of the present invention;

13 is a schematic cross-sectional structure diagram of a chip according to another embodiment of the present invention;

14 is a schematic structural diagram of a device for maximum pooling processing according to another embodiment of the present invention.

Detailed ways

As described in the background art, in the existing chip, the circuits of various functional modules are formed on the same wafer. Therefore, not only the data transmission between the functional modules is limited by the bandwidth, the data transmission speed of the chip is reduced, As a result, the operation speed of the chip is reduced, and the circuits of each functional module occupy a large area, so that the integration degree of the chip is low. Therefore, the performance of the existing chip still needs to be improved.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure for maximum pooling processing, comprising: a first substrate, the first substrate has an opposite first surface and a second surface, the first substrate The substrate includes a plurality of control areas, and the control area includes a plurality of control modules arranged parallel to the first surface; a second substrate bonded to the first substrate, the second substrate has an opposite third surface and The fourth surface, the first surface faces the third surface, the second substrate includes a plurality of operation areas, each of the control areas overlaps with one of the operation areas, and the operation area includes parallel to the first surface. A number of operation modules arranged on three sides, in the overlapping control area and operation area, the circuit of the control module and the circuit of the operation module are electrically interconnected; and the first substrate or the second The third substrate is bonded to the substrate, and the third substrate has a fifth surface. If the third substrate is bonded to the first substrate, the fifth surface faces the second surface. If the third substrate is bonded to the first substrate, the fifth surface faces the second surface. The substrate is bonded to the second substrate, the fifth surface faces the fourth surface, and the third substrate includes a plurality of storage areas, each of the storage areas is associated with one of the control areas and one of the operation areas overlapping, the storage area includes a plurality of storage modules arranged parallel to the fifth surface, and in the overlapping storage area, control area and operation area, between the circuit of the storage module and the circuit of the operation module Electrical interconnection between the circuits of the storage module and the circuits of the control module. Thus, the semiconductor structure for max-pooling can improve the performance of a chip for max-pooling.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 4 are schematic cross-sectional structural diagrams of each forming step of a semiconductor structure for maximum pooling processing according to an embodiment of the present invention.

Referring to FIG. 1, a first substrate 100 is provided, the first substrate 100 has a first surface 101 and a second surface 102 opposite to each other, the first substrate 100 includes a plurality of control areas A, the control areas A include parallel Several control modules 110 are arranged on the first surface 101 , and the control modules 110 have circuits 111 of the control modules.

The material of the first substrate 100 includes semiconductor material.

In this embodiment, the material of the first substrate 100 includes silicon.

In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the first substrate 100 has a device layer (not shown) therein. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the control module 110 is used to obtain and parse the maximum pooling instruction to obtain the data to be calculated, the pooled core and the target address; after obtaining the data to be calculated, the pooled core and the target address, The control module 110 is further configured to transmit the to-be-operated data and the pooled core to a subsequent operation module that is electrically interconnected with the circuit 111 of the control module 110 . The control module is further configured to transmit the to-be-operated data and the pooled core to a subsequent storage module electrically interconnected with the control module 110 .

In this embodiment, each of the control areas A includes one control module 110 .

In other embodiments, each control area includes two or more control modules.

In this embodiment, the first substrate 100 further includes a first metal interconnection layer 120, the first metal interconnection layer 120 is electrically interconnected with the circuit 111 of the control module 110, and the first surface 101 exposes the surface of the first metal interconnection layer 120 .

In this embodiment, the first substrate 100 further includes a third metal interconnection layer 130, the third metal interconnection layer 130 is electrically interconnected with the circuit 111 of the control module 110, and the second surface 102 exposes the surface of the third metal interconnection layer 130 .

In another embodiment, the first substrate does not include a third metal interconnect layer.

In this embodiment, the control area A further includes a plurality of memory addressing modules 150 arranged parallel to the first surface 101 , and the memory addressing modules 150 have circuits 151 of memory addressing modules in the memory addressing module 150 . The circuits 151 of the memory addressing module are electrically interconnected with the circuits 111 of one of the control modules.

Specifically, in this embodiment, each of the control areas A includes a memory addressing module 150 .

In another embodiment, each control area includes two or more memory addressing modules.

In other embodiments, the control area does not include a memory addressing module.

In this embodiment, the first substrate 100 further includes the circuit 111 surrounding the control module, the circuit 151 of the memory addressing module, the first metal interconnection layer 120 and the third metal interconnection The first dielectric layer (not shown) of the connecting layer 130 .

Referring to FIG. 2, a second substrate 200 is provided, the second substrate 200 has a third surface 203 and a fourth surface 204 opposite to each other, the second substrate 200 includes a plurality of operation areas B, and the operation areas B include parallel A plurality of operation modules 210 are arranged on the third surface 203 , and the operation modules 210 have circuits 211 of the operation modules.

The material of the second substrate 200 includes semiconductor material.

In this embodiment, the material of the second substrate 200 includes silicon.

In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the second substrate 200 has a device layer (not shown) therein. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit 211 of the operation module 210 includes more than one comparator (not shown).

In this embodiment, the circuit 211 of the arithmetic module 210 further includes one or more arithmetic units (not shown).

In this embodiment, the operator includes a combination of one or more of an adder, a multiplier, a divider and a comparator.

The operation module 210 is configured to obtain the data to be calculated and the pooling core, perform a maximum pooling operation on the data to be calculated according to the pooling core to obtain an operation result, and store the operation result in the target. address.

In this embodiment, each of the operation regions B includes one operation module 210 .

In other embodiments, each of the operation regions includes two or more operation modules.

In this embodiment, the second substrate further includes a second metal interconnection layer 220, the second metal interconnection layer 220 is electrically interconnected with the circuit 211 of the operation module 210, and the third surface 203 The surface of the second metal interconnection layer 220 is exposed.

In this embodiment, the second substrate 200 further includes a second dielectric layer (not marked in the figure) surrounding the second metal interconnection layer 220 and the circuit 211 of the operation module 210 .

Referring to FIG. 3 , a third substrate 300 is provided, the third substrate has a fifth surface 301 , the third substrate 300 includes a plurality of storage areas C, and the storage areas C are arranged parallel to the fifth surface 301 There are several storage modules 310 in the storage module 310, and the storage module 310 has a circuit 311 of the storage module.

The material of the third substrate 300 includes semiconductor material.

In this embodiment, the material of the third substrate 300 includes silicon.

In other embodiments, the material of the third substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the third substrate 300 has a device layer (not shown) therein. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit 311 of the storage module includes one or both of a buffer and a register. The buffer includes one or both of a temporary buffer and a neuron buffer.

In this embodiment, the storage module 310 is configured to acquire the data to be calculated and the pooling core and store the data to be calculated and the pooling core.

In this embodiment, each of the storage areas C includes one storage module 310 .

In other embodiments, each of the storage areas includes two or more storage modules.

In this embodiment, the third substrate 300 further includes a fifth metal interconnection layer 320, the fifth metal interconnection layer 320 is electrically interconnected with the circuit 311 of the memory module, and the fifth surface 301 The surface of the fifth metal interconnection layer 320 is exposed.

In this embodiment, the third substrate 300 further includes a third dielectric layer (not marked in the figure) surrounding the fifth metal interconnection layer 320 and the circuit 311 of the memory module.

Referring to FIG. 4 , the first substrate 100 is bonded to the second substrate 200 , the first surface 101 faces the third surface 203 , each of the control areas A and one of the operation areas B Overlapping, in the overlapping control area A and operation area B, the circuit 111 of the control module and the circuit 211 of the operation module are electrically interconnected; and, the first substrate 100 and the third The substrate 300 is bonded, the fifth surface 301 faces the second surface 102, each of the storage areas C overlaps with one of the control areas A and one of the operation areas B, and the overlapping storage areas C, In the control area A and the operation area B, the circuit 311 of the storage module and the circuit 211 of the operation module are electrically interconnected, and the circuit 311 of the storage module and the circuit 111 of the control module are electrically interconnected .

Specifically, in the overlapping control region A, operation region B and storage region C, the first metal interconnection layer 120 and the second metal interconnection layer 220 are bonded to each other, and the third metal interconnection layer is bonded to each other. The connection layer 130 and the fifth metal interconnection layer 320 are bonded to each other.

In this embodiment, in the mutually overlapping control area A and operation area B, the circuit 111 of each of the control modules is electrically interconnected with the circuit 211 of one operation module.

In another embodiment, the circuits of each of the control modules are electrically interconnected with the circuits of 2 or more arithmetic modules in the overlapping control and arithmetic regions.

In this embodiment, in the overlapping storage area C, control area A and operation area B, the circuit 111 of each control module and the circuit 311 of one storage module are electrically interconnected, and the circuit 111 of each control module is electrically interconnected with the circuit 311 of the control module. The circuit 311 of the storage module to which the circuit 111 is electrically interconnected is also electrically interconnected with the circuit 211 of the arithmetic module, and the circuit 211 of the arithmetic module and the circuit 111 of the control module are electrically interconnected.

In another embodiment, in the overlapping storage area, control area and operation area, the circuit of each control module is electrically interconnected with the circuit of 2 or more storage modules, and is electrically interconnected with the control module The circuit of the storage module is also electrically interconnected with the circuit of the arithmetic module, and the circuit of the arithmetic module and the circuit of the control module are electrically interconnected.

In this embodiment, the control module 110 has a first projection (not shown) on the first surface 101 , and the calculation module 210 has a second projection (not shown) on the first surface 101 , The storage module 310 has a third projection (not shown) on the first surface 101. In the overlapping storage area C, the control area A and the operation area B, the circuits of the calculation module 210 are electrically interconnected. The second projection and the third projection of the storage module 310 are both within the range of the first projection of the control module 110 .

5 is a schematic structural diagram of a semiconductor structure for maximum pooling processing according to an embodiment of the present invention.

Correspondingly, the present invention also provides a semiconductor structure for maximum pooling processing formed by the above-mentioned forming method. Please refer to FIG. 5 on the basis of FIG. 4 . FIG. 4 is a schematic cross-sectional structure diagram of FIG. It includes: a first substrate 100, the first substrate 100 has a first surface 101 and a second surface 102 opposite to each other, the first substrate 100 includes a plurality of control areas A, the control areas A include parallel to the first surface A plurality of control modules 110 arranged on the surface 101; a second substrate 200 bonded to the first substrate 100, the second substrate 200 has an opposite third surface 203 and a fourth surface 204, the first surface 101 Facing the third surface 203 , the second substrate 200 includes a plurality of operation areas B, each of the control areas A overlaps with one of the operation areas B, and the operation area B includes parallel to the third surface 203 A plurality of operation modules 210 are arranged, in the mutually overlapping control area A and operation area B, the circuit 111 of the control module and the circuit 211 of the operation module are electrically interconnected.

The semiconductor structure for max-pooling processing further includes a third substrate 300 bonded to the first substrate 100 or the second substrate 200, the third substrate 300 has a fifth surface 301, and the third substrate 300 includes several storage areas C, each of the storage areas C overlaps with one of the control areas A and one of the operation areas B, and the storage area C includes several storage modules arranged parallel to the fifth surface 301 310. In the overlapping storage area C, control area A and operation area B, the circuit 311 of the storage module and the circuit 211 of the operation module are electrically interconnected, and the circuit 311 of the storage module is connected to the circuit 311 of the storage module. The circuits 111 of the control modules are electrically interconnected.

On the one hand, in the overlapping storage area C, control area A and operation area B, the circuit 111 of the control module and the circuit 211 of the operation module are electrically interconnected by bonding, and the circuit 211 of the storage module is electrically interconnected. The electrical interconnection between the circuit 311 and the circuit 211 of the arithmetic module, and the electrical interconnection between the circuit 311 of the storage module and the circuit 111 of the control module, therefore, the circuit 211 of the arithmetic module and the circuit of the control module Between 111 and the circuit 311 of the storage module, data can be directly transmitted, thereby improving the speed of data transmission, increasing the bandwidth of the semiconductor structure for maximum pooling processing, and further improving the computing processing speed of the chip used for maximum pooling processing. , the performance of the chip used for max pooling is improved, the operation time of the chip used for max pooling is reduced, and the power consumption of the chip used for max pooling is reduced; on the other hand, due to the The first substrate 100 is bonded to the second substrate 200 , the third substrate 300 is bonded to the first substrate 100 or the second substrate 200 , and the control area A, the operation area B and the storage area C overlapping, thereby reducing the area of the semiconductor structure for max-pooling processing with a simple structure, thereby improving the integration degree of the chip for max-pooling processing.

In this embodiment, the third substrate 300 is bonded to the first substrate 100 , and the fifth surface 301 faces the second surface 102 .

In this embodiment, in the mutually overlapping control area A and operation area B, the circuit 111 of each of the control modules is electrically interconnected with the circuit 211 of one operation module.

In another embodiment, the circuits of each of the control modules are electrically interconnected with the circuits of 2 or more arithmetic modules in the overlapping control and arithmetic regions.

In this embodiment, in the overlapping storage area C, control area A and operation area B, the circuit 111 of each control module and the circuit 311 of one storage module are electrically interconnected, and the circuit 111 of each control module is electrically interconnected with the circuit 311 of the control module. The circuit 311 of the storage module to which the circuit 111 is electrically interconnected is also electrically interconnected with the circuit 211 of the arithmetic module, and the circuit 211 of the arithmetic module and the circuit 111 of the control module are electrically interconnected.

In another embodiment, in the overlapping storage area, control area and operation area, the circuit of each control module is electrically interconnected with the circuit of 2 or more storage modules, and is electrically interconnected with the control module The circuit of the storage module is also electrically interconnected with the circuit of the arithmetic module, and the circuit of the arithmetic module and the circuit of the control module are electrically interconnected.

In this embodiment, each of the control areas A includes one control module 110 .

In other embodiments, each control area includes two or more control modules.

In this embodiment, the control area A further includes a plurality of memory addressing modules 150 arranged parallel to the first surface 101 , and the memory addressing modules 150 have circuits 151 of memory addressing modules in the memory addressing module 150 . The circuits 151 of the memory addressing module are electrically interconnected with the circuits 111 of one of the control modules.

Since the control area A further includes a plurality of memory addressing modules 150 arranged parallel to the first surface 101, and the circuit 151 of each of the memory addressing modules is electrically interconnected with the circuit 111 of one of the control modules, therefore , the control module 110 can be addressed faster through the memory addressing module 150, thereby improving the operation speed of the chip used for maximum pooling processing.

Specifically, in this embodiment, each of the control areas A includes a memory addressing module 150 .

In another embodiment, each control area includes two or more memory addressing modules.

In other embodiments, the control area does not include a memory addressing module.

In this embodiment, each of the operation regions B includes one operation module 210 .

In other embodiments, each of the operation regions includes two or more operation modules.

In this embodiment, each of the storage areas C includes one storage module 310 .

In other embodiments, each of the storage areas includes two or more storage modules.

In this embodiment, the circuit 211 of the operation module 210 includes more than one comparator (not shown).

In this embodiment, the circuit 211 of the arithmetic module 210 further includes one or more arithmetic units (not shown). The operator includes a combination of one or more of an adder, a multiplier, a divider, and a comparator.

In this embodiment, the circuit 311 of the storage module includes one or both of a buffer and a register. The buffer includes one or both of a temporary buffer and a neuron buffer.

In this embodiment, the control module 110 is used to obtain and parse the maximum pooling instruction to obtain the data to be calculated, the pooled core and the target address; after obtaining the data to be calculated, the pooled core and the target address, The control module 110 is further configured to transmit the data to be calculated and the pooled core to the operation module 210 electrically interconnected with the circuit 111 of the control module.

The control module 110 is further configured to transmit the to-be-operated data and the pooled core to a storage module 310 that is electrically interconnected with the circuit of the control module 110 .

The operation module 210 is configured to obtain the data to be calculated and the pooling core, perform a maximum pooling operation on the data to be calculated according to the pooling core to obtain an operation result, and store the operation result in the target. address.

The storage module 310 is configured to acquire the data to be calculated and the pooling core and store the data to be calculated and the pooling core.

In this embodiment, the first substrate 100 further includes a first metal interconnection layer 120, the first metal interconnection layer 120 is electrically interconnected with the circuit 111 of the control module 110, and the first surface 101 exposes the surface of the first metal interconnection layer 120 .

In this embodiment, the first substrate 100 further includes a third metal interconnection layer 130, the third metal interconnection layer 130 is electrically interconnected with the circuit 111 of the control module 110, and the second surface 102 exposes the surface of the third metal interconnection layer 130 .

In another embodiment, the first substrate does not include a third metal interconnect layer.

In this embodiment, the first substrate 100 further includes the circuit 111 surrounding the control module, the circuit 151 of the memory addressing module, the first metal interconnection layer 120 and the third metal interconnection A first dielectric layer (not shown) of the connecting layer 130 .

In this embodiment, the second substrate further includes a second metal interconnection layer 220, the second metal interconnection layer 220 is electrically interconnected with the circuit 211 of the operation module 210, and the third surface 203 The surface of the second metal interconnection layer 220 is exposed, and in the overlapping control region A and the operation region B, the first metal interconnection layer 120 and the second metal interconnection layer 220 are bonded to each other .

In this embodiment, the second substrate 200 further includes a second dielectric layer (not marked in the figure) surrounding the second metal interconnection layer 220 and the circuit 211 of the operation module 210 .

In this embodiment, the third substrate 300 further includes a fifth metal interconnection layer 320, the fifth metal interconnection layer 320 is electrically interconnected with the circuit 311 of the memory module, and the fifth surface 301 The surface of the fifth metal interconnection layer 320 is exposed, and in the overlapping control region A, operation region B and storage region C, the third metal interconnection layer 130 and the fifth metal interconnection layer 320 are bonded to each other.

In this embodiment, the third substrate 300 further includes a third dielectric layer (not marked in the figure) surrounding the fifth metal interconnection layer 320 and the circuit 311 of the memory module.

In this embodiment, the control module 110 has a first projection (not shown) on the first surface 101 , and the calculation module 210 has a second projection (not shown) on the first surface 101 , The storage module 310 has a third projection (not shown) on the first surface 101. In the overlapping storage area C, the control area A and the operation area B, the circuits of the calculation module 210 are electrically interconnected. The second projection and the third projection of the storage module 310 are both within the range of the first projection of the control module 110 .

Because the control module 110 has a first projection on the first surface 101 , the computing module 210 has a second projection on the first surface 101 , and the storage module 310 has a third projection on the first surface 101 Moreover, the second projection of the computing module 210 and the third projection of the storage module 310 that form electrical interconnection between the circuits are all within the range of the first projection of the control module 110. Therefore, on the one hand, it is beneficial to the control area. A. The mutual bonding between the storage area C and the operation area B. On the other hand, the area occupied by the storage module 310, the control module 110 and the operation module 210 is reduced, thereby achieving a simple structure to reduce the maximum The area of the semiconductor structure for pooling increases the level of integration of the chip used for maximum pooling.

6 is a schematic cross-sectional structure diagram of a chip according to an embodiment of the present invention.

Correspondingly, an embodiment of the present invention also provides a method for forming a chip, please refer to FIG. 6 , which includes: cutting the above-mentioned semiconductor structure for maximum pooling treatment to form a plurality of chips, and each chip includes: a control area A, storage area C and operation area B, and each of the control areas A overlaps with one of the operation areas B, and each of the storage areas C overlaps with one of the control areas A and one of the operation areas B .

Correspondingly, an embodiment of the present invention also provides a chip formed based on the above-mentioned semiconductor structure for maximum pooling processing, please refer to FIG. 6 , including: a control area A, a storage area C and an operation area B, and each of the The control area A overlaps with one of the operation areas B, and each of the storage areas C overlaps with one of the control areas A and one of the operation areas B.

The control area A includes a plurality of control modules 110 arranged parallel to the first surface 101 ; each of the control areas A overlaps with one of the operation areas B, and the operation area B includes A plurality of operation modules 210 arranged on the surface 203, in the mutually overlapping control area A and operation area B, the circuit 111 of the control module and the circuit 211 of the operation module are electrically interconnected.

Each of the storage areas C overlaps with one of the control areas A and one of the operation areas B, and the storage area C includes a plurality of storage modules 310 arranged parallel to the fifth surface 301 . In area C, control area A and operation area B, the circuit 311 of the storage module and the circuit 211 of the operation module are electrically interconnected, and the circuit 311 of the storage module and the circuit 111 of the control module are electrically interconnected. electrical interconnection.

FIG. 7 is a schematic structural diagram of an apparatus for maximum pooling processing according to an embodiment of the present invention.

Correspondingly, an embodiment of the present invention also provides a device for maximum pooling processing. Please refer to FIG. 7 on the basis of FIG. 6 . The device 700 for maximum pooling processing includes: the above-mentioned chip (as shown in FIG. 6 ) ; an interface device 710, the interface device 710 is used to realize data transmission between the chip and an external device, and the interface device 710 is connected with the chip.

In this embodiment, the device 700 for maximum pooling processing further includes: a control device 720 for monitoring the state of the chip, the control device 720 is connected to the chip; a memory The storage device 730 is used for storing data in the chip, and the storage device 730 is connected to the chip.

FIG. 8 to FIG. 11 are schematic cross-sectional structural diagrams of each forming step of the semiconductor structure for maximum pooling processing according to another embodiment of the present invention.

Referring to FIG. 8, a first substrate 400 is provided, the first substrate 400 has a first surface 401 and a second surface 402 opposite to each other, the first substrate 400 includes a plurality of control areas A, the control areas A include parallel A plurality of control modules 410 are arranged on the first surface 401 , and the control modules 410 have circuits 411 of the control modules in them.

The material of the first substrate 400 includes semiconductor material.

In this embodiment, the material of the first substrate 400 includes silicon.

In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the first substrate 400 has a device layer (not shown) therein. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the control module 410 is configured to acquire and parse the maximum pooling instruction to acquire the data to be computed, the pooled core and the target address; after acquiring the data to be computed, the pooled core and the target address, The control module 410 is further configured to transmit the to-be-operated data and the pooled core to a subsequent operation module that is electrically interconnected with the circuit 411 of the control module 410 . The control module is further configured to transmit the to-be-operated data and the pooled core to a subsequent storage module electrically interconnected with the control module 410 .

In this embodiment, each of the control areas A includes one control module 410 .

In other embodiments, each control area includes two or more control modules.

In this embodiment, the first substrate 400 further includes a first metal interconnection layer 420, the first metal interconnection layer 420 is electrically interconnected with the circuit 411 of the control module 410, and the first surface 401 exposes the surface of the first metal interconnection layer 420 .

In this embodiment, the control area A further includes a plurality of memory addressing modules 450 arranged parallel to the first surface 401 , and the memory addressing modules 450 have circuits 451 of memory addressing modules, each The circuits 451 of the memory addressing module are electrically interconnected with the circuits 411 of one of the control modules.

Specifically, in this embodiment, each of the control areas A includes a memory addressing module 450 .

In another embodiment, each control area includes two or more memory addressing modules.

In other embodiments, the control area does not include a memory addressing module.

In this embodiment, the first substrate 400 further includes a circuit 411 surrounding the control module, a circuit 451 of the memory addressing module, and a first dielectric layer (not shown) of the first metal interconnection layer 420 icon).

Referring to FIG. 9, a second substrate 500 is provided, the second substrate 500 has opposite third surfaces 503 and fourth surfaces 504, the second substrate 500 includes a plurality of operation areas B, and the operation areas B include parallel A plurality of operation modules 510 are arranged on the third surface 503 , and the operation modules 510 have circuits 511 of the operation modules.

The material of the second substrate 500 includes semiconductor material.

In this embodiment, the material of the second substrate 500 includes silicon.

In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the second substrate 500 has a device layer (not shown) therein. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit 511 of the operation module 510 includes more than one comparator (not shown).

In this embodiment, the circuit 511 of the arithmetic module 510 further includes one or more arithmetic units (not shown).

In this embodiment, the operator includes a combination of one or more of an adder, a multiplier, a divider and a comparator.

The operation module 510 is configured to obtain the data to be calculated and the pooling core, perform a maximum pooling operation on the data to be calculated according to the pooling core to obtain an operation result, and store the operation result in the target. address.

In this embodiment, each of the operation regions B includes one operation module 510 .

In other embodiments, each of the operation regions includes two or more operation modules.

In this embodiment, the second substrate 500 further includes a second metal interconnection layer 520, the second metal interconnection layer 520 is electrically interconnected with the circuit 511 of the operation module 510, and the third surface 503 exposes the surface of the second metal interconnection layer 520 .

In this embodiment, the second substrate 500 further includes a fourth metal interconnection layer 530, the fourth metal interconnection layer 530 is electrically interconnected with the circuit 511 of the operation module 510, and the fourth surface 504 exposes the surface of the fourth metal interconnection layer 530 .

In this embodiment, the second substrate 500 further includes a second dielectric layer ( not shown in the figure).

Referring to FIG. 10, a third substrate 600 is provided, the third substrate 600 has a fifth surface 601, the third substrate 600 includes a plurality of storage areas C, and the storage areas C include rows parallel to the fifth surface 601 A number of storage modules 610 are distributed, and the storage modules 610 have circuits 611 of the storage modules.

The material of the third substrate 600 includes semiconductor material.

In this embodiment, the material of the third substrate 600 includes silicon.

In other embodiments, the material of the third substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

In this embodiment, the third substrate 600 has a device layer (not shown) therein. The device layer may include device structures, eg, PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

In this embodiment, the circuit 611 of the storage module includes one or both of a buffer and a register. The buffer includes one or both of a temporary buffer and a neuron buffer.

In this embodiment, the storage module 610 is configured to acquire the data to be calculated and the pooling core and store the data to be calculated and the pooling core.

In this embodiment, each of the storage areas C includes one storage module 610 .

In other embodiments, each of the storage areas includes two or more storage modules.

In this embodiment, the third substrate 600 further includes a fifth metal interconnection layer 620, the fifth metal interconnection layer 620 is electrically interconnected with the circuit 611 of the memory module, and the fifth surface 601 The surface of the fifth metal interconnection layer 620 is exposed.

In this embodiment, the third substrate 600 further includes a third dielectric layer (not marked in the figure) surrounding the fifth metal interconnection layer 620 and the circuit 611 of the memory module.

Referring to FIG. 11 , the first substrate 400 is bonded to the second substrate 500 , the first surface 401 faces the third surface 503 , each of the control areas A and one of the operation areas B Overlapping, in the overlapping control area A and operation area B, the circuit 411 of the control module and the circuit 511 of the operation module are electrically interconnected; and, the second substrate 500 and the third The substrate 600 is bonded, the fifth surface 601 faces the fourth surface 504, each of the storage areas C overlaps with one of the control areas A and one of the operation areas B, and the overlapping storage areas C, In the control area A and the operation area B, the circuit 611 of the storage module and the circuit 511 of the operation module are electrically interconnected, and the circuit 611 of the storage module and the circuit 411 of the control module are electrically interconnected .

Specifically, in the overlapping control region A, operation region B and storage region C, the first metal interconnection layer 420 and the second metal interconnection layer 520 are bonded to each other, and the fourth metal interconnection layer is bonded to each other. The connection layer 530 and the fifth metal interconnection layer 620 are bonded to each other.

In this embodiment, in the mutually overlapping control area A and operation area B, the circuit 411 of each control module is electrically interconnected with the circuit 511 of one operation module.

In another embodiment, the circuits of each of the control modules are electrically interconnected with the circuits of 2 or more arithmetic modules in the overlapping control and arithmetic regions.

In this embodiment, in the overlapping storage area C, control area A and operation area B, the circuit 411 of each control module and the circuit 611 of one storage module are electrically interconnected, and the circuit 611 of the control module is The circuit 611 of the storage module that is electrically interconnected by the circuit 411 is also electrically interconnected with the circuit 511 of the arithmetic module, and the circuit 511 of the arithmetic module and the circuit 411 of the control module are electrically interconnected.

In another embodiment, in the overlapping storage area, control area and operation area, the circuit of each control module is electrically interconnected with the circuit of 2 or more storage modules, and is electrically interconnected with the control module The circuit of the storage module is also electrically interconnected with the circuit of the arithmetic module, and the circuit of the arithmetic module and the circuit of the control module are electrically interconnected.

In this embodiment, the control module 410 has a first projection (not shown) on the first surface 401 , and the calculation module 510 has a second projection (not shown) on the first surface 401 , The storage module 610 has a third projection (not shown) on the first surface 401. In the overlapping storage area C, the control area A and the operation area B, the circuits of the calculation module 510 are electrically interconnected. The second projection and the third projection of the storage module 610 are both within the range of the first projection of the control module 410 .

12 is a schematic structural diagram of a semiconductor structure for maximum pooling processing according to another embodiment of the present invention.

Correspondingly, the present invention also provides a semiconductor structure for maximum pooling processing formed by the above forming method. Please refer to FIG. 12 on the basis of FIG. 11 . FIG. 11 is a schematic cross-sectional structure diagram of FIG. Including: a first substrate 400, the first substrate 400 has an opposite first surface 401 and a second surface 402, the first substrate 400 includes a plurality of control areas A, the control areas A include parallel to the first A plurality of control modules 410 arranged on the surface 401; a second substrate 500 bonded to the first substrate 400, the second substrate 500 has an opposite third surface 503 and a fourth surface 504, the first surface 401 Facing the third surface 503 , the second substrate 500 includes a plurality of operation areas B, each of the control areas A overlaps with one of the operation areas B, and the operation area B includes parallel to the third surface 503 A plurality of operation modules 510 are arranged, in the overlapping control area A and operation area B, the circuit 411 of the control module and the circuit 511 of the operation module are electrically interconnected.

The semiconductor structure for max-pooling processing further includes a third substrate 600 bonded to the first substrate 400 or the second substrate 500, the third substrate 600 has a fifth surface 601, and the third substrate 600 includes several storage areas C, each of the storage areas C overlaps with one of the control areas A and one of the operation areas B, and the storage area C includes several storage modules arranged parallel to the fifth surface 601 610. In the overlapping storage area C, control area A and operation area B, the circuit 611 of the storage module and the circuit 511 of the operation module are electrically interconnected, and the circuit 611 of the storage module is connected to the circuit 511 of the operation module. The circuits 411 of the control modules are electrically interconnected.

On the one hand, in the overlapping storage area C, control area A and operation area B, the circuit 411 of the control module and the circuit 511 of the operation module are electrically interconnected by bonding, and the circuit 511 of the storage module is electrically interconnected. The electrical interconnection between the circuit 611 and the circuit 511 of the arithmetic module, and the electrical interconnection between the circuit 611 of the storage module and the circuit 411 of the control module, therefore, the circuit 511 of the arithmetic module and the circuit of the control module Between 411 and the circuit 611 of the storage module, data can be directly transmitted, thereby increasing the speed of data transmission, increasing the bandwidth of the semiconductor structure for maximum pooling processing, and further improving the computing processing speed of the chip used for maximum pooling processing. , the performance of the chip used for max pooling is improved, the operation time of the chip used for max pooling is reduced, and the power consumption of the chip used for max pooling is reduced; on the other hand, due to the The first substrate 400 is bonded to the second substrate 500, the third substrate 600 is bonded to the first substrate 400 or the second substrate 500, and the control area A, the operation area B and the storage area C overlapping, thereby reducing the area of the semiconductor structure for max-pooling processing with a simple structure, thereby improving the integration degree of the chip for max-pooling processing.

In this embodiment, the third substrate 600 is bonded to the second substrate 500 , and the fifth surface 601 faces the fourth surface 504 .

In this embodiment, in the mutually overlapping control area A and operation area B, the circuit 411 of each control module is electrically interconnected with the circuit 511 of one operation module.

In another embodiment, the circuits of each of the control modules are electrically interconnected with the circuits of 2 or more arithmetic modules in the overlapping control and arithmetic regions.

In this embodiment, in the overlapping storage area C, control area A and operation area B, the circuit 411 of each control module and the circuit 611 of one storage module are electrically interconnected, and the circuit 611 of the control module is The circuit 611 of the storage module that is electrically interconnected by the circuit 411 is also electrically interconnected with the circuit 511 of the arithmetic module, and the circuit 511 of the arithmetic module and the circuit 411 of the control module are electrically interconnected.

In another embodiment, in the overlapping storage area, control area and operation area, the circuit of each control module is electrically interconnected with the circuit of 2 or more storage modules, and is electrically interconnected with the control module The circuit of the storage module is also electrically interconnected with the circuit of the arithmetic module, and the circuit of the arithmetic module and the circuit of the control module are electrically interconnected.

In this embodiment, each of the control areas A includes one control module 410 .

In other embodiments, each control area includes two or more control modules.

In this embodiment, the control area A further includes a plurality of memory addressing modules 450 arranged parallel to the first surface 401 , and the memory addressing modules 450 have circuits 451 of memory addressing modules, each The circuits 451 of the memory addressing module are electrically interconnected with the circuits 411 of one of the control modules.

Specifically, in this embodiment, each of the control areas A includes a memory addressing module 450 .

In another embodiment, each control area includes two or more memory addressing modules.

In other embodiments, the control area does not include a memory addressing module.

In this embodiment, each of the operation regions B includes one operation module 510 .

In other embodiments, each of the operation regions includes two or more operation modules.

In this embodiment, each of the storage areas C includes one storage module 610 .

In other embodiments, each of the storage areas includes two or more storage modules.

In this embodiment, the circuit 511 of the operation module 510 includes more than one comparator (not shown).

In this embodiment, the circuit 511 of the arithmetic module 510 further includes one or more arithmetic units (not shown). The operator includes a combination of one or more of an adder, a multiplier, a divider, and a comparator.

In this embodiment, the circuit 611 of the storage module includes one or both of a buffer and a register. The buffer includes one or both of a temporary buffer and a neuron buffer.

In this embodiment, the control module 410 is configured to acquire and parse the maximum pooling instruction to acquire the data to be computed, the pooled core and the target address; after acquiring the data to be computed, the pooled core and the target address, The control module 410 is further configured to transmit the data to be calculated and the pooled core to the operation module 510 electrically interconnected with the circuit 411 of the control module.

The control module 410 is further configured to transmit the to-be-operated data and the pooled core to a storage module 610 that is electrically interconnected with the circuit of the control module 410 .

The operation module 510 is configured to obtain the data to be calculated and the pooling core, perform a maximum pooling operation on the data to be calculated according to the pooling core to obtain an operation result, and store the operation result in the target. address.

The storage module 610 is configured to acquire the data to be calculated and the pooling core, and store the data to be calculated and the pooling core.

In this embodiment, the first substrate 400 further includes a first metal interconnection layer 420, the first metal interconnection layer 420 is electrically interconnected with the circuit 411 of the control module 410, and the first surface 401 exposes the surface of the first metal interconnection layer 420 .

In this embodiment, the first substrate 400 further includes a circuit 411 surrounding the control module, a circuit 451 of the memory addressing module, and a first dielectric layer (not shown) of the first metal interconnection layer 420 icon).

In this embodiment, the second substrate 500 further includes a second metal interconnection layer 520, the second metal interconnection layer 520 is electrically interconnected with the circuit 511 of the operation module 510, and the third surface 503 The surface of the second metal interconnection layer 520 is exposed, and in the overlapping control region A and the operation region B, the first metal interconnection layer 420 and the second metal interconnection layer 520 are bonded to each other combine.

In this embodiment, the second substrate 500 further includes a fourth metal interconnection layer 530, the fourth metal interconnection layer 530 is electrically interconnected with the circuit 511 of the operation module 510, and the fourth surface 504 exposes the surface of the fourth metal interconnection layer 530 .

In this embodiment, the second substrate 500 further includes a second dielectric layer ( not shown in the figure).

In this embodiment, the third substrate 600 further includes a fifth metal interconnection layer 620, the fifth metal interconnection layer 620 is electrically interconnected with the circuit 611 of the memory module, and the fifth surface 601 The surface of the fifth metal interconnection layer 620 is exposed, and in the overlapping control region A, operation region B and storage region C, the fourth metal interconnection layer 530 and the fifth metal interconnection layer 620 are bonded to each other.

In this embodiment, the third substrate 600 further includes a third dielectric layer (not marked in the figure) surrounding the fifth metal interconnection layer 620 and the circuit 611 of the memory module.

In this embodiment, the control module 410 has a first projection (not shown) on the first surface 401 , and the calculation module 510 has a second projection (not shown) on the first surface 401 , The storage module 610 has a third projection (not shown) on the first surface 401. In the overlapping storage area C, the control area A and the operation area B, the circuits of the calculation module 510 are electrically interconnected. The second projection and the third projection of the storage module 610 are both within the range of the first projection of the control module 410 .

Since the control module 410 has a first projection on the first surface 401 , the computing module 510 has a second projection on the first surface 401 , and the storage module 610 has a third projection on the first surface 401 Moreover, the second projection of the computing module 510 and the third projection of the storage module 610 that form electrical interconnection between the circuits are all within the range of the first projection of the control module 410. Therefore, on the one hand, it is beneficial to the control area. A. The mutual bonding between the storage area C and the operation area B. On the other hand, the area occupied by the storage module 610, the control module 410 and the operation module 510 is reduced, so as to achieve a simple structure to reduce the maximum The area of the semiconductor structure for pooling increases the level of integration of the chip used for maximum pooling.

13 is a schematic cross-sectional structure diagram of a chip according to another embodiment of the present invention.

Correspondingly, another embodiment of the present invention also provides a method for forming a chip, please refer to FIG. 6 , which includes: cutting the above-mentioned semiconductor structure for maximum pooling treatment to form several chips, each of which includes: A control area, a storage area C, and an operation area B, and each of the control areas A overlaps with one of the operation areas B, and each of the storage areas C overlaps with one of the control areas A and one of the operation areas B overlaps.

Correspondingly, another embodiment of the present invention also provides a chip formed based on the above-mentioned semiconductor structure for maximum pooling processing, please refer to FIG. 13 , including: a control area A, a storage area C and an operation area B, and each Each of the control areas A and one of the operation areas B overlap, and each of the storage areas C overlaps with one of the control areas A and one of the operation areas B.

The control area A includes a plurality of control modules 410 arranged parallel to the first surface 401; each of the control areas A overlaps with one of the operation areas B, and the operation area B includes A plurality of operation modules 510 arranged on the surface 503, in the mutually overlapping control area A and operation area B, the circuit 411 of the control module and the circuit 511 of the operation module are electrically interconnected.

Each of the storage areas C overlaps with one of the control areas A and one of the operation areas B, and the storage area C includes a plurality of storage modules 610 arranged parallel to the fifth surface 601 . In area C, control area A and operation area B, the circuit 611 of the storage module and the circuit 511 of the operation module are electrically interconnected, and the circuit 611 of the storage module and the circuit 411 of the control module are electrically interconnected. electrical interconnection.

14 is a schematic structural diagram of a device for maximum pooling processing according to another embodiment of the present invention.

Correspondingly, another embodiment of the present invention also provides a device for maximum pooling processing. Please refer to FIG. 14 on the basis of FIG. 13 . The device 800 for maximum pooling processing includes: the above-mentioned chip (as shown in FIG. 13 ). shown); an interface device 810, the interface device 810 is used to realize data transmission between the chip and an external device, and the interface device 810 is connected to the chip.

In this embodiment, the device 800 for maximum pooling processing further includes: a control device 820 for monitoring the state of the chip, the control device 820 is connected to the chip; a memory The storage device 830 is used for storing data in the chip, and the storage device 830 is connected to the chip.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (16)

1. A semiconductor structure for maximum pooling treatment, comprising: a first substrate, the first substrate has an opposite first surface and a second surface, the first substrate includes a plurality of control areas, and the control area includes a plurality of control modules arranged parallel to the first surface; a second substrate bonded to the first substrate, the second substrate has an opposite third surface and a fourth surface, the first surface faces the third surface, and the second substrate includes a plurality of operation areas , each of the control areas overlaps with one of the operation areas, and the operation area includes several operation modules arranged parallel to the third surface. In the overlapping control areas and operation areas, the electrical interconnection between the circuit and the circuit of the arithmetic module; A third substrate bonded to the first substrate or the second substrate, the third substrate has a fifth surface, and if the third substrate is bonded to the first substrate, the fifth surface faces The second surface, if the third substrate is bonded to the second substrate, the fifth surface faces the fourth surface, the third substrate includes a plurality of storage areas, each of the storage areas and One of the control areas and one of the operation areas overlap, the storage area includes several storage modules arranged parallel to the fifth surface, and in the overlapping storage area, control area and operation area, the storage modules The circuit of the storage module and the circuit of the control module are electrically interconnected. 2. The semiconductor structure for maximum pooling processing as claimed in claim 1, wherein in the overlapping control area and the operation area, the circuit of each described control module is electrically interconnected with the circuit of more than one operation module. even. 3. The semiconductor structure for maximum pooling processing according to claim 1 or 2, wherein in the overlapping storage area, control area and operation area, the circuit of each control module and more than one storage module The circuit of the memory module is electrically interconnected with the circuit of the control module, and the circuit of the storage module is also electrically interconnected with the circuit of the arithmetic module, and the circuit of the arithmetic module is electrically interconnected with the circuit of the control module. electrical interconnection. 4 . The semiconductor structure for max pooling processing according to claim 1 , wherein the circuit of the arithmetic module includes one or more comparators. 5 . 5 . The semiconductor structure for max pooling processing according to claim 4 , wherein the circuit of the arithmetic module further comprises one or more arithmetic units. 6 . 6 . The semiconductor structure for max pooling processing according to claim 5 , wherein the arithmetic unit comprises a combination of one or more of an adder, a multiplier, a divider and a comparator. 7 . 7 . The semiconductor structure for max pooling processing according to claim 1 , wherein the circuit of the storage module includes one or both of a buffer and a register. 8 . 8 . The semiconductor structure for max pooling according to claim 7 , wherein the buffer includes one or both of a temporary buffer and a neuron buffer. 9 . 9. The semiconductor structure for maximum pooling processing according to claim 1, wherein the control area further comprises a plurality of memory addressing modules arranged parallel to the surface of the first substrate, each of the memory addressing modules. The circuits of the address module are electrically interconnected with the circuits of one of the control modules. 10. The semiconductor structure of claim 1, wherein the control module has a first projection on the first surface, and the arithmetic module has a second projection on the first surface , the storage module has a third projection on the first surface, and in the overlapping storage area, control area and operation area, the second projection of the operation module and the third projection of the storage module that are electrically interconnected between circuits All are within the range of the first projection of the control module. 11. The semiconductor structure for maximum pooling processing according to claim 1, wherein the first substrate further comprises a first metal interconnection layer, and the first metal interconnection layer is connected to the control module. circuit electrical interconnection, the first surface exposes the surface of the first metal interconnection layer, the second substrate further includes a second metal interconnection layer, the second metal interconnection layer and the computing module The circuit is electrically interconnected, the third surface exposes the surface of the second metal interconnection layer, and, in the overlapping control region and operation region, the first metal interconnection layer and the second metal interconnection layer The interconnect layers are bonded to each other. 12. The semiconductor structure of claim 11, wherein if the third substrate is bonded to the first substrate, the first substrate further comprises a third metal interconnection layer , the third metal interconnection layer is electrically interconnected with the circuit of the control module, the second surface exposes the surface of the third metal interconnection layer, and the third substrate further includes a fifth metal interconnection layer, the fifth metal interconnect layer is electrically interconnected with circuits of the memory module, the fifth side exposes the surface of the fifth metal interconnect layer, and the third metal interconnect layer and the The fifth metal interconnection layers are bonded to each other. 13. The semiconductor structure of claim 11, wherein if the third substrate is bonded to the second substrate, the second substrate further comprises a fourth metal interconnection layer , the fourth metal interconnection layer is electrically interconnected with the circuit of the computing module, the fourth surface exposes the surface of the fourth metal interconnection layer, and the third substrate further includes a fifth metal interconnection layer, the fifth metal interconnect layer is electrically interconnected with circuits of the memory module, the fifth side exposes the surface of the fifth metal interconnect layer, and the fourth metal interconnect layer and the The fifth metal interconnection layers are bonded to each other. 14. A chip based on the semiconductor structure for maximum pooling processing according to any one of claims 1 to 13, characterized in that, comprising: A control area, a storage area, and an operation area, and each of the control areas overlaps with one of the operation areas, and each of the storage areas overlaps with one of the control areas and one of the operation areas. 15. A device for maximum pooling processing, characterized in that it comprises: The chip of claim 14; An interface device, the interface device is used to realize data transmission between the chip and an external device, and the interface device is connected with the chip. 16. The device for maximum pooling processing according to claim 15, further comprising: a control device, the control device is used to monitor the state of the chip, and the control device is connected to the chip ; a storage device, the storage device is used for storing data in the chip, and the storage device is connected to the chip.

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