CN211123733U - Extensible P L C core module - Google Patents

Abstract

The utility model provides an extensible P L C core module, a serial communication port, P L C core module includes a CPU the control unit (it contains 4 way UART buses, 2 way CAN buses, 1 way 100M ethernet bus, 8 way analog input, 2 way analog output, 40 digital input/output, 2 high-speed counter inputs, 2 way PWM outputs), a ROM memory cell, a RAM flash memory unit, a power module, CPU the control unit passes through bus connection with RAM flash memory unit and ROM memory cell, ROM memory cell includes NAND F L ASH flash memory and SPI F L ASH flash memory, power module includes 5V changes 3.3V power module.

Description

Extensible P L C core module

Technical Field

The utility model relates to a P L C development field especially relates to P L C's software and hardware development.

Background

However, with the advancement of science and technology and the rapid development of the automation field, more and more enterprises and industries need to use the P L C to realize automatic control, such as agricultural mechanical automation, the automobile industry, intelligent medical treatment, smart cities, intelligent buildings, stage automation and the like, so that for a P L C developer, the P L C product cannot be well applied to each industry, and if the P L C developer is developed for each industry and even each user independently, the cost is very high, therefore, the P L C developer needs to develop a P L C core module which can be basically applied to most industries, and different functions can be realized by using different bottom plates, so that the development time can be effectively shortened.

SUMMERY OF THE UTILITY MODEL

The to-be-solved problem of the utility model is to provide an extensible P L C core module, including a CPU control processing unit, a ROM memory cell, a RAM flash memory unit, a power module and function pin are drawn forth, can supply the user to develop the product.

The CPU control unit is characterized by comprising 4 paths of UART buses, 2 paths of CAN buses, 1 path of 100M Ethernet buses, 8 paths of analog quantity inputs, 2 paths of analog quantity outputs, 40 digital input/outputs, 2 high-speed counter inputs and 2 paths of PWM outputs.

The ROM storage unit is characterized by comprising a NAND F L ASH flash memory, and the SPI F L ASH flash memory is connected with the CPU control unit.

The RAM memory unit is characterized by comprising a Synchronous Dynamic Random Access Memory (SDRAM) connected with the CPU control unit.

The power module is characterized by comprising a 5V to 3.3V power supply module.

The utility model relates to a P L C core module that can supply the development product, the module has contained SDRAM and NANDDF L ASH, can read and write data fast, preserves data, the bottom driver of this module uses the real-time kernel of extensible, and the user can freely expand peripheral circuit according to the function of the pin of having defined, again to the function that its programming realization wanted.

The utility model discloses at the during operation, can save data in real time, do not worry because of the data loss and the program that cause suddenly fall the power down and lose.

After the technical scheme is adopted, the utility model discloses at least, following gain has:

1. with 256M NAND F L ASH, can save system image files and file systems;

2. with 64M SDRAM, a program with a large occupied space can be executed.

3. The CPU with 218M high main frequency greatly improves the program execution speed and efficiency.

4. Can be used as hardware support for process signal processing and as part of an intelligent network node.

5. Can be used as the core of a motion controller.

Drawings

Fig. 1 is a schematic diagram of the operating principle of the program access between the CPU and the memory according to the present invention.

Fig. 2 is a block diagram of the present invention.

Detailed Description

The present invention will be described in further detail with reference to fig. 1 and 2. It should be noted that the features of the examples and example implementations in this application may be combined with each other without conflict.

As shown in FIG. 1, the present invention provides a P L C core module for development, including a CPU controller, SDRAM, NAND F L ASH, and a power supply module, wherein SDRAM, i.e. synchronous dynamic random access memory, can be any one of the SDRAMs on the market, which has the advantages of synchronizing the clock signals of CPU and RAM, so that CPU and RAM share one clock cycle, and operate at the same speed, thereby solving the speed mismatch between CPU and RAM, avoiding the extra waiting time required for synchronization when the system bus operates asynchronous DRAM, and speeding up the data transmission.

As shown in fig. 1, after power is supplied to the power module, the CPU first operates to initialize the SDRAM, and then determines whether a valid control program is found in the nonvolatile memory, if so, reads the program from the NAND F L ASH into the SDRAM, and the SDRAM executes the read program, otherwise, enters the stop mode.

As shown in fig. 2, the present invention can be externally connected to various devices and peripheral circuits to realize various functions. In this embodiment, RS232 or RS485 serial port communication can be performed by externally connecting an RS232 or RS485 transceiver; the TCP or Modbus TCP communication can be carried out through an external Ethernet transceiver; the CAN bus communication CAN be realized by externally connecting a CAN transceiver; the input/output of digital quantity and pulse can be controlled by externally connecting a digital quantity isolation and protection circuit; the output of analog quantity voltage/current can be realized by externally connecting a digital-to-analog conversion module.

In addition, the utility model discloses still support functions such as motion control, process signal processing, centralized monitoring, intelligent network node, distributed control system. The user can expand the peripheral circuit as required by oneself, realizes the function that oneself wanted.

Claims (1)

1. A scalable P L C core module is characterized in that the P L C core module comprises a CPU control unit (comprising 4 paths of UART buses, 2 paths of CAN buses, 1 path of 100M Ethernet buses, 8 paths of analog quantity inputs, 2 paths of analog quantity outputs, 40 digital input/outputs, 2 high-speed counter inputs and 2 paths of PWM outputs), a ROM storage unit, a RAM flash memory unit and a power supply module, wherein the CPU control unit is connected with the RAM flash memory unit and the ROM storage unit through buses, the ROM storage unit comprises a NAND F L ASH flash memory and an SPI F L ASH flash memory, and the power supply module comprises a 5V to 3.3V power supply module.

Images