CN211123658U - Serial communication simulation board card - Google Patents
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- CN211123658U CN211123658U CN202020034438.2U CN202020034438U CN211123658U CN 211123658 U CN211123658 U CN 211123658U CN 202020034438 U CN202020034438 U CN 202020034438U CN 211123658 U CN211123658 U CN 211123658U
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- 238000004891 communication Methods 0.000 title claims abstract description 110
- 238000004088 simulation Methods 0.000 title claims description 29
- 230000002093 peripheral effect Effects 0.000 claims abstract description 23
- 238000006243 chemical reaction Methods 0.000 claims description 24
- 230000002457 bidirectional effect Effects 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 15
- 238000012360 testing method Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000005094 computer simulation Methods 0.000 description 5
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Abstract
The utility model discloses a serial communication emulation integrated circuit board, include: the communication interface comprises a serial peripheral communication interface and an upper computer interface which is used for being in communication connection with an upper computer, the serial peripheral communication interface comprises a DIS data line, and the DIS data line is used for being connected with a DO data line of the slave SPI equipment and obtaining output data of the slave SPI equipment so as to monitor the output data of the slave SPI equipment; an FPGA connected to the communication interface; and the power supply system is connected to the FPGA and used for supplying power to the FPGA. The technical scheme of the utility model, can improve the reliability and the reusability of serial communication emulation integrated circuit board test at least.
Description
Technical Field
The utility model relates to a data simulation technical field, more specifically relates to a serial communication emulation integrated circuit board.
Background
The SPI (Serial Peripheral Interface) sensor simulation board card can be used for simulation and emulation of a hall sensor, a yaw rate sensor, an acceleration sensor, and an SBC (System Basic Chip) In HI L (Hardware-In-the-L oop, Hardware-In-the-ring).
The existing simulation and emulation method of the SPI sensor in the HI L is to place the SPI sensor in a specific physical environment, and physically apply different test stimulus items to the SPI sensor to test the reliability of the whole system.
As above, because the existing SPI sensor simulation method needs to rely on sensors to generate SPI data under different physical environments to test the reliability of the whole system, the existing SPI sensor simulation method has the following main problems: 1. the physical environment is complex to build, and different test items need to be frequently switched among different physical environments; 2. some extreme physical environments are not or are more difficult to reach; 3. the test is time-consuming, and the automatic test is not easy to realize; 4. different physical environments need to be constructed for different SPI sensors, and the reusability is not high.
In addition, in the process of simulating the sensor by the existing SPI sensor simulation board, the SPI sensor simulation board needs to complete a complete communication process with the main SPI device, which may cause the following problems: 1. the SPI sensor simulation board card needs to strictly meet the master-slave SPI communication protocol; 2. the reusability is low, and different FPGA logic circuits need to be customized for different main SPI equipment for the simulation of the same sensor; 3. the reliability of the SPI sensor simulation board is low.
SUMMERY OF THE UTILITY MODEL
To the above-mentioned problem among the correlation technique, the utility model provides a serial communication emulation integrated circuit board can replace sensor and main SPI equipment to communicate to improve the reliability and the reusability of serial communication emulation integrated circuit board test.
The utility model provides a serial communication emulation integrated circuit board, include:
the communication interface comprises a serial peripheral communication interface and an upper computer interface which is used for being in communication connection with an upper computer, the serial peripheral communication interface comprises a DIS data line, and the DIS data line is used for being connected with a DO data line of the slave SPI equipment and obtaining output data of the slave SPI equipment so as to monitor the output data of the slave SPI equipment;
an FPGA connected to the communication interface;
and the power supply system is connected to the FPGA and used for supplying power to the FPGA.
According to the utility model discloses an embodiment, serial peripheral hardware communication interface is still including being connected to FPGA: the device comprises a DIM data line used for being connected with a DO data line of the main SPI equipment, a DIO bidirectional data line used for being connected with a DI data line of the main SPI equipment, an SCK input data line used for being connected with an SCK data line of the main SPI equipment and a first chip selection signal data line used for receiving a first chip selection signal of the main SPI equipment.
According to the utility model discloses an embodiment, communication interface still includes chip selection input interface, and chip selection input interface is including being used for receiving second chip selection signal to seventh chip selection signal respectively and the second chip selection signal data line to the seventh chip selection signal data line of being connected with FPGA respectively.
According to the utility model discloses an embodiment, electrical power generating system includes: the power supply input interface is used for being connected with power supply voltage outside the serial communication simulation board card; a voltage reference interface for connection to a logic reference voltage of a primary SPI device; and the power supply circuit is used for supplying power to the FPGA and is connected with the power supply input interface and the voltage reference interface through the reference voltage change-over switch.
According to the utility model discloses an embodiment, serial communication emulation integrated circuit board still includes the voltage conversion module, and the voltage conversion module includes: the input end of the digital isolation and level conversion circuit is connected with the chip selection input interface and the serial peripheral communication interface, the output end of the digital isolation and level conversion circuit is connected with the FPGA, and the digital isolation and level conversion circuit is also connected with the power supply system.
According to the utility model discloses an embodiment, voltage conversion module still includes: and the electrostatic protection circuit, the chip selection input interface and the serial peripheral communication interface are connected to the input end of the digital isolation and level conversion circuit through the electrostatic protection circuit.
According to the utility model discloses an embodiment is 4 lines SPI sensor from SPI equipment, and wherein, the DO data line of main SPI equipment is connected in DIM data line, and the DI data line of main SPI equipment is connected in the two-way data line of DIO, and the SCK data line of main SPI equipment is connected in SCK input data line, and the chip selection signal data line of main SPI equipment is connected in first piece selection signal data line.
According to the utility model discloses an embodiment is 3 lines SPI sensor from SPI equipment, and wherein, the DIO data line of main SPI equipment is connected in the two-way data line of DIO, and the SCK data line of main SPI equipment is connected in SCK input data line, and the chip selection signal data line of main SPI equipment is connected in first piece selection signal data line.
According to the utility model discloses an embodiment, be I2C interface sensor from SPI equipment, wherein, the DIO data line of main SPI equipment is connected in the two-way data line of DIO, and the SCK data line of main SPI equipment is connected in SCK input data line.
The utility model discloses an above-mentioned technical scheme, dispose from the data output accessible host computer of SPI equipment, consequently can realize communicating with main SPI equipment by host computer model analog sensor place physical environment, serial communication emulation integrated circuit board can replace communicating from SPI equipment and main SPI equipment, realizes the test to main SPI equipment and its entire system's reliability to can realize following the automatic configuration of SPI equipment data full range through the host computer model. In addition, because the data input data line of the slave SPI equipment is added in the equipment communication interface, the data output of the slave SPI equipment can be monitored, so that data reference can be provided for communication with the master SPI equipment, the communication is more reliable, and the reusability is higher.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit block diagram of a serial communication emulation board according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a logic circuit of the FPGA of the serial communication emulation board according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a serial communication emulation board card simulating a 7-way 4-wire SPI sensor according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a serial communication emulation board card simulating a 7-way 3-wire SPI sensor according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a principle that the serial communication emulation board simulates a 1-way I2C interface sensor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art all belong to the protection scope of the present invention.
Fig. 1 is a circuit block diagram of a serial communication emulation board according to an embodiment of the present invention. As shown in fig. 1, the communication interface 110 of the serial communication emulation board 100 according to the embodiment of the present invention includes an upper computer interface 112 and a serial peripheral communication interface 114. The upper computer interface 112 is used for connecting with an upper computer. The Serial Peripheral communication Interface 114 includes a DIS (Data input from SPI device) Data line for connecting to a DO (Data output) Data line of an SPI (Serial Peripheral Interface) device and for acquiring output Data from the SPI device through the DO Data line, so that the output Data transmitted from the DO Data line of the SPI device can be monitored through the DIS Data line.
The serial communication emulation board 100 further includes an FPGA (Field programmable gate Array) 130 connected to the communication interface 110. The serial communication emulation integrated circuit board 100 of the present invention further comprises a power system 140 connected to the FPGA130 and configured to supply power to the FPGA 130. The power system 140 may also provide a power input to the serial communication emulation board 100.
With reference to fig. 1 and fig. 2, taking the slave SPI device as the SPI sensor 400 as an example, the upper computer 200 may simulate sensor data through a model and send the sensor data to the serial communication simulation board 100 in real time, receive the sensor data sent by the upper computer 200 through the upper computer interface 112, communicate the SPI sensor 400 with the master SPI device 300 through the serial peripheral communication interface 114, and simultaneously, the FPGA130 may monitor output data sent on a DO data line of the simulated SPI sensor 400 through a DIS data line. Like this, sensor data accessible host computer 200 disposes, SPI sensor data can communicate with main SPI equipment 300 under the control of host computer model, consequently can realize by host computer model simulation sensor place physical environment and main SPI equipment 300 communicate, serial communication emulation integrated circuit board 100 can replace SPI sensor 400 and main SPI equipment 300 to communicate, the realization is to the test of main SPI equipment 300 and its entire system's reliability, and can realize sensor data full-scale within-range automated configuration through the host computer model. Moreover, since the DIS data line is added to the serial peripheral communication interface 114, the output data sent on the DO data line of the SPI sensor 400 can be monitored, so that a data reference can be provided for communication with the main SPI device 300, which makes the communication more reliable and the reusability higher.
Specifically, as shown in fig. 2, the upper computer 200 sends the sensor data to the serial communication emulation board 100 in real time, and the serial communication emulation board 100 monitors the output data sent on the DO data line of the SPI sensor 400 through the FPGA130 and communicates with the master SPI device 300 at the same time. More specifically, the FPGA130 includes a Command (Command) processing module 132, an SPI Command (SPI _ Command) processing module 134, and an audit (Scope) module 136. The command processing module 132 is connected to the upper computer 200 and configured to analyze data sent to the serial communication emulation board 100 by the upper computer 200. The SPI command processing module 134 is connected to the primary SPI device 300, and parses and replies to the command of the primary SPI device 300. The SPI command processing module 134 is connected to the command processing module 132 and the auditing module 136, and is configured to receive data of the upper computer 200 and the auditing module 136 as a reference for communication with the master SPI device 300. The audit module 136 is also connected to the emulated SPI sensor 400 to monitor the contents of data frames that the SPI sensor 400 communicates with the primary SPI device 300. Meanwhile, the monitoring module 136 sends the output data of the SPI sensor 400 sent on the DO data line to the SPI command processing module 134 for analysis, so as to provide a data reference for the communication between the serial communication emulation board 100 and the primary SPI device 300.
With continued reference to fig. 1, the serial peripheral communication interface 114 further includes a DIM (Data input from Master) Data line, a DIO (Data input output) bidirectional Data line, an SCK (clock signal) input Data line, and a first chip select signal (CS1) Data line, where the DIM Data line is used to connect with a DO Data line of the Master SPI device, the DIO bidirectional Data line is used to connect with a DI Data line of the Master SPI device, the SCK input Data line is used to connect with a SCK Data line of the Master SPI device, and the CS1 Data line is used to receive the first chip select signal CS1 of the Master SPI device. The serial peripheral communication interface 114 may specifically include 1 DIS interface connected to a DIS data line and a set of standard serial communication data line interfaces. The DIS interface may be connected with the DO interface of the slave SPI device to monitor output data from the slave SPI device. A standard serial communication data line interface may be used to interface with the primary SPI device to enable communication between the DIM data line, DIO bidirectional data line, SCK input data line, and CS1 data line with the primary SPI device.
The communication interface 110 also includes a chip select input interface 116. The chip select input interface 116 is a multi-way chip select input interface. Specifically, the chip select input interface 116 includes CS2 data lines to CS7 data lines for receiving the second to seventh chip select signals CS2, CS3, CS4, CS5, CS6, and CS7, respectively, so that simulation of a 7-way slave SPI device can be supported by the chip select signals CS1-CS 7. It can support to insert a plurality of chip selection signals through chip selection input interface 116 the utility model discloses a plurality of SPI equipment of following, for example a plurality of SPI sensors, are simulated to serial communication emulation integrated circuit board 100. The connection between the data line and the master SPI device in various embodiments and the application of the chip select signal will be described in more detail below with reference to the embodiments of fig. 3 to 5.
Referring to fig. 1, the serial communication emulation board 100 further includes a voltage conversion module 160, the voltage conversion module 160 includes a digital isolation and level conversion circuit 161, an input terminal of the digital isolation and level conversion circuit 161 is connected to the chip selection input interface 116 and the serial peripheral communication interface 114, an output terminal of the digital isolation and level conversion circuit 161 is connected to the FPGA130, and the digital isolation and level conversion circuit 161 is further connected to the power system 140. The voltage conversion module 160 may further include an electrostatic protection circuit 162, and the chip select input interface 116 and the serial peripheral communication interface 114 are connected to an input terminal of the digital isolation and level conversion circuit 161 through the electrostatic protection circuit 162. The voltage conversion module 160 can implement logic level conversion between a master SPI device and a slave SPI device, and has antistatic and digital isolation functions.
The power supply system 140 specifically includes a power input interface 141 for connecting to a power supply external to the serial communication emulation board 100, a voltage reference interface 142 for connecting to a logic reference voltage of the primary SPI device 300, and a power supply circuit 143 for supplying power to the FPGA130, the power supply circuit 143 being connected to the power input interface 141 and to the voltage reference interface 142 via a reference voltage changeover switch 144. The power supply circuit 143 can convert the external supply voltage to the voltages required by the FPGA130 and the digital isolation and level shift circuit 161. The reference voltage switch 144 may control the SPI logic reference voltage to be provided by the power system 140 or by a power supply external to the serial communication emulation board 100.
Since the serial peripheral communication interface 114 includes 5 data lines: 1 way DIS data line, 1 way DIM data line, 1 way DIO two-way data line, 1 way SCK input data line and 1 way CS1 data line, consequently the utility model discloses a serial communication emulation integrated circuit board 100 can compatible 3 line SPI sensors, 4 line SPI sensors and I2C sensor emulation.
Fig. 3 is according to the utility model discloses a principle schematic diagram of SPI sensor emulation board simulation 7 way 4 line SPI sensor. As shown in FIG. 3, primary SPI device 300 is connected to a DIM data line, a DIO bidirectional data line, an SCK input data line, and a CS1 data line. The sensor data is configured through the upper computer 200 and is sent to the serial communication simulation board 100 in real time. The serial communication simulation board card 100 analyzes the sensor data sent by the upper computer 200 and stores the sensor data in a specific register in real time. The output data sent on the DO data line of the emulated SPI sensor 400 is received through the DIS data line, and the output data on the DO data line is stored in a specific register in real time. The serial communication emulation board 100 communicates with the master SPI device 300 when the chip select signal CS1 on the CS1 data line is active in synchronization with the clock signal SCK transmitted from the master SPI device 300. The CS1 data lines through the CS7 data lines are all connected to the master SPI device 300, so that the serial communication emulation board 100 supports emulation of up to 7 slave SPI devices (e.g., SPI sensors). The overall operation of the embodiment shown in fig. 3 is as follows: the serial communication simulation board 100 replies the primary SPI device 300 by referring to the output data of the SPI sensor 400 acquired by the DIO data line and the sensor data configured by the upper computer 200 according to the instruction sent by the primary SPI device 300; the logic reference level of the SPI sensor 400 may be configured to be provided by a power supply external to the serial communication emulation board 100 or provided by the internal power circuit 143 through the reference voltage switch 144 (fig. 1).
Fig. 4 is according to the utility model discloses a principle schematic diagram of serial communication emulation integrated circuit board simulation 7 way 3 lines SPI sensor. As shown in FIG. 4, primary SPI device 300 is connected to the DIO bidirectional data line, the SCK input data line, and the CS1 data line. Configuring sensor data through the upper computer 200, and sending the sensor data to the serial communication simulation board card 100 in real time; the serial communication simulation board card 100 analyzes the sensor data sent by the upper computer 200 and stores the sensor data in a specific register in real time. The DIO bidirectional data line of the serial communication emulation board 100 is connected to the DIO bidirectional data line of the primary SPI device 300. The serial communication emulation board 100 communicates with the master SPI device 300 when the chip select signal CS1 on the CS1 data line is active in synchronization with the clock signal SCK transmitted by the master SPI device 300. The CS1 data lines through the CS7 data lines are all connected to the master SPI device 300, so that the serial communication emulation board 100 supports emulation of up to 7 slave SPI devices. The whole working process is as follows: the serial communication emulation board 100 replies to the primary SPI device 300 with reference to the data configured by the upper computer 200 according to the instruction sent by the primary SPI device 300. Similarly, the logic reference level of the SPI sensor 400 may be configured to be provided by a power supply external to the serial communication emulation board 100 or provided by the internal power circuit 143 through the reference voltage switch 144 (fig. 1).
Fig. 5 is a schematic diagram illustrating a principle that the serial communication emulation board simulates a 1-way I2C sensor according to an embodiment of the present invention. The serial communication emulation board 100 can support emulation of a 1-way I2C interface from an SPI device. The slave SPI device in this embodiment is an I2C interface sensor. As shown in FIG. 5, the I2C master 500 is connected to DIO bidirectional data lines and SCK input data lines. The upper computer 200 of the serial communication simulation board 100 configures sensor data and transmits the sensor data to the serial communication simulation board 100 in real time. The serial communication simulation board card 100 analyzes the sensor data sent by the upper computer 200 and stores the data in a specific register in real time. The SCK input data line of the serial communication emulation board 100 is connected to the SCK data line of the I2C host 500, and the DIO bidirectional data line is connected to the DIO bidirectional data line of the I2C host 500. The whole working process is as follows: the serial communication simulation board card 100 replies to the I2C host device 500 with reference to the sensor data configured by the host computer 200 according to the instruction sent by the I2C host device 500. Similarly, the logic reference level of the I2C interface sensor may be configured to be provided by a power supply external to the serial communication emulation board 100 or provided by the internal power circuit 143 via the reference voltage switch 144 (fig. 1).
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A serial communication emulation integrated circuit board, its characterized in that includes:
the communication interface comprises a serial peripheral communication interface and an upper computer interface which is used for being in communication connection with an upper computer, the serial peripheral communication interface comprises a DIS data line, and the DIS data line is used for being connected with a DO data line of a slave SPI device and used for acquiring output data of the slave SPI device so as to monitor the output data of the slave SPI device;
an FPGA connected to the communication interface;
a power system connected to the FPGA and configured to power the FPGA.
2. The serial communication emulation board of claim 1 wherein the serial peripheral communication interface further comprises, connected to the FPGA: the device comprises a DIM data line used for being connected with a DO data line of the main SPI equipment, a DIO bidirectional data line used for being connected with a DI data line of the main SPI equipment, an SCK input data line used for being connected with an SCK data line of the main SPI equipment and a first chip selection signal data line used for receiving a first chip selection signal of the main SPI equipment.
3. The serial communication emulation board of claim 2, in which the communication interface further comprises a chip select input interface comprising second through seventh chip select signal data lines for receiving second through seventh chip select signals, respectively, and connected to the FPGA, respectively.
4. The serial communication emulation board card of claim 1, wherein the power system comprises:
the power supply input interface is used for being connected with power supply voltage outside the serial communication simulation board card;
a voltage reference interface for connection to a logic reference voltage of a primary SPI device;
and the power supply circuit is used for supplying power to the FPGA and is connected with the power supply input interface and the voltage reference interface through a reference voltage change-over switch.
5. The serial communication emulation board card of claim 3 further comprising a voltage conversion module, said voltage conversion module comprising:
and the input end of the digital isolation and level conversion circuit is connected with the chip selection input interface and the serial peripheral communication interface, the output end of the digital isolation and level conversion circuit is connected with the FPGA, and the digital isolation and level conversion circuit is also connected with the power supply system.
6. The serial communication emulation board card of claim 5, wherein the voltage conversion module further comprises:
and the chip selection input interface and the serial peripheral communication interface are connected to the input end of the digital isolation and level conversion circuit through the electrostatic protection circuit.
7. The serial communication emulation board card of claim 2, wherein the slave SPI device is a 4-wire SPI sensor, wherein the DO data line of the master SPI device is connected to the DIM data line, the DI data line of the master SPI device is connected to the DIO bidirectional data line, the SCK data line of the master SPI device is connected to the SCK input data line, and the chip select signal data line of the master SPI device is connected to the first chip select signal data line.
8. The serial communication emulation board card of claim 2, wherein the slave SPI device is a 3-wire SPI sensor, wherein a DIO data line of the master SPI device is connected to the DIO bidirectional data line, an SCK data line of the master SPI device is connected to the SCK input data line, and a chip select signal data line of the master SPI device is connected to the first chip select signal data line.
9. The serial communication emulation board card of claim 2, wherein the slave SPI device is an I2C interface sensor, wherein the DIO data line of the master SPI device is connected to the DIO bidirectional data line, and the SCK data line of the master SPI device is connected to the SCK input data line.
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| CN202020034438.2U CN211123658U (en) | 2020-01-08 | 2020-01-08 | Serial communication simulation board card |
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| CN202020034438.2U CN211123658U (en) | 2020-01-08 | 2020-01-08 | Serial communication simulation board card |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118011868A (en) * | 2024-04-08 | 2024-05-10 | 杭州沃镭智能科技股份有限公司 | Rotary transformer and eddy current position sensor simulation board card |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118011868A (en) * | 2024-04-08 | 2024-05-10 | 杭州沃镭智能科技股份有限公司 | Rotary transformer and eddy current position sensor simulation board card |
| CN118011868B (en) * | 2024-04-08 | 2024-06-11 | 杭州沃镭智能科技股份有限公司 | Rotary transformer and eddy current position sensor simulation board card |
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Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |
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