CN211087930U - Memory reliability testing device - Google Patents
Memory reliability testing device Download PDFInfo
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- CN211087930U CN211087930U CN202020271990.3U CN202020271990U CN211087930U CN 211087930 U CN211087930 U CN 211087930U CN 202020271990 U CN202020271990 U CN 202020271990U CN 211087930 U CN211087930 U CN 211087930U
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Abstract
The utility model provides a memory reliability testing device, which comprises a controller, a power supply module and a testing station, wherein the testing station is used for placing a chip to be tested; the power supply module is connected with the chip to be tested and the controller and respectively supplies power to the controller and the chip to be tested; the controller is respectively connected with the chip to be tested and the power supply module and controls the test voltage output of the power supply module and the flash operation of the chip to be tested. The testing device can test various voltage waveforms aiming at the flash module of the chip to be tested, and the test result is more comprehensive and accurate.
Description
Technical Field
The utility model relates to an electronic circuit field, concretely relates to memory reliability testing arrangement.
Background
With the wide application of electronic circuit systems in daily life, the service life of electronic products is more and more emphasized. The chip is internally provided with a very complex system, a built-in memory is a very important module, and the flash module of the chip stores core data of the whole system, so the quality of the flash module directly influences the quality of the whole chip, and if the flash module has quality problems, serious consequences such as crash, program runaway and the like can be caused. This concern is necessary, and there have been cases in the market where the flash module cannot adapt to the voltage variation due to unstable power supply voltage, resulting in the loss of the flash program. Therefore, a high-reliability flash memory chip is crucial to a design company to improve enterprise competitiveness and industrial profit.
Generally, the reliability test of a flash memory chip has the characteristics of long test time and large test quantity, in the test process, the test voltage is usually limited to be converted from a certain specific voltage value to another specific voltage value, and the test channel is limited, so that the reliability test of the flash memory chip cannot be comprehensively and massively performed.
SUMMERY OF THE UTILITY MODEL
The utility model provides a memory reliability testing arrangement, this testing arrangement can carry out the test of multiple voltage waveform to the flash module that awaits measuring the chip, and the test result is more comprehensive, accurate.
The utility model discloses a following technical scheme realizes:
a memory reliability testing device comprises a controller, a power supply module and a testing station,
the test station is used for placing a chip to be tested;
the power supply module is connected with the chip to be tested and the controller and respectively supplies power to the controller and the chip to be tested;
the controller is respectively connected with the chip to be tested and the power supply module and controls the test voltage output of the power supply module and the flash operation of the chip to be tested.
Specifically, the test voltage varies according to the test mode.
Specifically, the test modes comprise a fluctuation test, a steep rising and dropping test and an intermittent power failure test.
Specifically, the test voltage under the fluctuation test is a sine wave or/and a triangular wave.
Specifically, the test voltage under the steep rising and dropping test is a square wave.
Specifically, the test voltage under the intermittent power-off test is an intermittent wave.
Specifically, the test station has a plurality of.
Specifically, the testing device further comprises a display for displaying the testing result of the chip to be tested.
The utility model discloses a power module is for awaiting measuring the chip and provide multiple test voltage under the different test mode, including voltage fluctuation test, steep rising steep drop test of voltage and intermittent type nature outage test, carry out more comprehensive test to the flash module of the chip that awaits measuring, the test result is more reliable. In addition, a plurality of test stations are additionally arranged, and simultaneous test of a large number of chips can be met.
Drawings
Fig. 1 is a circuit module structure diagram of a memory reliability testing apparatus according to a first embodiment, a second embodiment, and a third embodiment of the present invention.
Fig. 2A, 2B, 2C are waveform diagrams of the test voltage under the fluctuation test provided by the embodiment of the present invention.
Fig. 3A, 3B, and 3C are waveform diagrams of another test voltage under the ripple test provided by the first embodiment of the present invention.
Fig. 4A, 4B, and 4C are waveform diagrams of the test voltage under the steep rise and fall test provided by embodiment two of the present invention.
Fig. 5 is a waveform diagram of the test voltage under the intermittent power-off test provided by the third embodiment of the present invention.
Fig. 6 is a circuit module configuration diagram of a multi-test-station memory reliability testing apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
The utility model provides a memory reliability testing device, as shown in figure 1, the testing device comprises a controller, a power module and a testing station, wherein the testing station is used for placing a chip to be tested;
the power supply module is connected with the chip to be tested and the controller and respectively supplies power to the controller and the chip to be tested;
the controller is respectively connected with the chip to be tested and the power supply module and controls the test voltage output of the power supply module and the flash operation of the chip to be tested.
The test voltage output by the power module to the chip to be tested under the control of the controller may be different according to different test modes, and is specifically described by the following embodiments one to three:
the first embodiment is as follows:
in this embodiment, as a specific implementation manner of the test mode, the power module outputs the test voltage in a fluctuation state to the chip to be tested under the control of the controller, and the specific fluctuation amplitude and frequency may be set according to the test requirement, which is not limited herein.
As an example, the test voltage is a sine wave, the amplitude of voltage fluctuation is 3.3V +/-0.5V, and the frequency of voltage fluctuation is between 100HZ and 100 KHZ. Referring to FIG. 2A, a graph of a test voltage waveform for a power module is shown, where the test voltage is shown to have a voltage ripple amplitude of 3.3V + -0.5V and a voltage ripple frequency of 500 Hz. As an alternative to the waveform shown in fig. 2A or a succeeding waveform after a certain period of time, the voltage amplitude of the test voltage is changed, as shown in fig. 2B, which shows a test voltage waveform diagram of the power module, in which the test voltage is shown to have a voltage fluctuation amplitude of 3.3V ± 0.3V and a voltage fluctuation frequency of 500 HZ. Similar to fig. 2B, referring to fig. 2C, a test voltage waveform diagram of the power module is shown, in which the test voltage fluctuation amplitude is 3.3V ± 0.1V and the voltage fluctuation frequency is 500 HZ.
As another example, the test voltage is a triangular wave, the amplitude of the voltage fluctuation is 3.3V ± 0.5V, the frequency of the voltage fluctuation is between 100HZ and 100KHZ, and fig. 3A, 3B and 3C show graphs of test voltage waveforms of different voltage amplitudes under the triangular wave test voltage, respectively, similar to fig. 2A, 2B and 2C.
During the period of the output of the fluctuation voltage of the example, the controller controls the flash module of the chip to be tested to respectively perform erasing/writing/reading operations, and after each test, the comparison result is used for comparing whether the test data is consistent with the source data. The testing frequency can be freely set, the testing is automatically stopped after the set value is reached, the controller counts the testing result and displays the result through the display, and the reliability of the flash module of the chip to be tested in the testing mode is verified.
The above examples are only for illustrating the content of the present embodiment, the present embodiment is not limited to the above examples, and the waveform selection of the test voltage may have various types, for example, a sine wave with a continuously changing amplitude or frequency, a combined waveform of a partial sine wave and a partial triangular wave, other types of waveforms, and the like.
Example two:
the second embodiment is another specific implementation of the test mode, and is different from the first embodiment in the test mode, specifically, the power module outputs a test voltage with a steep rise and a steep fall to the chip to be tested under the control of the controller.
As an example, the test voltage is a square wave, the amplitude of voltage fluctuation is 0.5V-3.3V, and the frequency of voltage fluctuation is between 1HZ and 100 HZ. Referring to FIG. 4A, a graph of a test voltage waveform for a power module is shown, where the test voltage shown has a voltage fluctuation amplitude of 1.5V-3.3V and a voltage fluctuation frequency of 50 HZ. As an alternative to the waveform shown in fig. 4A or a succeeding waveform after a certain period of time, the voltage amplitude of the test voltage is changed, as shown in fig. 4B, which shows a test voltage waveform diagram of the power module, in which the test voltage has a fluctuation amplitude of 0.5V to 3.3V and a voltage fluctuation frequency of 50 HZ. Similar to fig. 4B, referring to fig. 4C, a test voltage waveform diagram of the power module is shown, in which the test voltage fluctuation amplitude is 1.0V-3.3V and the voltage fluctuation frequency is 50 HZ.
Similar to the embodiment, during the period of the steep-rise and steep-fall voltage output of the above example, the controller controls the flash module of the chip to be tested to perform erase/write/read operations respectively, and after each test, it is compared whether the test data is consistent with the source data. The testing frequency can be freely set, the testing is automatically stopped after the set value is reached, the controller counts the testing result and displays the result through the display, and the reliability of the flash module of the chip to be tested in the testing mode is verified.
Similar to the embodiment, the above example is only used to illustrate the content of the embodiment in the embodiment, the embodiment is not limited to the above example, and the waveform selection of the test voltage may have various types, such as a steep rising and falling triangular wave with a constantly changing amplitude or frequency, a combined waveform of a partial square wave and a partial triangular wave, other types of waveforms, and the like.
Example three:
as another specific implementation of the test mode, the third embodiment is different from the first and second embodiments in that the test mode is different, specifically, the power module outputs intermittently interrupted test voltage to the chip to be tested under the control of the controller.
As an example, the test voltage is a discontinuous wave, the voltage fluctuation amplitude is 0V-3.3V, and the voltage fluctuation frequency is between 0.1HZ and 1 HZ. Referring to fig. 5, which shows a test voltage waveform diagram of a power module, the voltage fluctuation amplitude of the test voltage shown in the diagram is 0V-3.3V, the voltage fluctuation frequency is 0.5HZ, the voltage is suddenly powered off and reduced to 0V after lasting for a period of time from 3.3V, and is powered on again after delaying for a period of time, and the specific duration and delay time can be set according to the test requirements, which is not limited herein.
Similar to the first and second embodiments, during the intermittent interrupted fluctuating voltage output period, the controller controls the flash modules of the chips to be tested to perform erase/write/read operations respectively, and after each test, compares whether the test data is consistent with the source data. The testing frequency can be freely set, the testing is automatically stopped after the set value is reached, the controller counts the testing result and displays the result through the display, and the reliability of the flash module of the chip to be tested in the testing mode is verified.
Similar to the first and second embodiments, the above examples are only for illustrating the content of the present embodiment, the present embodiment is not limited to the above examples, and the waveform selection of the test voltage may have various types, such as a discontinuous wave with a continuously changing amplitude or frequency, a combined waveform of the discontinuous wave and a partial triangular wave, other types of waveforms, and the like.
Example four:
fourth embodiment is to adjust the number of the test stations to be multiple on the basis of the first, second, and third embodiments, as shown in fig. 6, the power module respectively supplies power to the multiple test stations, and the voltage output to the chip to be tested is changed according to different test modes under the control of the controller, where the specific test mode and voltage change are as described in the first, second, and third embodiments, and this embodiment is not described in detail herein.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. The device for testing the reliability of the memory is characterized by comprising a controller, a power supply module and a test station,
the test station is used for placing a chip to be tested;
the power supply module is connected with the chip to be tested and the controller and respectively supplies power to the controller and the chip to be tested;
the controller is respectively connected with the chip to be tested and the power supply module and controls the test voltage output of the power supply module and the flash operation of the chip to be tested.
2. The test apparatus of claim 1, wherein the test voltage is different according to a test mode.
3. The test apparatus of claim 2, wherein the test modes include a surge test, a steep rise and fall test, and an intermittent power outage test.
4. A test apparatus according to claim 3, wherein the test voltage under the ripple test is a sine wave or/and a triangle wave.
5. The test apparatus of claim 3, wherein the test voltage under steep ramp-down test is a square wave.
6. The test apparatus as claimed in claim 3, wherein the test voltage under the intermittent power-off test is a discontinuous wave.
7. The test apparatus of any one of claims 1-6, wherein the test station has a plurality.
8. The test apparatus of claim 7, further comprising a display for displaying a test result of the chip under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020271990.3U CN211087930U (en) | 2020-03-06 | 2020-03-06 | Memory reliability testing device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020271990.3U CN211087930U (en) | 2020-03-06 | 2020-03-06 | Memory reliability testing device |
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| CN211087930U true CN211087930U (en) | 2020-07-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542210A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | High-speed flash limit read-write speed testing device |
| CN112599179A (en) * | 2020-12-31 | 2021-04-02 | 深圳市芯天下技术有限公司 | Parallel flash life testing device |
-
2020
- 2020-03-06 CN CN202020271990.3U patent/CN211087930U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542210A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | High-speed flash limit read-write speed testing device |
| CN112599179A (en) * | 2020-12-31 | 2021-04-02 | 深圳市芯天下技术有限公司 | Parallel flash life testing device |
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