CN211046875U

CN211046875U - Signal locking circuit

Info

Publication number: CN211046875U
Application number: CN201922436637.6U
Authority: CN
Inventors: 张小红; 吴梦璞
Original assignee: Xi'an Fucheng Defence Technology Co ltd
Current assignee: Xi'an Fucheng Defence Technology Co ltd
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-07-17
Anticipated expiration: 2029-12-30

Abstract

The utility model relates to a signal locking circuit, including the modulation signal input end, the carrier input end that obtains of extraction, locking signal output end, logic gate, eighth resistance R8, fourth electric capacity C4, fifth resistance R5, ninth resistance R9, comparator and eleventh resistance R11; the modulation signal input end and the extracted carrier input end are respectively connected with an eighth resistor R8 through a logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected into the comparator; the power supply input end of the comparator is connected to the comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end is connected to the comparator; the output end of the comparator is respectively connected with the eleventh resistor R11 and the locking signal output end. The utility model has the advantages of simple structure, easily locking the destination signal and can regard as a direct instruction number to give the system in save system and judge the time to data.

Description

Signal locking circuit

Technical Field

The utility model belongs to the electricity field relates to a signal locking circuit.

Background

Modem is an important means of achieving modern communications. In order for a digital signal to be transmitted in a band pass channel, a carrier wave must be modulated with the digital baseband signal to match the signal to the channel characteristics. Therefore, the method has important significance in researching the digital communication modulation and demodulation theory and providing an effective modulation mode. A high transmission rate and a low error rate are necessary to ensure efficient transmission of information in a transmission system. Differential phase shift keying (DPSK for short) is the most common modulation scheme in data communication, and has the advantages of simplicity and easy implementation. And due to the unique modulation mode, the phenomenon of 'falling pi' in the PSK modulation is avoided. Demodulation is the inverse of modulation, and is particularly important in order to extract the signal from the carrier as undistorted as possible. There are two commonly used DPSK demodulation methods, i.e., differential coherent demodulation and coherent demodulation. In a transmission signal, a 2PSK signal has a better error rate performance than 2ASK and 2FSK signals, but there is phase uncertainty in a 2PSK signal transmission system and it will cause the received symbols "0" and "1" to be reversed, resulting in an error. In order to ensure the advantages of 2PSK and not generate bit errors, the 2PSK system is improved into binary differential phase shift keying (2 DPSK). The DPSK demodulation method includes two differential coherent demodulation methods and a coherent demodulation method. The coherent demodulation method is mainly to multiply the original signal and the carrier wave, remove the carrier wave and process the signal. Differential coherent demodulation needs to delay one path of signal, but sometimes some hardware circuits cannot accurately delay one bit of code element, which may cause errors. And the DPSK signal is demodulated by directly utilizing software such as an FPGA (field programmable gate array) and the like, but when the DPSK signal is applied to a circuit, the DPSK signal is required to correspond to a front system and a rear system, and the conversion is complex. However, the input DPSK signal is correctly demodulated and then does not have a locked indication signal, which cannot save the time for the system to judge the data. The existing signal locking circuit is complex in structure and difficult to realize.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem existing in the background art, the utility model provides a simple structure, easily lock the purpose signal and can give the system in as a direct instruction number save the system and carry out the signal locking circuit who judges the time to the data.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a signal lock circuit, characterized by: the signal locking circuit comprises a modulation signal input end, an extracted carrier input end, a locking signal output end, a logic gate, an eighth resistor R8, a fourth capacitor C4, a fifth resistor R5, a ninth resistor R9, a comparator and an eleventh resistor R11; the modulation signal input end and the extracted carrier input end are respectively connected with an eighth resistor R8 through a logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the comparator; the power supply input end of the comparator is connected to the positive input end of the comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the comparator; the output end of the comparator is respectively connected with the eleventh resistor R11 and the locking signal output end.

The frequencies of the modulated signal input terminal and the extracted carrier input terminal are the same.

The comparator is a four-way differential comparator.

The comparator is model L M339.

The logic gate is model 74HC 86.

The resistance of the eighth resistor R8 is 90K Ω; the resistance value of the ninth resistor R9 is 21K omega; the resistance value of the fifth resistor R5 is 30K omega; the eleventh resistor R11 has a resistance of 6K Ω.

The capacitance of the fourth capacitor C4 is 1000 pF.

The utility model has the advantages that:

the utility model provides a signal locking circuit, including the modulation signal input end, the carrier input end that obtains of extraction, locking signal output end, logic gate, eighth resistance R8, fourth electric capacity C4, fifth resistance R5, ninth resistance R9, comparator and eleventh resistance R11; the modulation signal input end and the extracted carrier input end are respectively connected with an eighth resistor R8 through a logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the comparator; the power supply input end of the comparator is connected to the positive input end of the comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the comparator; the output end of the comparator is respectively connected with the eleventh resistor R11 and the locking signal output end. The utility model provides a signal locking circuit is a locking instruction state, and when no data input, the locking instruction is the low level, simple structure, easily locking signal and can regard as a direct instruction number to give the system in save system and judge the time to data.

Drawings

Fig. 1 is a schematic diagram of a signal locking circuit provided by the present invention;

wherein:

1-a modulated signal input; 2-extracting the obtained carrier input end; 3-locking the signal output.

Detailed Description

Referring to fig. 1, the present invention provides a signal locking circuit, which includes a modulation signal input terminal (1), a carrier input terminal (2) obtained by extraction, a locking signal output terminal (3), a logic gate, an eighth resistor R8, a fourth capacitor C4, a fifth resistor R5, a ninth resistor R9, a comparator, and an eleventh resistor R11; the modulation signal input end (1) and the extracted carrier input end (2) are respectively connected with an eighth resistor R8 through a logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the comparator; the power supply input end of the comparator is connected to the positive input end of the comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the comparator; the output end of the comparator is respectively connected with the eleventh resistor R11 and the locking signal output end (3).

The frequencies of the modulation signal input terminal (1) and the extracted carrier input terminal (2) are the same.

The eighth resistor R8 distinguishes the level of the signal input and the level of the no signal input through the filter formed by the fourth capacitor C4, then the comparator and a reference level are used to judge the states of the signal input and the no signal input, the output is high level when the signal is present, and the output is low level when the signal is absent.

The comparator is a four-way differential comparator, the model of the comparator is L M339, the model of the logic gate is 74HC86, the resistance value of the eighth resistor R8 is 90K omega, the resistance value of the ninth resistor R9 is 21K omega, the resistance value of the fifth resistor R5 is 30K omega, the resistance value of the eleventh resistor R11 is 6K omega, and the capacitance value of the fourth capacitor C4 is 1000 pF.

The utility model adds a path of locking signal, namely when no data is input, the locking signal is low level and has no demodulation data; when data is input, the locking signal is at high level, and a demodulation signal is output.

Claims

1. A signal lock circuit, characterized by: the signal locking circuit comprises a modulation signal input end (1), an extracted carrier input end (2), a locking signal output end (3), a logic gate, an eighth resistor R8, a fourth capacitor C4, a fifth resistor R5, a ninth resistor R9, a comparator and an eleventh resistor R11; the modulation signal input end (1) and the extracted carrier input end (2) are respectively connected with an eighth resistor R8 through a logic gate; the eighth resistor R8 is grounded after passing through the fourth capacitor C4; the eighth resistor R8 is connected to the inverting input end of the comparator; the power supply input end of the comparator is connected to the positive input end of the comparator through a fifth resistor R5; one end of the ninth resistor R9 is grounded, and the other end of the ninth resistor R9 is connected to the positive input end of the comparator; the output end of the comparator is respectively connected with the eleventh resistor R11 and the locking signal output end (3).

2. The signal lock circuit of claim 1, wherein: the frequencies of the modulation signal input end (1) and the extracted carrier input end (2) are the same.

3. The signal lock circuit of claim 2, wherein: the comparator is a four-way differential comparator.

4. The signal lock circuit of claim 3, wherein the comparator has a model number of L M339.

5. The signal lock circuit of claim 1 or 2 or 3 or 4, wherein: the model number of the logic gate is 74HC 86.

6. The signal lock circuit of claim 5, wherein: the resistance value of the eighth resistor R8 is 90K omega; the resistance value of the ninth resistor R9 is 21K omega; the resistance value of the fifth resistor R5 is 30K omega; the eleventh resistor R11 has a resistance of 6K Ω.

7. The signal lock circuit of claim 6, wherein: the capacitance value of the fourth capacitor C4 is 1000 pF.