CN211046755U - PFC circuit with input power limiting function - Google Patents
PFC circuit with input power limiting function Download PDFInfo
- Publication number
- CN211046755U CN211046755U CN201921110006.9U CN201921110006U CN211046755U CN 211046755 U CN211046755 U CN 211046755U CN 201921110006 U CN201921110006 U CN 201921110006U CN 211046755 U CN211046755 U CN 211046755U
- Authority
- CN
- China
- Prior art keywords
- voltage
- factor
- pfc
- vref
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A PFC circuit with an input power limiting function comprises a PFC power circuit and a PFC control circuit, wherein a multiplier module is arranged in the PFC control circuit, two input ends of the multiplier are respectively MU L T and COM, wherein a voltage VMU L T obtained by voltage division after line voltage rectification is carried out immediately, a voltage VCOM at an output end of a differential amplifier is obtained, a signal Vcs output by the multiplier is used as a reference signal of a current comparator, the upper limit value of the voltage VCOM is Vuc, an internal reference voltage is VREF, the signal Vcs is obtained by multiplying a factor K, a factor (MP-VREF) and a factor VMU L T, the maximum value of the factor (VCOMP-VREF) is (Vuc-VREF), the factor K, the upper limit value Vuc and the internal reference voltage VREF are accurately controlled, and the maximum value of the signal Vcs is determined for a determined factor VMU L T, and the VMU L T is used for input power control of the PFC circuit.
Description
Technical Field
The utility model relates to a power control technical field especially relates to a PFC circuit of taking input power restriction function.
Background
The harm of current harmonic waves in a power grid is well known, the current harmonic waves not only influence the power supply quality of the power grid and cause electric energy waste, but also cause equipment to generate heat, increase loss, shorten the service life, even cause failure or burnout and cause great economic loss. Lighting products such as self-ballasted fluorescent lamps and electronic ballasts also generate a large amount of harmonics when used, and particularly when used over a large area, the harmfulness of the products is not insignificant.
The Chinese national standard has strict requirements on harmonic content, the Chinese national standard has different requirements on harmonic of the self-ballasted fluorescent lamp with the power of more than 25W and the self-ballasted fluorescent lamp with the power of not more than 25W, and the requirement on the self-ballasted fluorescent lamp with the power of more than 25W is much higher than that of the self-ballasted fluorescent lamp with the power of less than 25W.
The power factor of a conventional self-ballasted fluorescent lamp becomes very low due to the rich harmonic content. The Power Factor Correction (PFC) technique is an effective method for improving the Power Factor of a self-ballasted fluorescent lamp. The power factor correction circuit is divided into a passive PFC (passive PFC) circuit and an Active PFC (APFC) circuit.
The passive PFC circuit has the characteristics of simple circuit and low cost, can improve the power factor of a circuit to a certain extent, can even reach 0.95 in some cases, but has poor filtering effect, is difficult to realize the requirement of low harmonic, often influences other parameters of a system, and is generally suitable for a self-ballasting fluorescent lamp circuit below 25W.
The APFC circuit is based on a power factor controller IC, utilizes the switching of a switching device and is matched with a passive element, so that the current waveform drawn by a system from a mains supply is consistent with the voltage waveform, the current waveform distortion and the phase distortion are eliminated, a high power factor similar to 1 is obtained, and the harmonic distortion can be greatly reduced. The APFC circuit structure is far more complex than a passive PFC, a control IC is needed, a 1-level circuit is usually formed at the front end of a system independently, and the cost is higher. But since it operates at high frequencies, the inductive element is small and lightweight. With the decreasing price of PFC control ICs, APFCs have been widely used.
For self-ballasted fluorescent lamps above 25W, the power factor can be boosted by APFC techniques to improve the individual current harmonics.
For other electric devices in the power grid, such as an electric vehicle charger, an arc welding power supply, a communication power supply and the like, the input power usually reaches thousands of watts or even higher, and the devices also need to improve the power factor and reduce the current harmonic waves through the APFC technology.
APFC controllers play a key role in APFC the home and abroad representative APFC controllers are FAN7527B, L6561/L6562, NCP1601A/B, IR1150 and the like.
L6562A is PFC controller of Italian semiconductor company, FIG. 1 is taken from chip specification of L6562A, the chip specification explains in detail the working principle and using method of L6562A, the technical details about L6562A are not repeated here, FIG. 1 is APFC circuit schematic diagram using chip L6562A as controller, 50 Hz input AC power passes through fuse F1 and rectifier bridge P1, 100 Hz half-wave voltage is obtained on C1, through BOOST circuit, output voltage Vo. output voltage Vo is obtained on capacitor C6, through divider resistors R11 and R12, feedback voltage of output voltage Vo is obtained on parallel resistors R13 and R13B, and is sent to the first pin of control chip L6562A, namely the reverse input end of internal differential amplifier, INV passes through PI regulator formed by differential amplifier inside L6562A, and keeps the output voltage stable.
L6562A has a multiplier module, the multiplier has two input terminals, the first input terminal is MU L T, the input signal is voltage VMU L T obtained by voltage division after instant line voltage rectification, the second input terminal is COM, the input signal is voltage VCOM at the output terminal of the differential amplifier, usually, in steady state, VCOM is a slowly changing DC level containing certain 100 Hz AC component, the envelope of the output waveform of the multiplier is a rectified sine wave, the output signal of the multiplier is used as the reference signal of the current comparator, and the output of the current comparator is used to control the peak current of each period of MOSFET.
L6562A has a current comparator, which obtains a voltage signal via a current detection resistor (MOS switch tube source series resistor) and compares with the output signal of the multiplier to determine the turn-off time of the external MOSFET.
Fig. 2 is a diagram of the relationship between VMU L T, VCOM and Vcs of the chip L6562A. the multiplier has the relationship of Vcs ═ k (VCOMP-2.5) × VMU L T, (where x represents multiplication), and the output Vcs of the multiplier is used as the reference voltage on the current detection pin.
In the chip specification of L6562A, the multiplier parameters can be looked up, where typical values for the upper limit of VCOMP are 5.7V, 5.3V minimum, 6V maximum, 2.25V, 2.1V minimum, 2.4V maximum, where VMU L T1V, VCOMP 4V, K is 0.38, 0.32 minimum, 0.44 maximum, and VREF 2.5V maximum, and the insert of the chip specification shows that the absolute value of the relative error of VREF is less than two thousandths in the range of-20 degrees celsius to 100 degrees celsius.
The output voltage Vo is kept stable by the regulation action of the PI regulator formed by the differential amplifier inside L6562A, and the voltage VCOM at the output terminal of the differential amplifier is a result of the dynamic regulation.
If the input ac voltage changes to cause the VMU L T to change, or the output load changes to cause the output voltage Vo to change, or the factor K changes, which are all dynamically adjusted by the PI regulator, so that after the dynamic process is over, a stable VCOMP is finally obtained, for example, the input ac voltage is unchanged, the output load is unchanged, VREF is 2.5V, and the factor K slowly changes from the initial 0.3 to 0.4 after the PFC operates for 100 minutes, then if the initial VCOMP is 3.3V, the initial Vcs is K (VCOMP-2.5) VMU L T, and the VCOMP after the PFC operates for 100 minutes is 3.1V.
L6562A adopts critical conduction mode control. L6562A has a current comparator inside, the current comparator obtains a voltage signal through a current detection resistor (MOS switch tube source electrode series resistor) and compares the voltage signal with the output signal of the multiplier to determine the off time of the external MOSFET, and L6562A uses the externally provided ZCD signal to determine the on time of the external MOSFET.
The relationship between the switching state of the MOSFET and the peak value and the average value of the inductor current is shown in fig. 3, where the peak value of the inductor current is twice the average value of the inductor current, and the peak value of the inductor current is determined by the output signal Vcs of the multiplier and the source series resistance of the MOS switch tube.
A small part of current rectified by the input alternating current flows through a filter capacitor C1 behind a rectifier bridge, and a large part of current flows through a PFC inductor; the voltage of the filter capacitor C1 has a phase difference of 90 degrees with the current, and the C1 only stores energy and consumes little energy; therefore, if the losses of the input rectifier bridge, the input filter and other devices are not considered for the moment, the input power of the PFC is obtained by multiplying the rectified voltage of the input ac by the average value of the inductor current.
I.e. the input ac voltage.
In fig. 1, VMU L T is a voltage obtained by dividing an instantaneous line voltage after rectification, and Vinp is a voltage obtained by rectifying the instantaneous line voltage, then VMU L T may be Kv Vinp, Kv is related to voltage dividing resistors R1, R2, and R3, Kv is R3/(R1+ R2+ R3), an average value of an inductance current may be Ki Vcs, Ki is related to MOS switch source series resistors R9 and R10, and Ki is 0.5 (R9+ R10)/(R9R 10).
The input power of the PFC can be expressed as:
Pin＝Vinp*Ki*Vcs (1)
due to the fact that
Vcs＝K*(VCOMP-2.5)*VMULT (2)
Therefore, it is not only easy to use
Pin＝Kv*Ki*K*(VCOMP-2.5)*Vinp*Vinp (3)
Or
Pin＝Ki*K*(VCOMP-2.5)*VMULT*VMULT/Kv (4)
The general high-power supply is generally divided into two stages, wherein the front stage is a PFC circuit, the rear stage is a DC/DC converter, such as an LL C converter, the DC/DC converter of the rear stage is generally provided with an output short-circuit protection circuit and an output power limiting circuit, so that the DC/DC converter is ensured not to be overloaded, and as the DC/DC converter is connected to the PFC circuit, the output power of the PFC circuit is not overloaded as long as the DC/DC converter is ensured not to be overloaded, so that the input power of the PFC circuit is limited.
Consider the following example: the input alternating current of the PFC circuit is 50 Hz, the voltage is changed from 150V to 300V, the output power is 300W, and the loss is not considered for the moment, so that the current of the input alternating current is 2A when the voltage is 150V, and is 1A when the voltage is 300V.
Then, the voltage endurance of the power device in the PFC circuit, including the input end fuse, the rectifier bridge, the EMI filter, etc., is designed according to the input ac voltage of 300V, and the current of the power device is designed according to the input ac current of 2A; and adding a certain margin according to the characteristics of different devices after the design is finished, and finally selecting the model of the device.
At this time, if the input power is not limited, when the input voltage is reduced to 100V, the current of the input ac is 3A, and the output power of the PFC is guaranteed to be 300W. This may cause damage to the input fuses, rectifier bridges, EMI filters, etc. due to overcurrent.
In order to prevent the input current from rising due to the drop of the input voltage, various methods may be employed.
For example, when the input voltage decreases to a certain value Vin-low, a hysteresis comparator is triggered to turn off the PFC circuit and the DC/DC converter behind the PFC circuit until the input voltage increases to another value Vin-high, and the hysteresis comparator turns on the PFC circuit and the DC/DC converter behind the PFC circuit again.
The problem with this approach is that it is not guaranteed that the circuit will work properly when the input voltage varies between Vin-low and Vin-high.
In another method, when the input voltage is reduced to a certain value Vin-low and further reduced, the control circuit generates a proportional signal to reduce the output power of the following DC/DC converter according to the proportional relation of the input voltage, thereby reducing the input power and the input current of the PFC.
The problem with this approach is that the design of the control circuit is complex, and when the DC/DC converter is electrically isolated, it involves accurate isolated transmission of the control signal.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a PFC circuit of taking input power restriction function to solve the input current control problem of PFC circuit under the low input voltage condition among the prior art, technical scheme is as follows:
a PFC circuit with an input power limiting function comprises a PFC power circuit and a PFC control circuit, wherein a multiplier module is arranged in the PFC control circuit, two input ends of the multiplier are respectively MU L T and COM, wherein a voltage VMU L T obtained by voltage division after line voltage rectification is carried out immediately, a voltage VCOM at an output end of a differential amplifier is obtained, a signal Vcs output by the multiplier is used as a reference signal of a current comparator, the upper limit value of the voltage VCOM is Vuc, an internal reference voltage is VREF, the signal Vcs is obtained by multiplying a factor K, a factor (MP-VREF) and a factor VMU L T, the maximum value of the factor (VCOMP-VREF) is (Vuc-VREF), the factor K, the upper limit value Vuc and the internal reference voltage VREF are accurately controlled, and the maximum value of the signal Vcs is determined for a determined factor VMU L T.
VMU L T is used for input power control of the PFC circuit.
Preferably, the factor K is equal to 0.5, the absolute value of the relative error of the factor K being less than one hundredth; preferably, the upper limit value Vuc is 5.5V, and the absolute value of the relative error of the upper limit value Vuc is less than one hundredth; preferably, the internal reference voltage VREF is 2.5V, and the absolute value of the relative error of the internal reference voltage VREF is less than one hundredth.
VMU L T may be expressed as Kv Vinp, inductor current average may be expressed Ki Vcs, internal reference voltage is VREF, equation 3 is rewritten as:
Pin＝Kv*Ki*K*(VCOMP-VREF)*Vinp*Vinp (5)
Pin＝Ki*K*(VCOMP-VREF)*VMULT*VMULT/Kv (6)
the maximum value of the input power can be expressed as follows:
Pin-max＝Kv*Ki*K*(Vuc-VREF)*Vinp*Vinp (7)
Pin-max＝Ki*K*(Vuc-VREF)*VMULT*VMULT/Kv (8)
from the formula 7, the factor K, the upper limit value Vuc and the internal reference voltage VREF are accurately controlled, and since the parameters Kv and Ki are fixed values, the maximum value of the corresponding input power is available for any voltage Vinp rectified from the instant line voltage, that is, for any ac input voltage.
Drawings
Fig. 1 is a schematic diagram of an APFC circuit using a chip L6562A as a controller.
FIG. 2 is a diagram of the relationship between VMU L T, VCOM and Vcs of chip L6562A.
Fig. 3 is a plot of the switching state of a MOSFET versus the peak and average values of the inductor current.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples.
Examples
Fig. 1 is a schematic diagram of an APFC circuit using a chip L6562A as a controller, fig. 2 is a graph of VMU L T, VCOM and Vcs of a chip L6562A, and fig. 3 is a graph of the switching state of a MOSFET versus the peak and average values of the inductor current.
Consider still an example of this: the input alternating current of the PFC circuit is 50 Hz, the voltage is changed from 150V to 300V, the output power is 300W, the loss is not considered for the moment, the input power and the output power of the PFC circuit are equal, and then the current of the input alternating current is 2A when the voltage is 150V, and is 1A when the voltage is 300V.
At this time, if the input power is not limited, when the input voltage is reduced to 100V, the current of the input ac is 3A, and the output power of the PFC is guaranteed to be 300W. This may cause damage to the input fuses, rectifier bridges, EMI filters, etc. due to overcurrent.
Consider now using equation 7 to limit the input power at low input ac voltages. When the maximum input power is set to 300W at an input voltage of 150V without considering the loss of the PFC circuit, equation 7 shows that
300＝Kv*Ki*K*(Vuc-VREF)*150*150 (9)
Preferably, K is 0.5, Vuc is 5.5V, VREF is 2.5V, then
300＝Kv*Ki*1.5*150*150
Selecting MOS switch tube source electrode series resistance to make Ki equal to 6, then
Kv＝0.00148
In fig. 1, if both R1 and R2 are selected to be 1M Ω, then R3 is 7.4K Ω.
Thus, when the ac input voltage is 150V under the conditions that the parameter K is 0.5, Vuc is 5.5V, VREF is 2.5V, Ki is 6, and Kv is 0.00148, the input power of the PFC is 300W; when the input ac voltage is less than 150V, since the output voltage VCOM of the differential amplifier has reached the upper limit value and cannot be increased, according to equation 7, the maximum value of the input power is less than 300W, and is proportional to the square of the input ac voltage, and the maximum value of the input power is attenuated rapidly along with the decrease of the input ac voltage; when the input ac voltage is greater than 150V, the output voltage VCOM of the differential amplifier is decreased, so as to keep the output power of the PFC at 300W.
This realizes that the control chip of PFC controls the input power by detecting the voltage of MU L T pin.
In the existing PFC control chip, parameters such as a factor K, an upper limit value Vuc, an internal reference voltage VREF and the like are related to the design and production process of the chip, and generally, the parameters have wide variation range and low precision and are not suitable for PFC power control under low input voltage.
The PFC circuit with the input power limiting function comprises a PFC power circuit and a PFC control circuit, wherein a multiplier module is arranged in the PFC control circuit, two input ends of a multiplier are respectively MU L T and COM, a voltage VMU L T obtained by voltage division after line voltage rectification is carried out immediately, a voltage VCOM at an output end of a differential amplifier is obtained, a signal Vcs output by the multiplier is used as a reference signal of a current comparator, the upper limit value of the voltage VCOM is Vuc, an internal reference voltage is VREF, the signal Vcs is a factor K, the factor (VCOMP-VREF) and the factor VMU L T are multiplied to obtain, the maximum value of the factor (VCOMP-VREF) is (Vuc-VREF), the factor K, the upper limit value Vuc and the internal reference voltage VREF are accurately controlled, and the maximum value of the signal Vcs is determined for a determined factor VMU L T.
Preferably, the factor K is equal to 0.5, the absolute value of the relative error of the factor K being less than one hundredth; preferably, the upper limit value Vuc is 5.5V, and the absolute value of the relative error of the upper limit value Vuc is less than one hundredth; preferably, the internal reference voltage VREF is 2.5V, and the absolute value of the relative error of the internal reference voltage VREF is less than one hundredth.
By selecting proper parameters Kv and Ki, the purpose that the VMU L T is used for controlling the input power of the PFC circuit can be achieved.
To sum up, the utility model has the characteristics of rational in infrastructure, stable performance.
The preferred embodiments of the present invention are described in the specification, rather than in the limitation of the present invention, and all modifications and variations that may occur to those skilled in the art based on the teachings herein are intended to be included within the scope of the present invention.
Claims (2)
1. A PFC circuit with an input power limiting function comprises a PFC power circuit and a PFC control circuit, and is characterized in that a multiplier module is arranged in the PFC control circuit, two input ends of a multiplier are respectively MU L T and COM, wherein voltage VMU L T obtained by voltage division after line voltage rectification is carried out instantly, voltage VCOM at an output end of a differential amplifier is obtained by multiplying a signal Vcs output by the multiplier as a reference signal of a current comparator, the upper limit value of the voltage VCOM is Vuc, internal reference voltage is VREF, the signal Vcs is factor K, factor (VCOMP-VREF) and factor VMU L T, the maximum value of the factor (VCOMP-VREF) is (Vuc-VREF), the factor K, the upper limit value Vuc and the internal reference voltage VREF are accurately controlled, and the maximum value of the signal Vcs is determined for a determined factor VMU L T.
2. The PFC circuit of claim 1, wherein the VMU L T is configured to control input power of the PFC circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921110006.9U CN211046755U (en) | 2019-07-16 | 2019-07-16 | PFC circuit with input power limiting function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921110006.9U CN211046755U (en) | 2019-07-16 | 2019-07-16 | PFC circuit with input power limiting function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211046755U true CN211046755U (en) | 2020-07-17 |
Family
ID=71538205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921110006.9U Active CN211046755U (en) | 2019-07-16 | 2019-07-16 | PFC circuit with input power limiting function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211046755U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110380603A (en) * | 2019-07-16 | 2019-10-25 | 南京博德新能源技术有限公司 | A kind of pfc circuit with input power limitation function |
-
2019
- 2019-07-16 CN CN201921110006.9U patent/CN211046755U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110380603A (en) * | 2019-07-16 | 2019-10-25 | 南京博德新能源技术有限公司 | A kind of pfc circuit with input power limitation function |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102695341B (en) | LED drive power supply applicable to electronic transformer | |
| US7952293B2 (en) | Power factor correction and driver circuits | |
| US20160352210A1 (en) | Green power converter | |
| CN103155714B (en) | Led driving chip and circuit with power compensation | |
| CN102612224B (en) | A kind of MR16LED lamp drive circuit, driving method and apply its MR16LED lamp illuminating system | |
| CN106787675B (en) | Resonant converter with power factor correction function and controller thereof | |
| CN103987178A (en) | LED driving method and circuit and output current ripple controller of LED driving circuit | |
| CN101868078A (en) | Single-power level LED constant current driving device with high power factor | |
| CN102594175B (en) | Alternating current-to-direct current circuit | |
| WO2019136567A1 (en) | Power converter controlled capacitor circuits and methods | |
| CN103716952B (en) | A kind of LED switch power supply and control method thereof | |
| CN203851350U (en) | LED driving circuit and output current ripple controller thereof | |
| CN106300925B (en) | Drive control circuit, method and its system of AC-DC circuits | |
| CN211046755U (en) | PFC circuit with input power limiting function | |
| CN107332438B (en) | Power factor correction method based on double-inductor double-voltage direct current output circuit | |
| CN104124862A (en) | High-PFC constant current control device without loop compensation and voltage converter | |
| WO2018024035A1 (en) | Indicating circuit for switching power supply, and using method therefor | |
| CN104753335A (en) | Quadratic form Buck power factor correction converter | |
| CN202750021U (en) | Converter for converting alternating current into direct current | |
| CN105101539A (en) | Light-emitting diode (LED) constant current driving circuit | |
| JP2019536405A (en) | AC / DC converter with power factor correction | |
| CN211046756U (en) | PFC circuit | |
| KR20130084199A (en) | Single power stage power factor correction circuit | |
| CN202663316U (en) | Circuit with three common-grounded power supplies of high voltage alternating current, low voltage alternating current and low voltage direct current | |
| CN205546103U (en) | Flyback drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |