CN211018798U - Short circuit isolation circuit suitable for loop bus - Google Patents

Abstract

The utility model relates to a short circuit isolating circuit suitable for loop bus, it includes NMOS pipe NM1, NMOS pipe NM 1's grid terminal is connected with resistance R1's one end and the output of phase inverter, NMOS pipe NM 1's first end is connected with resistance R2's one end, NMOS pipe NM 1's second end is connected with resistance R3's one end, resistance R2's the other end, resistance R1's the other end is connected with the inverting terminal of comparator, resistance R3's the other end is connected with the homophase end of comparator and load circuit's power VCC end, and the power end of comparator, the power end of phase inverter all are connected with load circuit's power VCC end; the other end of the resistor R1, the other end of the resistor R2 and the inverting terminal of the comparator are all connected with a power line VIN of the loop bus, and the grounding end of the comparator, the grounding end of the inverter and the grounding end of the load circuit are all connected with a grounding line GND of the loop bus; the utility model discloses with the isolation of loop bus when can effectively realize the load short circuit, improve stability and reliability to loop bus protection.

Description

Short circuit isolation circuit suitable for loop bus

Technical Field

The utility model relates to a short circuit isolation circuit, especially a short circuit isolation circuit suitable for loop bus belongs to the technical field that the short circuit was kept apart.

Background

Loop buses are commonly used in two-bus electrical fire monitoring systems. When the device on the bus has a short-circuit fault, if the fault device is not isolated from the bus, the normal operation of other devices on the loop bus will be affected, and even the system is broken down.

Therefore, it is necessary to connect with devices on the bus through the short-circuit protector. However, the conventional short-circuit protector is connected with a bus by a relay, so that the connection and disconnection between bus equipment and a loop bus are controlled. The short-circuit protection device is mechanical compared with the on-off mode of a bus, and when the inside of a relay is aged, the on-off fault of a circuit is easily caused, so that the reliability of equipment is greatly reduced; moreover, the on-off mode is easy to generate electric sparks and is not suitable for some occasions.

Disclosure of Invention

The utility model aims at overcoming the not enough of existence among the prior art, providing a short circuit isolation circuit suitable for loop bus, its compact structure, with the isolation of loop bus when can effectively realize the load short circuit, improve stability and the reliability to loop bus protection.

According to the technical scheme provided by the utility model, short circuit isolation circuit suitable for loop bus, including NMOS pipe NM1, NMOS pipe NM 1's grid terminal is connected with resistance R1's one end and the output of phase inverter, NMOS pipe NM 1's first end is connected with resistance R2's one end, NMOS pipe NM 1's second end is connected with resistance R3's one end, resistance R2's the other end, resistance R1's the other end are connected with the inverting terminal of comparator, resistance R3's the other end is connected with the homophase end of comparator and load circuit's power VCC end, and the power end of comparator, the power end of phase inverter all are connected with load circuit's power VCC end; the other end of the resistor R1, the other end of the resistor R2 and the inverting terminal of the comparator are all connected with a power line VIN of the loop bus, and the grounding end of the comparator, the grounding end of the inverter and the grounding end of the load circuit are all connected with a grounding line GND of the loop bus;

when the voltage of the power line VIN is higher than the turn-on voltage of the NMOS transistor NM1, the NMOS transistor NM1 can be in a turn-on state, the power line VIN can charge the VCC terminal of the power supply through the NMOS transistor NM1, and after the VCC terminal of the load circuit is charged, the comparator and the inverter can be in a working state;

after the comparator and the phase inverter are in working states, the voltage of the power line VIN is compared with the voltage of the power VCC end through the comparator, when the voltage of the power line VIN is greater than the voltage of the power VCC end, the NMOS tube NM1 keeps in a conducting state, and when the voltage of the power line VIN is lower than the voltage of the power VCC end, the NMOS tube NM1 can be in a switching-off state through the comparator and the phase inverter;

when the load circuit is short-circuited, the NMOS transistor NM1 can be turned off by the cooperation of the inverter and the NMOS transistor NM1, so as to turn off the path of the power supply line VIN to the ground through the NMOS transistor NM 1.

The source-drain selection circuit is matched with the NMOS tube NM1 and is connected with the first end of the NMOS tube NM1 and the second end of the NMOS tube NM 1;

when the voltage of the power line VIN is higher than the power source VCC terminal, the first terminal of the NMOS transistor NM1 can be selected as the drain terminal by the source-drain selection circuit, and the second terminal of the NMOS transistor NM1 can be selected as the source terminal by the source-drain selection circuit;

when the voltage of the power line VIN is lower than the power source VCC terminal, the first terminal of the NMOS transistor NM1 can be selected as the source terminal by the source-drain selection circuit, and the second terminal of the NMOS transistor NM1 can be selected as the drain terminal by the source-drain selection circuit.

The source-drain selection circuit comprises a diode D1 and a diode D2, wherein the anode end of the diode D1 is connected with the anode end of the diode D2 and the substrate of an NMOS tube NM1, the cathode end of the diode D1 is connected with the first end of the NMOS tube NM1, and the cathode end of the diode D2 is connected with the second end of the NMOS tube NM 2.

The comparator comprises a resistor R4, a resistor R5, an NMOS tube NM2 and an NMOS tube NM3, wherein one end of the resistor R4 is connected with the other end of the resistor R3 and a power supply VCC end, the other end of the resistor R4 is connected with the gate end of the NMOS tube NM3, one end of the resistor R5 is connected with a power supply line VIN, the other end of the resistor R1 and the other end of the resistor R2, and the other end of the resistor R5 is connected with the gate end of the NMOS tube NM 2;

the substrate of the NMOS tube NM2 and the substrate of the NMOS tube NN3 are both connected with the ground wire GND; the source terminal of the NMOS tube NM2 and the source terminal of the NMOS tube NM3 are both connected with the drain terminal of the NMOS tube NM5, the gate terminal of the NMOS tube NM5 is connected with the gate terminal of the NMOS tube NM4, the gate terminal of the NMOS tube NM6 and the drain terminal of the NMOS tube NM4, and the source terminal of the NMOS tube NM4, the source terminal of the NMOS tube NM5 and the source terminal of the NMOS tube NM6 are all connected with the ground wire GND;

the drain terminal of NMOS transistor NM2 is connected with the drain terminal of PMOS transistor PM3 and the gate terminal of PMOS transistor PM4, the drain terminal of NMOS transistor NM3 is connected with the gate terminal of PMOS transistor PM3, the drain terminal of PMOS transistor PM4 and the gate terminal of PMOS transistor PM5, and the source terminal of PMOS transistor PM3, the source terminal of PMOS transistor PM4 and the source terminal of PMOS transistor PM5 are all connected with power VCC.

The transistor also comprises a PMOS transistor PM1 and a PMOS transistor PM2, wherein a source terminal of the PMOS transistor PM1 and a source terminal of the PMOS transistor PM2 are both connected with a VCC terminal, a gate terminal of the PMOS transistor PM1 is connected with a drain terminal of the PMOS transistor PM1, a drain terminal of the NMOS transistor NM2, a drain terminal of the PMOS transistor PM3 and a gate terminal of the PMOS transistor PM4, and a gate terminal of the PMOS transistor PM2 is connected with a drain terminal of the PMOS transistor PM2, a gate terminal of the PMOS transistor PM3, a drain terminal of the PMOS transistor PM4 and a source terminal of the PMOS transistor PM 5.

The phase inverter comprises a PMOS tube PM6 and an NMOS tube NM7, the grid end of the PMOS tube PM6 and the grid end of the NMOS tube NM7 are both connected with the drain end of the PMOS tube PM5 and the drain end of the NMOS tube NM6, the source end of the PMOS tube PM6 is connected with a power supply VCC end, and the drain end of the PMOS tube PM6 is connected with the drain end of the NMOS tube NM7 and the grid end of the NMOS tube NM 1; the source terminal of the NMOS transistor NM7 is grounded.

A load capacitor CAP is also included in parallel with the load circuit.

The utility model has the advantages that: when the voltage of the power line VIN is higher than the turn-on voltage of the NMOS transistor NM1, the NMOS transistor NM1 can be in a turn-on state, the power line VIN can charge the VCC terminal of the power supply through the NMOS transistor NM1, and after the VCC terminal of the load circuit is charged, the comparator and the inverter can be in a working state;

after the comparator and the phase inverter are in working states, the voltage of the power line VIN is compared with the voltage of the power VCC end through the comparator, when the voltage of the power line VIN is greater than the voltage of the power VCC end, the NMOS tube NM1 keeps in a conducting state, and when the voltage of the power line VIN is lower than the voltage of the power VCC end, the NMOS tube NM1 can be in a switching-off state through the comparator and the phase inverter; when the load circuit is short-circuited, the NMOS tube NM1 can be in a turn-off state through the matching of the phase inverter and the NMOS tube NM1, so that a path from a power line VIN to the ground is formed through the NMOS tube NM1 in a turn-off state, the isolation from a loop bus can be effectively realized when the load is short-circuited, and the stability and the reliability of loop bus protection are improved.

Drawings

Fig. 1 is a system block diagram of the present invention.

Fig. 2 is a schematic circuit diagram of the short circuit isolation circuit of the present invention.

Reference description: 1-controller, 2-loop bus, 3-short circuit isolation circuit and 4-load circuit.

Detailed Description

The invention is further described with reference to the following specific drawings and examples.

As shown in fig. 1 and 2: in order to effectively realize the isolation of the load short circuit with the loop bus 2 and improve the stability and reliability of the protection of the loop bus 2, the short circuit isolation circuit 3 of the utility model comprises an NMOS tube NM1, the grid terminal of the NMOS tube NM1 is connected with one end of a resistor R1 and the output end of a phase inverter, the first end of the NMOS tube NM1 is connected with one end of a resistor R2, the second end of the NMOS tube NM1 is connected with one end of a resistor R3, the other end of the resistor R2 and the other end of the resistor R1 are connected with the inverting end of a comparator, the other end of the resistor R3 is connected with the inverting end of the comparator and the power VCC end of the load circuit 4, and the power ends of the comparator and the phase inverter are connected with the power VCC end of the load circuit 4; the other end of the resistor R1, the other end of the resistor R2 and the inverting terminal of the comparator are all connected with a power line VIN of the loop bus 2, and the grounding end of the comparator, the grounding end of the inverter and the grounding end of the load circuit 4 are all connected with a grounding line GND of the loop bus;

when the voltage of the power line VIN is higher than the turn-on voltage of the NMOS transistor NM1, the NMOS transistor NM1 can be in a turn-on state, the power line VIN can charge the VCC terminal of the power supply through the NMOS transistor NM1, and after the VCC terminal of the load circuit is charged, the comparator and the inverter can be in a working state;

after the comparator and the phase inverter are in working states, the voltage of the power line VIN is compared with the voltage of the power VCC end through the comparator, when the voltage of the power line VIN is greater than the voltage of the power VCC end, the NMOS tube NM1 keeps in a conducting state, and when the voltage of the power line VIN is lower than the voltage of the power VCC end, the NMOS tube NM1 can be in a switching-off state through the comparator and the phase inverter;

when the load circuit 4 is short-circuited, the NMOS transistor NM1 can be turned off by the cooperation of the inverter and the NMOS transistor NM1, so as to turn off the path of the power supply line VIN to the ground through the NMOS transistor NM 1.

Specifically, the loop bus 2 includes a power line VIN and a ground line GND, the controller 1 is disposed on the loop bus 2, the load circuit 4 is connected to the loop bus 2 through the short-circuit isolation circuit 3, and the process of supplying power to the load circuit 4 by the controller 1, the loop bus 2, and the short-circuit isolation circuit 3 in a specific matching manner is consistent with the prior art, and is known to those skilled in the art specifically, and is not described herein again. Typically, a load capacitance CAP is also included in parallel with the load circuit 4.

In the embodiment of the present invention, the short circuit isolation circuit 3 can be integrated by using an integrated circuit, or the short circuit isolation circuit 3 can also be obtained by using a separate device, and can be specifically selected according to actual requirements, and is not repeated here. Fig. 2 shows a schematic diagram of a specific implementation of the short-circuit isolation circuit 3 integrated in an integrated circuit manner. The voltage of the power line VIN can be applied to the gate terminal of the NMOS transistor NM1 through the resistor R1, and the resistor R1 has the functions of starting and limiting current. After the voltage of the power line VIN is loaded to the gate terminal of the NMOS transistor NM1 through the resistor R1, when the turn-on condition of the NMOS transistor NM1 is satisfied, the NMOS transistor NM1 can be in a conducting state, at this time, the power line VIN can charge the VCC terminal through the conducting NMOS transistor NM1 and the resistor R3, and after the VCC terminal is charged, the voltage required for the operation of the comparator and the inverter can be provided.

The embodiment of the utility model provides an in, can know according to loop bus 2's signal characteristics, the voltage on the power cord VIN generally is the square wave, and the voltage on the power cord VIN is in the in-process that the height constantly changes. Specifically, when the voltage of the power supply line VIN is higher than the voltage of the power supply VCC terminal, the voltage of the gate terminal of the NMOS transistor NM1 is high, which is equivalent to charging the power supply VCC terminal by using the power supply line VIN; at this time, the output of the comparator is low, and the output of the inverter is high, that is, the output of the comparator and the output of the inverter does not affect the voltage state of the gate terminal of the NMOS transistor NM 1. When the voltage of the power line VIN is lower than the voltage of the power source VCC terminal, the comparator outputs a high level, and the gate terminal of the NMOS transistor NM1 is enabled to be a low level through the inverter, so that the NMOS transistor NM1 can be in an off state or an off state, and at this time, the current of the power source VCC terminal does not flow back to the power line VIN.

It can be known from the above description that the voltage of the power line VIN always has the high-low level conversion process, but in order to ensure the stability of the operation of the load circuit 4, the voltage of the power VCC terminal must be stable, so that when the voltage of the power line VIN is higher than the power VCC terminal, the power line VIN can charge the power VCC terminal through the NMOS tube NM1, and when the voltage of the power line VIN is lower than the power VCC terminal, the NMOS tube NM1 can be turned off, the voltage of the power VCC terminal can be prevented from being pulled down through the power line VIN, and the stability of the voltage of the power VCC terminal can be effectively realized.

When the load circuit 4 is short-circuited, the voltage of the power source VCC terminal approaches the level of the ground line GND. The embodiment of the utility model provides an in, cooperate through inverter and NMOS pipe NM1, can make NMOS pipe NM1 be in the off-state immediately, this moment promptly, no matter how the voltage that power cord VIN loaded NMOS pipe NM1 grid terminal through resistance R1, can both make NMOS pipe NM 1's grid terminal be the low level through the inverter, make NMOS pipe NM1 be in the off-state, when avoiding NMOS pipe NM1 to switch on, power cord VIN passes through the route that NMOS pipe NM1 formed power connection GND, realize the effective isolation with loop bus 2 when load circuit 4 short circuit, the improvement is to the stability and the reliability of loop bus 2 protection.

In the embodiment, since the voltage of the terminal VCC of the power supply is close to the level of the ground line GND when the load circuit 4 is short-circuited, the comparator and the inverter are in the off state at this time, that is, when the load circuit 4 is short-circuited, the gate terminal of the NMOS transistor NM1 is kept at the low level, which is not controlled by the output of the comparator.

The embodiment of the utility model provides an in, when the operating voltage of comparator, phase inverter was provided by power VCC end, short-circuit isolation circuit 3's circuit structure can effectively be simplified. Due to the load capacitor CAP, the voltage at the VCC terminal does not vary greatly with the variation of the VIN. When the power line VIN is larger than the power VCC terminal, even if the comparator and the inverter do not work, the charging of the power line VIN to the power VCC terminal is not affected.

Further, the transistor further comprises a source drain selection circuit matched with the NMOS transistor NM1, wherein the source drain selection circuit is connected with the first end of the NMOS transistor NM1 and the second end of the NMOS transistor NM 1;

when the voltage of the power line VIN is higher than the power source VCC terminal, the first terminal of the NMOS transistor NM1 can be selected as the drain terminal by the source-drain selection circuit, and the second terminal of the NMOS transistor NM1 can be selected as the source terminal by the source-drain selection circuit;

when the voltage of the power line VIN is lower than the power source VCC terminal, the first terminal of the NMOS transistor NM1 can be selected as the source terminal by the source-drain selection circuit, and the second terminal of the NMOS transistor NM1 can be selected as the drain terminal by the source-drain selection circuit.

The embodiment of the utility model provides an in, to NMOS pipe NM1, NMOS pipe NM 1's source end, drain end have the symmetry, can know according to the above-mentioned description that NMOS pipe NM 1's source end, drain end can be according to power cord VIN's voltage, the height of power VCC terminal voltage selects to confirm.

Specifically, when the voltage of the power line VIN is higher than the voltage of the power VCC terminal, the second terminal of the NMOS transistor NM1 is the source terminal, and according to the conduction condition of the NMOS transistor NM1, the NMOS transistor NM1 can be in the conduction state, and the power line VIN charges the power VCC terminal through the NMOS transistor NM 1. When the voltage of the VCC terminal is higher than the voltage of the power line VIN, theoretically, the power line VIN may be charged through the VCC terminal, and at this time, according to the state of the NMOS transistor NM1, the first terminal of the NMOS transistor NM1 should be selected as the source terminal. The source-drain selection circuit can improve the convenience of connecting the NMOS tube NM1 with the power line VIN and the power supply VCC end.

In specific implementation, the source-drain selection circuit comprises a diode D1 and a diode D2, an anode end of the diode D1 is connected with an anode end of the diode D2 and a substrate of the NMOS transistor NM1, a cathode end of the diode D1 is connected with a first end of the NMOS transistor NM1, and a cathode end of the diode D2 is connected with a second end of the NMOS transistor NM 2.

The embodiment of the utility model provides an in, when electric current flowed to power VCC end from power cord VIN, then think that the voltage of power cord VIN is higher than the corresponding voltage of power VCC end, see to power VCC end from power cord VIN, diode D1 is reverse terminal diode, and diode D2's forward diode that switches on, diode D2 switches on, at this moment, NMOS pipe NM 1's substrate just links to each other with one side of power VCC end, thereby decide the corresponding source end of NMOS pipe NM1 and drain end, NMOS pipe NM 1's first end is the drain end promptly, the second end of NMOS pipe NM1 is the source end.

When a current flows from the power source VCC terminal to the power source line VIN, it is considered that the voltage at the power source VCC terminal is higher than the voltage corresponding to the power source line VIN, and when viewed from the power source VCC terminal to the power source line VIN, the diode D2 is a reverse-blocking diode, and the diode D1 is a forward-conducting diode, since the diode D1 is turned on, a side vector of the substrate of the NMOS transistor NM1 corresponding to the power source line VIN can be determined, so that the drain terminal and the drain terminal corresponding to the NMOS transistor NM1, that is, the second terminal of the NMOS transistor NM1 is a drain terminal, and the first terminal of the source terminal NM1 is a source terminal.

For the NMOS transistor NM1, as known from the NMOS transistor process, the conductivity type of the NMOS transistor substrate is P-type, and the conductivity types of the source terminal and the drain terminal of the NMOS transistor are both N-type. In the embodiment of the utility model provides an in, the substrate of NMOS pipe NM11 is connected with diode D1's positive pole end and diode D2's positive pole end, and diode D1's negative pole end is connected with NMOS pipe NM 1's first end, and diode D2's negative pole end is connected with NMOS pipe NM 1's second end. For the NMOS transistor NM1, the N-type conduction region of the source terminal, the N-type conduction region of the drain terminal and the P-type substrate form a parasitic diode.

As can be seen from the above description, neither the power line VIN nor the power VCC terminal can be directly connected to the P substrate of the NMOS NM 1. Because the voltage output by the power line VIN is variable and not fixed, if the P substrate of the NMOS transistor NM1 is directly connected to the power line VIN or the power VCC terminal, for example, the P substrate of the NMOS transistor NM1 is connected to the power VCC terminal, when the voltage of the power line VIN is greater than the voltage of the power VCC terminal, the NMOS transistor NM1 may be considered to operate normally, but due to the variable voltage output by the power line VIN, when the voltage output by the power line VIN is less than the voltage of the power VCC terminal, the power VCC terminal is connected to the P substrate of the NMOS transistor NM1, which causes the parasitic diode (the parasitic diode formed by the N-type conductive region connected to the power line VIN and the P substrate) to turn on, so that the voltage of the power VCC terminal may not be stabilized regardless of the size of the load capacitor CAP, and may vary with the voltage variation of the power line VIN.

To sum up, the utility model discloses a source leakage selection circuit and NMOS pipe NM1 cooperation can improve power cord VIN, power VCC end and NMOS pipe NM1 and be connected the complex convenience, can ensure again that power VCC end output voltage reaches required steady state.

Further, the comparator comprises a resistor R4, a resistor R5, an NMOS transistor NM2 and an NMOS transistor NM3, wherein one end of the resistor R4 is connected to the other end of the resistor R3 and a power supply VCC terminal, the other end of the resistor R4 is connected to a gate terminal of the NMOS transistor NM3, one end of the resistor R5 is connected to the power supply line VIN, the other end of the resistor R1 and the other end of the resistor R2, and the other end of the resistor R5 is connected to a gate terminal of the NMOS transistor NM 2;

the substrate of the NMOS tube NM2 and the substrate of the NMOS tube NN3 are both connected with the ground wire GND; the source terminal of the NMOS tube NM2 and the source terminal of the NMOS tube NM3 are both connected with the drain terminal of the NMOS tube NM5, the gate terminal of the NMOS tube NM5 is connected with the gate terminal of the NMOS tube NM4, the gate terminal of the NMOS tube NM6 and the drain terminal of the NMOS tube NM4, and the source terminal of the NMOS tube NM4, the source terminal of the NMOS tube NM5 and the source terminal of the NMOS tube NM6 are all connected with the ground wire GND;

the drain terminal of NMOS transistor NM2 is connected with the drain terminal of PMOS transistor PM3 and the gate terminal of PMOS transistor PM4, the drain terminal of NMOS transistor NM3 is connected with the gate terminal of PMOS transistor PM3, the drain terminal of PMOS transistor PM4 and the gate terminal of PMOS transistor PM5, and the source terminal of PMOS transistor PM3, the source terminal of PMOS transistor PM4 and the source terminal of PMOS transistor PM5 are all connected with power VCC.

The embodiment of the utility model provides an in, NMOS pipe NM 4's drain terminal, NMOS pipe NM 4's grid terminal, NMOS pipe NM 5's grid terminal and NMOS pipe NM 6's grid terminal still connect electric current IB, electric current IB produces for reference current source, and electric current IB's specific size can be based on by reference current source production, and electric current IB's size is accurate in order to guarantee the normal work of comparator, and reference current source produce the condition of required electric current IB specifically for this technical field personnel are known, and it is no longer repeated here.

When the voltage of the power line VIN is higher than the voltage of the power source VCC terminal, the NMOS transistor NM2 is turned on, and the gate voltage of the PMOS transistor PM4 is turned on after going low, so that the gate voltage of the PMOS transistor PM5 goes high, that is, the PMOS transistor PM5 is in a cut-off state. Since the NMOS transistor NM4, the NMOS transistor NM5, and the NMOS transistor NM6 are mirror current sources, and the NMOS transistor NM6 is in a conducting state, the voltages of the corresponding gate terminals of the PMOS transistor PM6 and the NMOS transistor NM7 are all low, i.e., the comparator output is low.

When the voltage of the VCC terminal is higher than the voltage of the power line VIN, the NMOS transistor NM3 is turned on, the PMOS transistor MP3 is turned on, and the PMOS transistor PM4 is turned off, so that the voltage at the gate terminal of the PMOS transistor PM5 becomes low, the PMOS transistor PM5 is turned on, and the PMOS transistor PM5 is turned on, thereby enabling the output of the comparator to be at a high level.

In addition, the transistor also comprises a PMOS tube PM1 and a PMOS tube PM2, wherein a source terminal of the PMOS tube PM1 and a source terminal of the PMOS tube PM2 are both connected with a VCC terminal, a grid terminal of the PMOS tube PM1 is connected with a drain terminal of the PMOS tube PM1, a drain terminal of the NMOS tube NM2, a drain terminal of the PMOS tube PM3 and a grid terminal of the PMOS tube PM4, and a grid terminal of the PMOS tube PM2 is connected with a drain terminal of the PMOS tube PM2, a grid terminal of the PMOS tube PM3, a drain terminal of the PMOS tube PM4 and a source terminal of the PMOS tube PM 5.

The embodiment of the utility model provides an in, utilize PMOS pipe PM1, PMOS pipe PM2 can realize protecting PMOS pipe PM3, PMOS pipe PM4 to avoid the voltage of the corresponding gate terminal of PMOS pipe PM3, PMOS pipe PM4 to hang down, can avoid PMOS pipe PM3, PMOS pipe PM4 because the gate terminal voltage hangs down and leads to PMOS pipe PM3, PMOS pipe PM 4's damage. When the PMOS transistor PM1 and the PMOS transistor PM2 exist, it is equivalent to clamping the gate voltages of the PMOS transistor PM3 and the PMOS transistor PM4, respectively, so that the voltages of the corresponding gate and source terminals of the PMOS transistor PM3 and the PMOS transistor PM4 are not lower than VCC-VTH, where VCC is the voltage value of the VCC terminal of the power supply, and VTH is the threshold voltage of the PMOS transistor PM1 and the PMOS transistor PM 2.

Further, the phase inverter comprises a PMOS tube PM6 and an NMOS tube NM7, the grid end of the PMOS tube PM6 and the grid end of the NMOS tube NM7 are both connected with the drain end of the PMOS tube PM5 and the drain end of the NMOS tube NM6, the source end of the PMOS tube PM6 is connected with a power supply VCC end, and the drain end of the PMOS tube PM6 is connected with the drain end of the NMOS tube NM7 and the grid end of the NMOS tube NM 1; the source terminal of the NMOS transistor NM7 is grounded.

The embodiment of the utility model provides an in, when comparator output low level, PMOS pipe PM6 switches on, and NMOS pipe NM7 is in the off-state to the voltage that has decided NMOS pipe 1 is the high level, makes NMOS pipe 1 keep the on-state, and power cord VIN can charge to power VCC end.

When the comparator outputs high level, the electric potential of the corresponding grid ends of the PMOS pipe PM6 and the NMOS pipe NM7 can be made high level, namely the on-resistance of the PMOS pipe PM5 is much smaller than that of the NMOS pipe, so when the PMOS pipe PM5 is turned on, the grid electric potential of the PMOS pipe PM6 and the NMOS pipe NM7 is high level), at this time, the PMOS pipe PM6 is in an off state, the NMOS pipe NM7 is in an on state, and therefore, according to the connection with the grid end of the NMOS pipe NM1, the voltage of the grid end of the NMOS pipe NM1 can be made low level, and the power supply VCC end is prevented from discharging to the power supply line VIN.

As shown in fig. 2, the substrate of the PMOS transistor PM6 and the source terminal of the PMOS transistor PM6 are both connected to the voltage VCC terminal. In the integrated circuit, as can be known from the basic structure of the PMOS transistor, the conductivity type of the drain terminal of the PMOS transistor PM6 is P +, the drain terminal of the PMOS transistor PM6 is connected to the gate terminal of the NMOS transistor NM1, the substrate of the PMOS transistor PM6 is N +, and the substrate of the PMOS transistor PM6 is connected to the power VCC terminal, so that a forward diode is formed between the drain terminal of the PMOS transistor PM6 and the substrate of the PMOS transistor PM6, and when the voltage of the power VCC terminal is close to the ground line GND, the forward diode is turned on, so that the voltage of the drain terminal of the PMOS transistor PM6 is close to the ground line GND, and therefore the voltage of the gate terminal of the NMOS transistor NM1 connected to the drain terminal of the PMOS transistor PM6 is low, thereby achieving the purpose of turning off the NMOS transistor NM 1. After the NMOS transistor NM1 is turned off, the power line VIN cannot charge the VCC terminal through the NMOS transistor NM1, i.e., the power line VIN forms a path to ground through the NMOS transistor NM 1.

Claims (7)

1. A short circuit isolation circuit suitable for loop bus is characterized in that: the load circuit comprises an NMOS tube NM1, wherein the gate terminal of the NMOS tube NM1 is connected with one end of a resistor R1 and the output end of a phase inverter, the first end of the NMOS tube NM1 is connected with one end of a resistor R2, the second end of the NMOS tube NM1 is connected with one end of a resistor R3, the other ends of the resistor R2 and the resistor R1 are connected with the inverting end of a comparator, the other end of the resistor R3 is connected with the non-inverting end of the comparator and the power supply VCC end of a load circuit, and the power supply end of the comparator and the power supply end of the phase inverter are both connected with the power supply VCC end of the load circuit; the other end of the resistor R1, the other end of the resistor R2 and the inverting terminal of the comparator are all connected with a power line VIN of the loop bus, and the grounding end of the comparator, the grounding end of the inverter and the grounding end of the load circuit are all connected with a grounding line GND of the loop bus;

when the voltage of the power line VIN is higher than the turn-on voltage of the NMOS transistor NM1, the NMOS transistor NM1 can be in a turn-on state, the power line VIN can charge the VCC terminal of the power supply through the NMOS transistor NM1, and after the VCC terminal of the load circuit is charged, the comparator and the inverter can be in a working state;

after the comparator and the phase inverter are in working states, the voltage of the power line VIN is compared with the voltage of the power VCC end through the comparator, when the voltage of the power line VIN is greater than the voltage of the power VCC end, the NMOS tube NM1 keeps in a conducting state, and when the voltage of the power line VIN is lower than the voltage of the power VCC end, the NMOS tube NM1 can be in a switching-off state through the comparator and the phase inverter;

when the load circuit is short-circuited, the NMOS transistor NM1 can be turned off by the cooperation of the inverter and the NMOS transistor NM1, so as to turn off the path of the power supply line VIN to the ground through the NMOS transistor NM 1.

2. The short circuit isolation circuit for a loop bus of claim 1, wherein: the source-drain selection circuit is matched with the NMOS tube NM1 and is connected with the first end of the NMOS tube NM1 and the second end of the NMOS tube NM 1;

when the voltage of the power line VIN is higher than the power source VCC terminal, the first terminal of the NMOS transistor NM1 can be selected as the drain terminal by the source-drain selection circuit, and the second terminal of the NMOS transistor NM1 can be selected as the source terminal by the source-drain selection circuit;

when the voltage of the power line VIN is lower than the power source VCC terminal, the first terminal of the NMOS transistor NM1 can be selected as the source terminal by the source-drain selection circuit, and the second terminal of the NMOS transistor NM1 can be selected as the drain terminal by the source-drain selection circuit.

3. The short circuit isolation circuit for a loop bus of claim 2, wherein: the source-drain selection circuit comprises a diode D1 and a diode D2, wherein the anode end of the diode D1 is connected with the anode end of the diode D2 and the substrate of an NMOS tube NM1, the cathode end of the diode D1 is connected with the first end of the NMOS tube NM1, and the cathode end of the diode D2 is connected with the second end of the NMOS tube NM 2.

4. The short circuit isolation circuit for a loop bus of claim 1, wherein: the comparator comprises a resistor R4, a resistor R5, an NMOS tube NM2 and an NMOS tube NM3, wherein one end of the resistor R4 is connected with the other end of the resistor R3 and a power supply VCC end, the other end of the resistor R4 is connected with the gate end of the NMOS tube NM3, one end of the resistor R5 is connected with a power supply line VIN, the other end of the resistor R1 and the other end of the resistor R2, and the other end of the resistor R5 is connected with the gate end of the NMOS tube NM 2;

the substrate of the NMOS tube NM2 and the substrate of the NMOS tube NN3 are both connected with the ground wire GND; the source terminal of the NMOS tube NM2 and the source terminal of the NMOS tube NM3 are both connected with the drain terminal of the NMOS tube NM5, the gate terminal of the NMOS tube NM5 is connected with the gate terminal of the NMOS tube NM4, the gate terminal of the NMOS tube NM6 and the drain terminal of the NMOS tube NM4, and the source terminal of the NMOS tube NM4, the source terminal of the NMOS tube NM5 and the source terminal of the NMOS tube NM6 are all connected with the ground wire GND;

the drain terminal of NMOS transistor NM2 is connected with the drain terminal of PMOS transistor PM3 and the gate terminal of PMOS transistor PM4, the drain terminal of NMOS transistor NM3 is connected with the gate terminal of PMOS transistor PM3, the drain terminal of PMOS transistor PM4 and the gate terminal of PMOS transistor PM5, and the source terminal of PMOS transistor PM3, the source terminal of PMOS transistor PM4 and the source terminal of PMOS transistor PM5 are all connected with power VCC.

5. The short circuit isolation circuit for a loop bus of claim 4, wherein: the transistor also comprises a PMOS transistor PM1 and a PMOS transistor PM2, wherein a source terminal of the PMOS transistor PM1 and a source terminal of the PMOS transistor PM2 are both connected with a VCC terminal, a gate terminal of the PMOS transistor PM1 is connected with a drain terminal of the PMOS transistor PM1, a drain terminal of the NMOS transistor NM2, a drain terminal of the PMOS transistor PM3 and a gate terminal of the PMOS transistor PM4, and a gate terminal of the PMOS transistor PM2 is connected with a drain terminal of the PMOS transistor PM2, a gate terminal of the PMOS transistor PM3, a drain terminal of the PMOS transistor PM4 and a source terminal of the PMOS transistor PM 5.

6. The short-circuit isolation circuit for a loop bus as claimed in claim 4 or 5, wherein: the phase inverter comprises a PMOS tube PM6 and an NMOS tube NM7, the grid end of the PMOS tube PM6 and the grid end of the NMOS tube NM7 are both connected with the drain end of the PMOS tube PM5 and the drain end of the NMOS tube NM6, the source end of the PMOS tube PM6 is connected with a power supply VCC end, and the drain end of the PMOS tube PM6 is connected with the drain end of the NMOS tube NM7 and the grid end of the NMOS tube NM 1; the source terminal of the NMOS transistor NM7 is grounded.

7. The short circuit isolation circuit for a loop bus of claim 1, wherein: a load capacitor CAP is also included in parallel with the load circuit.

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