CN210986049U - Precision DME logarithmic medium-discharge circuit - Google Patents
Precision DME logarithmic medium-discharge circuit Download PDFInfo
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- CN210986049U CN210986049U CN201922265210.4U CN201922265210U CN210986049U CN 210986049 U CN210986049 U CN 210986049U CN 201922265210 U CN201922265210 U CN 201922265210U CN 210986049 U CN210986049 U CN 210986049U
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- intermediate frequency
- amplifying circuit
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Abstract
The utility model discloses a discharge circuit in accurate DME logarithm. The circuit comprises a 3.5MHz bandwidth intermediate frequency filter circuit, a 0.5MHz bandwidth intermediate frequency filter circuit, two logarithmic amplifiers, a delay compensation circuit and four amplification circuits; the 63MHz intermediate frequency input signal outputs a Video signal through a 3.5MHz bandwidth intermediate frequency filter circuit, a first logarithmic amplifier, a 0.5MHz bandwidth intermediate frequency filter circuit and a second logarithmic amplifier, and the Video signal is provided for a half-amplitude detection circuit to be used as a temporary wave channel suppression; the video signal is output to a precise logarithmic signal through a first amplifying circuit and a second amplifying circuit and is provided for a precise signal processing circuit to be processed; after the logarithmic video signal is amplified by the third amplifying circuit, the logarithmic video signal and the signal output by the delay compensation are output to the fourth amplifying circuit together, and after the logarithmic video signal and the signal output by the delay compensation are amplified, a conventional logarithmic signal is output and provided for a conventional signal processing circuit to be processed. The circuit has stable work and reliable performance, reduces noise and improves the signal-to-noise ratio.
Description
Technical Field
The utility model relates to a ground navigation technique, in particular to discharge circuit in accurate DME logarithm is applicable to accurate DME ground equipment.
Background
The conventional logarithmic medium-frequency amplifier circuit applied to the precision DME adopts a two-stage baseband logarithmic amplifier, has low gain and large noise, cannot meet the requirements of high sensitivity and large dynamic range of precision DME ground equipment, and how to solve the problem becomes a subject to be researched and solved by the technical personnel in the field.
Disclosure of Invention
In order to overcome prior art's not enough, to prior art gain low, the big problem of noise, the utility model provides an accurate DME logarithmic mesodischarge circuit.
The utility model discloses the technical scheme who takes is, a discharge circuit in accurate DME logarithm, its characterized in that: the digital-to-analog converter comprises a 3.5MHz bandwidth intermediate frequency filter circuit, a 0.5MHz bandwidth intermediate frequency filter circuit, a first logarithmic amplifier, a second logarithmic amplifier, a delay compensation circuit, a first amplifying circuit, a second amplifying circuit, a third amplifying circuit and a fourth amplifying circuit, wherein the 3.5MHz bandwidth intermediate frequency filter circuit is sequentially connected with the first logarithmic amplifier, the 0.5MHz bandwidth intermediate frequency filter circuit and the second logarithmic amplifier, the first logarithmic amplifier and the second logarithmic amplifier are respectively connected with the first amplifying circuit and the third amplifying circuit, and the first amplifying circuit and the third amplifying circuit are respectively connected with the second amplifying circuit, the fourth amplifying circuit and the delay compensation circuit.
The utility model has the advantages that: the logarithmic middle-discharge circuit is tested, the circuit works stably and has reliable performance, and a 3.5MHz bandwidth filter circuit and a 0.5MHz bandwidth filter circuit are added in the circuit, so that the noise is reduced, and the signal-to-noise ratio is improved.
Drawings
Fig. 1 is a circuit connection block diagram of the present invention.
Detailed Description
The present invention will be further explained with reference to the accompanying drawings.
As shown in figure 1, the circuit adopts a logarithm-limiting intermediate frequency amplification principle, adopts a two-stage basic logarithm amplifier and a four-stage amplification circuit for amplification, and increases the sensitivity and the dynamic range of the circuit. The circuit comprises a 3.5MHz bandwidth intermediate frequency filter circuit, a 0.5MHz bandwidth intermediate frequency filter circuit, a first logarithmic amplifier, a second logarithmic amplifier, a delay compensation circuit, a first amplifying circuit, a second amplifying circuit, a third amplifying circuit and a fourth amplifying circuit, wherein the 3.5MHz bandwidth intermediate frequency filter circuit is sequentially connected with the first logarithmic amplifier, the 0.5MHz bandwidth intermediate frequency filter circuit and the second logarithmic amplifier, the first logarithmic amplifier and the second logarithmic amplifier are respectively connected with the first amplifying circuit and the third amplifying circuit, and the first amplifying circuit and the third amplifying circuit are respectively connected with the second amplifying circuit, the fourth amplifying circuit and the delay compensation circuit.
The working principle of the precision DME logarithmic medium-voltage discharge circuit is as follows: the 63MHz intermediate frequency input signal enters a 3.5MHz bandwidth intermediate frequency filter circuit, enters a first logarithmic amplifier after filtering, and simultaneously outputs a radio frequency signal and a video signal, after the video signal is amplified by a first amplifying circuit, one path of the video signal is amplified by a second amplifying circuit and then outputs a precise logarithmic signal which is provided for a precise signal processing circuit of a half-amplitude detection unit for processing, and the other path of the video signal enters a delay compensation circuit; the radio frequency signal output by the first logarithmic amplifier enters a 0.5MHz bandwidth intermediate frequency filter circuit, the filtered signal enters a second logarithmic amplifier for amplification, one path of the signal outputs a Video signal which is provided for a half-amplitude detection circuit to be used as a temporary wave channel inhibition, the other path of the signal outputs a logarithmic Video signal which is amplified by a third amplification circuit, then the signal and a signal output by delay compensation are output to a fourth amplification circuit together, and a conventional logarithmic signal is output after amplification and is provided for a half-amplitude detection unit to be processed by a conventional signal processing circuit.
The technical indexes of the circuit are as follows:
1. the working frequency is as follows: and 63 MHz.
2. Dynamic range: -90dBm to 0 dBm.
3. Linearity of RSSI: 0.4 dB.
4. Power supply voltage: 15V and 5V.
5. The signal-to-noise ratio is greater than 2.
6. Working temperature range: minus 40 ℃ to plus 60 ℃.
Claims (1)
1. A precision DME logarithmic middle-discharge circuit is characterized in that: the digital-to-analog converter comprises a 3.5MHz bandwidth intermediate frequency filter circuit, a 0.5MHz bandwidth intermediate frequency filter circuit, a first logarithmic amplifier, a second logarithmic amplifier, a delay compensation circuit, a first amplifying circuit, a second amplifying circuit, a third amplifying circuit and a fourth amplifying circuit, wherein the 3.5MHz bandwidth intermediate frequency filter circuit is sequentially connected with the first logarithmic amplifier, the 0.5MHz bandwidth intermediate frequency filter circuit and the second logarithmic amplifier, the first logarithmic amplifier and the second logarithmic amplifier are respectively connected with the first amplifying circuit and the third amplifying circuit, and the first amplifying circuit and the third amplifying circuit are respectively connected with the second amplifying circuit, the fourth amplifying circuit and the delay compensation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922265210.4U CN210986049U (en) | 2019-12-17 | 2019-12-17 | Precision DME logarithmic medium-discharge circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922265210.4U CN210986049U (en) | 2019-12-17 | 2019-12-17 | Precision DME logarithmic medium-discharge circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210986049U true CN210986049U (en) | 2020-07-10 |
Family
ID=71438843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922265210.4U Active CN210986049U (en) | 2019-12-17 | 2019-12-17 | Precision DME logarithmic medium-discharge circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210986049U (en) |
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2019
- 2019-12-17 CN CN201922265210.4U patent/CN210986049U/en active Active
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