CN210984239U - Display substrate and display device - Google Patents
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- CN210984239U CN210984239U CN201922108775.1U CN201922108775U CN210984239U CN 210984239 U CN210984239 U CN 210984239U CN 201922108775 U CN201922108775 U CN 201922108775U CN 210984239 U CN210984239 U CN 210984239U
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Abstract
The present disclosure provides a display substrate and a display device. The display substrate comprises a substrate and a display function layer arranged on the substrate, wherein the display function layer comprises a plurality of first grid lines extending along a first direction and a plurality of second grid lines extending along the first direction; the display functional layer further comprises a plurality of pixel circuits arranged along a first direction and a second direction, and the display functional layer further comprises a plurality of sensing lines extending along the second direction and a plurality of power lines extending along the second direction; a row of pixel circuits arranged along a first direction is arranged between the adjacent first grid lines and the second grid lines, any first grid line is electrically connected with the grid signal input end of the pixel circuit adjacent along a second direction, and any second grid line is electrically connected with the sensing control signal input end of the pixel circuit adjacent along the second direction. Further improvement of resolution is achieved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and more particularly, to a display substrate and a display device.
Background
The display device of the light emitting diode type is, for example, an organic light emitting diode (O L ED) display panel or a quantum dot light emitting diode display panel.
SUMMERY OF THE UTILITY MODEL
The present disclosure provides a display substrate and a display device to improve the resolution of a light emitting diode type display device.
According to a first aspect of the present disclosure, a display substrate is provided, which includes a substrate and a display function layer disposed on the substrate, where the display function layer includes a plurality of first gate lines extending along a first direction and a plurality of second gate lines extending along the first direction, the first gate lines and the second gate lines are alternately arranged at intervals along a second direction, and the second direction intersects with the first direction; the display functional layer further includes a plurality of pixel circuits arranged in the first direction and the second direction, and a plurality of sensing lines extending in the second direction and a plurality of power supply lines extending in the second direction; and a row of pixel circuits arranged along the first direction is arranged between the adjacent first grid lines and the second grid lines, any first grid line is electrically connected with the grid signal input end of the pixel circuit adjacent along the second direction, and any second grid line is electrically connected with the sensing control signal input end of the pixel circuit adjacent along the second direction.
In some embodiments, two rows of pixel circuits arranged along the second direction are disposed between adjacent sensing lines, and the sensing lines are electrically connected to sensing signal terminals of the pixel circuits adjacent to each other along the first direction.
In some embodiments, the sensing lines are electrically connected to the sensing signal terminals of the corresponding pixel circuits through sensing connection lines extending along the first direction, and two rows of pixel circuits are spaced between adjacent sensing connection lines and arranged along the first direction.
In some embodiments, a plurality of rows of pixel circuits arranged along the second direction are disposed between adjacent power lines, at least one row of pixel circuits arranged along the second direction is spaced between any sensing line and any power line, and a power input end of the same row of pixel circuits arranged along the second direction is electrically connected to one of the power lines closest to the pixel circuit.
In some embodiments, the power line is electrically connected to the power input terminal of the corresponding pixel circuit through a power connection line extending along the first direction, and two rows of pixel circuits are arranged along the first direction between two adjacent power connection lines.
In some embodiments, the power connection line is located between two rows of pixel circuits where the sensing connection line is disposed, or the power connection line is located between two rows of pixel circuits where the sensing connection line is not disposed.
In some embodiments, the display function layer further includes light emitting elements of four colors, a plurality of light emitting elements of each color are included, each pixel circuit is electrically connected to one of the light emitting elements, the four colors are divided into a first color, a second color, a third color, and a fourth color, the light emitting elements of the first color and the light emitting elements of the second color are alternately arranged in the first direction, the light emitting elements of the first color and the light emitting elements of the third color are alternately arranged in the second direction, the light emitting elements of the third color and the light emitting elements of the fourth color are alternately arranged in the first direction, and the light emitting elements of the second color and the light emitting elements of the fourth color are alternately arranged in the second direction.
In some embodiments, the display function layer further includes a plurality of data lines extending in a second direction, two data lines are disposed between two adjacent rows of the pixel circuits arranged in the second direction, the plurality of data lines are divided into a plurality of first data lines, a plurality of second data lines, a plurality of third data lines and a plurality of fourth data lines, each first data line is electrically connected with the data input ends of a row of pixel circuits connected with the first color light-emitting elements and arranged along the second direction, each second data line is electrically connected with the data input ends of a row of pixel circuits connected with the second color light-emitting elements and arranged along the second direction, each third data line is electrically connected with the data input ends of a row of pixel circuits connected with the third color light-emitting elements and arranged along the second direction, and each fourth data line is electrically connected with the data input ends of a row of pixel circuits connected with the fourth color light-emitting elements and arranged along the second direction.
In some embodiments, the sensing line is disposed between adjacent data lines, and the power line is disposed between adjacent data lines.
In some embodiments, the first color, the second color, the third color, and the fourth color are each one of red, green, blue, and white.
In some embodiments, the light emitting element is an organic light emitting diode or a quantum dot light emitting diode.
In some embodiments, the pixel circuit includes a switching transistor, a driving capacitor, and a sensing transistor, wherein a control electrode of the switching transistor is connected to a corresponding gate signal input terminal, a first electrode of the switching transistor is connected to a corresponding data input terminal, a second electrode of the switching transistor, a gate electrode of the driving transistor, and a first electrode of the driving capacitor are electrically connected, a first electrode of the driving transistor is connected to a corresponding power input terminal, a second electrode of the driving transistor and a first electrode of the sensing transistor are electrically connected, a control electrode of the sensing transistor is connected to a corresponding sensing control signal terminal, and a second electrode of the sensing transistor is electrically connected to a corresponding sensing signal terminal.
According to a second aspect of the present disclosure, there is provided a display device comprising the display substrate of the first aspect of the present disclosure.
Drawings
Fig. 1 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
Fig. 2 is a layout view of a display substrate according to an embodiment of the disclosure.
Fig. 3 is a layout view of a display substrate according to an embodiment of the disclosure.
Fig. 4 is a layout view of a display substrate according to an embodiment of the disclosure.
Fig. 5 is a timing diagram illustrating driving of the display substrate shown in fig. 4.
Fig. 6 is a stacked diagram of a portion of the circuit shown in fig. 1.
The reference numeral 100 denotes a pixel circuit, T0 denotes a driving transistor, T1 denotes a switching transistor, T2 denotes a sensing transistor, C denotes a driving capacitor, D denotes a light emitting element, D L denotes a data line, D L R denotes a first data line, D L G denotes a second data line, D L B denotes a third data line, D L W denotes a fourth data line, G L, G L _1, G L _2, G L _3 denotes a first gate line, G L, G L _1, G L _2, G L _3 denotes a second gate line, S L denotes a sensing line, S L0 denotes a sensing connection line, VDD L denotes a power supply line, L denotes a power supply connection line, R denotes a red light emitting element, G denotes a green light emitting element, B denotes a blue light emitting element, W denotes a white light emitting element, 1 denotes a substrate, 2 denotes a light emitting element, 3 denotes a source layer, a gate insulating layer, VSS 5, VSS 0 denotes a gate insulating layer, a power supply connection line, R denotes a red light emitting element, a green light emitting element, a blue light emitting element, a white light emitting element, a pixel electrode, a gate insulating layer, a gate electrode.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In this disclosure, "layered" means that the two structures are formed from the same layer of material and thus are in layered relationship in the same layer, but does not mean that they are equidistant from the substrate nor that they are completely identical in structure to other layers between the substrate.
An embodiment of the present invention provides a display substrate, referring to fig. 1-4 and 6, including a substrate 1 and a display function layer disposed on the substrate 1, the display function layer includes a plurality of first gate lines G L extending along a first direction and a plurality of second gate lines G L extending along the first direction, the first gate lines G L and the second gate lines G L are alternately arranged along a second direction, the second direction crosses the first direction, the display function layer further includes a plurality of pixel circuits 100 arranged along the first direction and the second direction, the display function layer further includes a plurality of sensing lines S L extending along the second direction and a plurality of power lines VDD L extending along the second direction, a row of pixel circuits 100 arranged along the first direction is disposed between adjacent first gate lines G L and second gate lines 829g L, any first gate line G L is electrically connected to a gate signal input terminal P35 of the pixel circuit 100 adjacent along the second direction, and any second gate line G L is electrically connected to a pixel signal input terminal P2 of the adjacent pixel circuit 100 along the second direction.
The display substrate can be used for preparing an organic light-emitting diode display device or a quantum dot light-emitting diode display device and the like.
The first direction is, for example, a row direction and the second direction is, for example, a column direction.
If an external driving circuit (e.g., a driving chip) supplies an active signal to the first gate line G L1, the pixel circuit 100 to which the first gate line G L1 is connected can be written with a data voltage.
If the external driving circuit supplies an active signal to the second gate line G L2, the pixel circuit 100 to which the second gate line G L2 is connected can be written with the data compensation voltage.
Referring to fig. 2, the first gate line G L1 and the second gate line G L2 are arranged in a column direction in such a manner that the first gate line G L1 _1, the second gate line G L2 _1, the first gate line G L1 _2, the second gate line G L2 _2, the first gate line G L1 _3, and the second gate line G L2 _3 are arranged.
In this arrangement, one first gate line G L1 can drive two rows of pixel circuits 100, and one second gate line G L2 can also drive two rows of pixel circuits 100, so that the number of the first gate lines G L1 and the second gate lines G L2 is reduced, which is beneficial to the improvement of resolution.
It should be noted that, at two ends in the column direction, whether the first gate line G L1 or the second gate line G L2 is provided in addition to the outermost row of pixel circuits 100 may be flexibly set by those skilled in the art, even if the outermost row of pixel circuits 100 is not connected to the second gate line G L2, the data voltage written to only the outermost row of pixel circuits is not compensated, and the overall influence on the display is small.
Referring to fig. 1, the pixel circuit 100 includes a switching transistor T1, a driving transistor T0, a driving capacitor C, and a sensing transistor T2, wherein a control electrode of the switching transistor T1 is connected to a corresponding gate signal input terminal P1, a first electrode 6 of the switching transistor T1 is connected to a corresponding data input terminal P3, a second electrode 7 of the switching transistor T1, a gate electrode 4 of the driving transistor T0, and a first electrode 6 of the driving capacitor C are electrically connected, a first electrode 6 of the driving transistor T0 is connected to a corresponding power input terminal P4, a second electrode 7 of the driving transistor T0 and a first electrode 6 of the sensing transistor T2 are electrically connected, a control electrode of the sensing transistor T2 is connected to a corresponding sensing control signal terminal, and a second electrode 7 of the sensing transistor T2 is electrically connected to a corresponding sensing signal terminal.
The light emitting element D is, for example, an organic light emitting diode, and its cathode is connected to a ground line VSS L through a ground terminal P5.
The pixel circuit 100 shown in fig. 1 is also referred to as a 3T1C circuit structure, and the pixel circuit 100 obtained by adding other components such as transistors is also applicable to the layout of the circuit provided in the present disclosure.
Referring to fig. 6, the driving transistor T0 provided on the substrate 1 includes: an active layer 2, a gate insulating layer 3, a gate electrode 4, a first electrode 6, and a second electrode 7. An interlayer insulating layer 5 is disposed on the side of the circuit connected to the first electrode 6 facing the substrate 1. The second electrode 7 is connected to the pixel electrode 9 through a via hole penetrating the interlayer insulating layer 5 and the passivation layer 8. The pixel electrode 9, the organic functional layer 11, and the cathode 12 constitute an organic light emitting diode. The pixel defining layer 10 defines the outer portion of the organic functional layer 11.
In some embodiments, two rows of pixel circuits 100 arranged along the second direction are disposed between the adjacent sensing lines S L, and the sensing line S L is electrically connected to the sensing signal ends of the pixel circuits 100 adjacent to each other along the first direction.
For example, according to the current view of fig. 2, one row of sensing lines S L connects two adjacent rows of pixel circuits 100, thereby reducing the number of sensing lines S L and improving the display resolution.
In some embodiments, the sensing line S L is electrically connected to the sensing signal terminal of the corresponding pixel circuit 100 through a sensing connection line S L0 extending along the first direction, and two rows of pixel circuits 100 arranged along the first direction are spaced between adjacent sensing connection lines S L0.
For example, according to the current view of fig. 2, one sensing connection line S L0 extending in the row direction is connected to two pixel circuits 100 above it and two pixel circuits 100 below it.
In some embodiments, a plurality of rows of pixel circuits 100 arranged along the second direction are disposed between adjacent power lines VDD L, at least one row of pixel circuits 100 arranged along the second direction is spaced between any sensing line S L and any power line VDD L, and the power input end P4 of the same row of pixel circuits 100 arranged along the second direction is electrically connected to one of the power lines VDD L closest to the pixel circuit 100.
Referring to fig. 3, the power line VDD L is disposed between adjacent sensing lines S L, and the same power line VDD L connects four columns of pixel circuits 100, and thus, the sensing lines S L, one column of pixel circuits 100, the power line VDD L, one column of pixel circuits 100, the sensing line S L, one column of pixel circuits 100, the power line VDD L, and one column of pixel circuits 100 are periodically arranged in the row direction.
Of course, one power line VDD L may be connected to pixel circuits 100 in more columns such as 8 columns of pixel circuits 100, and thus, the pixel circuits are periodically arranged in the row direction in the manner of a sensing line S L, a column of pixel circuits 100, a power line VDD L, a column of pixel circuits 100, a sensing line S L, two columns of pixel circuits 100, a sensing line S L, a column of pixel circuits 100, a power line VDD L, a column of pixel circuits 100, a sensing line S L, and two columns of pixel circuits 100.
The number of columns of pixel circuits 100 to which different power supply lines VDD L are connected may also be different.
Therefore, the number of the power lines VDD L can be reduced, and the display resolution is further improved.
In some embodiments, referring to fig. 2 and 3, the power line VDD L is electrically connected to the power input terminal P4 of the corresponding pixel circuit 100 through a power connection line VDD L0 extending along a first direction, and two rows of pixel circuits 100 arranged along the first direction are spaced between adjacent power connection lines VDD L0.
The same power connection line VDD L0 is connected to two rows of pixel circuits 100 opposite to each other, so that no two rows of pixel circuits 100 are provided with one (or more) power connection lines VDD L0, further reducing the space occupied by wiring and improving the resolution.
In some embodiments, referring to fig. 2, the power connection line VDD L0 is located between two rows of pixel circuits 100 where the sensing connection line S L0 is disposed, or referring to fig. 3, the power connection line VDD L0 is located between two rows of pixel circuits 100 where the sensing connection line S L0 is not disposed.
The above are two possible distribution ways of the power connection line VDD L0.
In some embodiments, referring to fig. 2, the display function layer further includes light emitting elements D of four colors, a plurality of light emitting elements D of each color, each pixel circuit 100 electrically connected to one of the light emitting elements D, the four colors being divided into a first color, a second color, and a third color and a fourth color, wherein the light emitting elements D of the first color (not shown in fig. 2, identified only by the letter R) and the light emitting elements D of the second color (not shown in fig. 2, identified only by the letter G) are alternately arranged in the first direction, the light emitting elements D of the first color and the light emitting elements D of the third color are alternately arranged in the second direction, the light emitting elements D of the third color (not shown in fig. 2, identified only by the letter B) and the light emitting elements D of the fourth color (not shown in fig. 2, identified only by the letter S) are alternately arranged in the first direction, and the light emitting elements D of the second color and the light emitting elements D of the fourth color are alternately arranged in the second direction.
For example, the first color, the second color, the third color, and the fourth color are respectively one of red, green, blue, and white. The first color, the second color, the third color and the fourth color are different colors.
In this manner, the light emitting elements D connected to the four pixel circuits 100 distributed in one approximately square region constitute one pixel.
Of course, the light-emitting element D necessary for forming one pixel may be a light-emitting element D to which three pixel circuits 100 are connected.
The light emitting elements D are arranged in a manner such that, for example, the light emitting elements D in the first row are periodically arranged in a manner of red, green, blue, red, green, and blue, and the light emitting elements D in the second row are periodically arranged in a manner of blue, green, red, blue, green, and red, and so on.
In some embodiments, referring to fig. 4, the display function layer further includes a plurality of data lines D L extending in the second direction, two data lines D L are disposed between two adjacent rows of the pixel circuits 100 arranged in the second direction, the plurality of data lines D L0 are divided into a plurality of first data lines D L R, a plurality of second data lines D L G, a plurality of third data lines D L B, and a plurality of fourth data lines D L W, each of the first data lines D L R is electrically connected to the data input terminals P3 of a row of the pixel circuits 100 connected to the first color light emitting elements D arranged in the second direction, each of the second data lines D L G is electrically connected to the data input terminals P3 of a row of the pixel circuits 100 connected to the second color light emitting elements D arranged in the second direction, each of the third data lines D L B is electrically connected to the data input terminals P3 of a row of the pixel circuits 100 connected to the third color light emitting elements D arranged in the second direction, and each of the fourth data lines D L W is electrically connected to the data input terminals P3 of the pixel circuits 100 connected to the fourth color light emitting elements D arranged in the second direction.
That is, one data line D L provides a corresponding data voltage to the pixel circuits 100 connected to the light emitting elements D of the same color in one column of the pixel circuits 100.
In some embodiments, referring to fig. 4, the sensing line S L is disposed between adjacent data lines D L, and the power supply line VDD L is disposed between adjacent data lines D L.
Thus, the path from the data line D L to the corresponding pixel circuit 100 can be reduced, and the display accuracy can be improved.
In some embodiments, the light emitting element D is an organic light emitting diode or a quantum dot light emitting diode.
It should be noted that, the present disclosure does not limit the layered structure of the above lines, for example, some of them are disposed in the same layer, and others are disposed in different layers, and two connected lines may be connected in the same layered structure, or may be connected through a via.
Referring to fig. 6, the first gate line G L1 may be disposed at the same layer as the gate electrode 4, and the data line D L may be disposed at the same layer as the first electrode 6.
For another example, the sensing line S L and the sensing connecting line S L0 may be disposed on the same layer, or may be disposed on different layers, and so on.
Referring to fig. 5, in a frame period, an effective voltage (e.g., a high level voltage) may be supplied to all the second gate lines G L in an initial first stage T0. among them, a signal supplied to the first second gate line G L _1 is labeled as G2_1, a signal supplied to the second gate line G L _2 is labeled as G2_2, and so on.
A signal applied to the pixel circuit 100 by the i-th first gate line G L1 is denoted by G1_ i, and a signal applied to the pixel circuit 100 by the i + 1-th first gate line G L1 is denoted by G1_ i + 1.
When an active voltage (e.g., a high level voltage) is received on the ith first gate line G L1, the pixel circuits connected to the corresponding row of pixel circuits are written with data voltages.
Referring to fig. 5, in the second stage P2, the pixel circuit 100 corresponding to the red light emitting element D and the pixel circuit 100 corresponding to the green light emitting element D in the pixel circuit 100 connected to the i-th row first gate line G L are written with data voltages (denoted as DR and DB, respectively), and in the third stage P3, the pixel circuit 100 corresponding to the red light emitting element D and the pixel circuit 100 corresponding to the green light emitting element D in the pixel circuit 100 connected to the i + 1-th row first gate line G L are written with data voltages.
An embodiment of the present disclosure further provides a display device, including the foregoing display substrate.
The display device is any product or component having a display function, such as an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mobile phone, and a navigator.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (10)
1. A display substrate comprises a substrate and a display function layer arranged on the substrate, wherein the display function layer comprises a plurality of first grid lines extending along a first direction and a plurality of second grid lines extending along the first direction, the display substrate is characterized in that the first grid lines and the second grid lines are alternately arranged at intervals along a second direction, and the second direction is intersected with the first direction; the display functional layer further includes a plurality of pixel circuits arranged in the first direction and the second direction, and a plurality of sensing lines extending in the second direction and a plurality of power supply lines extending in the second direction; and a row of pixel circuits arranged along the first direction is arranged between the adjacent first grid lines and the second grid lines, any first grid line is electrically connected with the grid signal input end of the pixel circuit adjacent along the second direction, and any second grid line is electrically connected with the sensing control signal input end of the pixel circuit adjacent along the second direction.
2. The display substrate according to claim 1, wherein two rows of pixel circuits arranged along the second direction are disposed between adjacent sensing lines, and the sensing lines are electrically connected to sensing signal terminals of the pixel circuits adjacent to each other along the first direction.
3. The display substrate according to claim 2, wherein the sensing lines are electrically connected to the sensing signal terminals of the corresponding pixel circuits through sensing connection lines extending along the first direction, and two rows of pixel circuits are arranged between adjacent sensing connection lines along the first direction.
4. The display substrate according to claim 3, wherein a plurality of rows of pixel circuits are disposed between adjacent power lines, at least one row of pixel circuits is disposed between any sensing line and any power line, and the power input terminal of the same row of pixel circuits disposed in the second direction is electrically connected to one of the power lines closest to the pixel circuit.
5. The display substrate of claim 4, wherein the power lines are electrically connected to the power input terminals of the corresponding pixel circuits through power connection lines extending along the first direction, and two rows of pixel circuits are arranged along the first direction between two adjacent power connection lines.
6. The display substrate according to claim 5, wherein the power connection line is located between two rows of pixel circuits where the sensing connection line is disposed, or the power connection line is located between two rows of pixel circuits where the sensing connection line is not disposed.
7. The display substrate according to claim 6, wherein the display function layer further comprises a plurality of light emitting elements of four colors, each of the light emitting elements of four colors is electrically connected to one of the light emitting elements, the four colors are divided into a first color, a second color, a third color, and a fourth color, the light emitting elements of the first color and the light emitting elements of the second color are alternately arranged in the first direction, the light emitting elements of the first color and the light emitting elements of the third color are alternately arranged in the second direction, the light emitting elements of the third color and the light emitting elements of the fourth color are alternately arranged in the first direction, and the light emitting elements of the second color and the light emitting elements of the fourth color are alternately arranged in the second direction.
8. The display substrate according to claim 7, wherein the display function layer further comprises a plurality of data lines extending in a second direction, two data lines are provided between two adjacent rows of the pixel circuits arranged in the second direction, the plurality of data lines are divided into a plurality of first data lines, a plurality of second data lines, a plurality of third data lines and a plurality of fourth data lines, each first data line is electrically connected with the data input ends of a row of pixel circuits connected with the first color light-emitting elements and arranged along the second direction, each second data line is electrically connected with the data input ends of a row of pixel circuits connected with the second color light-emitting elements and arranged along the second direction, each third data line is electrically connected with the data input ends of a row of pixel circuits connected with the third color light-emitting elements and arranged along the second direction, and each fourth data line is electrically connected with the data input ends of a row of pixel circuits connected with the fourth color light-emitting elements and arranged along the second direction.
9. The display substrate according to any one of claims 1 to 8, wherein the pixel circuit comprises a switching transistor, a driving capacitor, and a sensing transistor, wherein a control electrode of the switching transistor is connected to a corresponding gate signal input terminal, a first electrode of the switching transistor is connected to a corresponding data input terminal, a second electrode of the switching transistor, a gate electrode of the driving transistor, and a first electrode of the driving capacitor are electrically connected, a first electrode of the driving transistor is connected to a corresponding power input terminal, a second electrode of the driving transistor and a first electrode of the sensing transistor are electrically connected, a control electrode of the sensing transistor is connected to a corresponding sensing control signal terminal, and a second electrode of the sensing transistor is electrically connected to a corresponding sensing signal terminal.
10. A display device comprising the display substrate according to any one of claims 1 to 9.
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|---|---|---|---|
| CN201922108775.1U CN210984239U (en) | 2019-11-29 | 2019-11-29 | Display substrate and display device |
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| CN201922108775.1U CN210984239U (en) | 2019-11-29 | 2019-11-29 | Display substrate and display device |
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| CN210984239U true CN210984239U (en) | 2020-07-10 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022133803A1 (en) * | 2020-12-23 | 2022-06-30 | 京东方科技集团股份有限公司 | Pixel circuit array, display panel, and driving method therefor |
| WO2022198575A1 (en) * | 2021-03-25 | 2022-09-29 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
| CN115346473A (en) * | 2022-05-25 | 2022-11-15 | 惠科股份有限公司 | Display panel, driving circuit and driving method |
-
2019
- 2019-11-29 CN CN201922108775.1U patent/CN210984239U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022133803A1 (en) * | 2020-12-23 | 2022-06-30 | 京东方科技集团股份有限公司 | Pixel circuit array, display panel, and driving method therefor |
| US11935469B2 (en) | 2020-12-23 | 2024-03-19 | Hefei Boe Joint Technology Co., Ltd. | Pixel circuit array and driving method thereof, display panel and driving method thereof |
| WO2022198575A1 (en) * | 2021-03-25 | 2022-09-29 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
| GB2610080A (en) * | 2021-03-25 | 2023-02-22 | Boe Technology Group Co Ltd | Display substrate and display apparatus |
| CN115346473A (en) * | 2022-05-25 | 2022-11-15 | 惠科股份有限公司 | Display panel, driving circuit and driving method |
| CN115346473B (en) * | 2022-05-25 | 2023-10-24 | 惠科股份有限公司 | Display panel, driving circuit and driving method |
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