CN210956643U - Airtight packaging device - Google Patents

Abstract

The utility model discloses an airtight encapsulation device, include: the packaging shell adopts a ceramic substrate as a packaging bottom plate, the ceramic substrate is provided with a first through hole penetrating through the upper surface and the lower surface of the ceramic substrate, metal is filled in the first through hole of the ceramic substrate, and the metal in the first through hole is marked as a first metal column; the at least two first chips are arranged inside the packaging shell and arranged on the ceramic substrate, and bonding pads of the first chips are connected with first metal columns on the ceramic substrate through bonding wires; the partition wall is arranged in the packaging shell and divides the packaging shell into different airtight cavities, and the first chip needing to be isolated is arranged in the different airtight cavities. The utility model discloses a set up the division wall in the encapsulation shell, the chip that the division wall will keep apart is mutual noninterference between the chip, has improved the isolation of airtight encapsulation device, and then has promoted the performance of airtight encapsulation device.

Description

Airtight packaging device

Technical Field

The utility model relates to a chip package technical field especially relates to an airtight encapsulation device.

Background

From a cellular communication network of hundreds of megameters, to the current 4G communication and 5G communication which is popularized immediately and has the working frequency of dozens of gigahertz, and to the THz field, the working frequency band of the radio frequency microwave circuit is higher and higher. Although the corresponding chip package is upgraded by multiple iterations, the corresponding chip package has many defects.

Along with the improvement of chip function integration level and the reduction of device size, the integrated design of chip, chip keysets and shell is more and more critical, in order to satisfy the encapsulation requirement and improve the integration level of encapsulation, can encapsulate a plurality of chips in an airtight packaging structure, can disturb between chip and the chip, and the isolation of airtight encapsulation device is not high, causes the use of chip inconvenient, can not full play chip's characteristic.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides an airtight encapsulation device aims at solving the not high problem of isolation of present airtight encapsulation device.

An embodiment of the utility model provides an airtight encapsulation device, include:

the packaging shell adopts a ceramic substrate as a packaging bottom plate, the ceramic substrate is provided with a first through hole penetrating through the upper surface of the ceramic substrate and the lower surface of the ceramic substrate, metal is filled in the first through hole of the ceramic substrate, and the metal in the first through hole is marked as a first metal column;

the at least two first chips are arranged inside the packaging shell and arranged on the ceramic substrate, and bonding pads of the first chips are connected with the first metal columns on the ceramic substrate through bonding wires;

and the isolation wall is arranged in the packaging shell and divides the packaging shell into different airtight cavities, and the first chip to be isolated is arranged in the different airtight cavities.

In an embodiment of the present application, the package housing further comprises:

the metal enclosure frame is arranged at the position, used for arranging the metal enclosure frame, on the ceramic substrate;

and the cover plate is welded on the metal enclosure frame and the isolation wall.

In an embodiment of the present application, the package housing further comprises:

the front dielectric layer is arranged on the upper surface of the ceramic substrate in a hot pressing mode; the front dielectric layer is provided with a second through hole and a third through hole which penetrate through the upper surface of the front dielectric layer and the lower surface of the front dielectric layer, metal is filled in the second through hole, the metal in the second through hole is marked as a second metal column, the upper surface of the front dielectric layer is provided with a second chip, a bonding pad of the second chip is connected with at least one second metal column through a bonding wire, and the second metal column is connected with the first metal column;

correspondingly, the first chip is arranged in the third through hole, the first chip is arranged on the upper surface of the ceramic substrate, and a bonding pad of the first chip is connected with the second metal column through a bonding wire;

correspondingly, the isolation wall is arranged in the packaging shell, the packaging shell is divided into different airtight cavities on the front dielectric layer, and the first chip and the second chip to be isolated are arranged in the different airtight cavities;

correspondingly, the metal enclosure frame is arranged on the front dielectric layer and used for arranging the metal enclosure frame.

In an embodiment of the present application, the hermetically sealed device further comprises:

the first front surface seed layer is arranged between the ceramic substrate and the front surface dielectric layer, is positioned in a first preset area on the ceramic substrate and is positioned on the inner side wall of the first through hole, and is used for arranging a first chip, wherein the filled metal is connected with the first through hole through the first front surface seed layer;

the second front surface seed layer is arranged in a first preset area on the front surface dielectric layer and the inner side wall of the second through hole, the second front surface seed layer of the first preset area on the front surface dielectric layer is used for arranging a second chip, the second front surface seed layer of the second preset area on the front surface dielectric layer is used for arranging a metal enclosure frame, and the filled metal is connected with the second through hole through the second front surface seed layer;

correspondingly, the metal enclosure is arranged on the second front-side seed layer and used for arranging the metal enclosure.

In an embodiment of the present application, the hermetically sealed device further comprises:

the first front side conductor layer is arranged between the first front side seed layer and the front side dielectric layer and is positioned on the first front side seed layer, a first area of the first front side conductor layer is used for arranging a first chip, and a second area of the first front side conductor layer is used for thickening the first metal column;

the second front-side conductor layer is arranged on the second front-side seed layer, a first area of the second front-side conductor layer is used for arranging a second chip, a second area of the second front-side conductor layer is used for thickening the second metal column, and a third area of the second front-side conductor layer is used for arranging a metal enclosure frame;

correspondingly, the metal enclosure frame is arranged at the position, used for arranging the metal enclosure frame, on the second front conductor layer.

In an embodiment of the present application, the hermetically sealed device further comprises:

the back dielectric layer is arranged on the back of the ceramic substrate in a hot pressing mode, a fourth through hole penetrating through the upper surface of the back dielectric layer and the lower surface of the back dielectric layer is formed in the back dielectric layer, metal is filled in the fourth through hole, the metal in the fourth through hole is marked as a fourth metal column, and the fourth metal column is connected with the first metal column.

In an embodiment of the present application, the hermetically sealed device further comprises:

the first back seed layer is arranged between the ceramic substrate and the back dielectric layer and positioned in a first preset area below the ceramic substrate, and the first back seed layer in the first preset area is used for growing a first back conductor layer;

the first back conductor layer is arranged between the first back seed layer and the back dielectric layer and positioned below the first back seed layer, and the first back conductor layer is used for thickening the first metal column.

In an embodiment of the present application, the hermetically sealed device further comprises:

the second back surface seed layer is arranged on the inner side wall of the fourth through hole and at a position below the back surface dielectric layer and corresponding to the first preset area of the substrate, and the filled metal is connected with the fourth through hole through the second back surface seed layer;

and the second back conductor layer is arranged below the second back seed layer and is used for thickening the fourth metal column.

In an embodiment of the present application, the hermetically sealed device further comprises:

and the solder mask layer is arranged on the lower surface of the back dielectric layer and is positioned in the area outside the fourth metal column.

In an embodiment of the present application, the hermetically sealed device further comprises:

and the radiating fins are arranged on the front surface of the cover plate.

The utility model discloses a set up the division wall in the encapsulation shell, the chip that the division wall will keep apart is mutual noninterference between the chip, has improved the isolation of airtight encapsulation device, and then has promoted the performance of airtight encapsulation device.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a hermetically sealed device according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structural view illustrating the preparation of a first through hole on a ceramic substrate according to an embodiment of the present invention;

fig. 3 is a schematic bottom view of a first through hole formed in a ceramic substrate according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional structural view illustrating the preparation of the first front seed layer and the first back seed layer according to an embodiment of the present invention;

fig. 5 is a schematic cross-sectional structure diagram of preparing a first photoresist layer according to an embodiment of the present invention;

fig. 6 is a schematic cross-sectional structural diagram of a first front conductor layer and a first back conductor layer according to an embodiment of the present invention;

fig. 7 is a schematic cross-sectional structural diagram of a second embodiment of the present invention illustrating the preparation of a first front conductor layer and a first back conductor layer;

fig. 8 is a schematic cross-sectional view of the first front seed layer and the second back seed layer removed according to an embodiment of the present invention;

fig. 9 is a schematic cross-sectional structural diagram of preparing a front dielectric layer and a back dielectric layer according to an embodiment of the present invention;

fig. 10 is a schematic cross-sectional structural diagram of preparing a second through hole and a fourth through hole according to an embodiment of the present invention;

fig. 11 is a schematic cross-sectional structural view illustrating the preparation of a second front conductor layer and a second back conductor layer according to an embodiment of the present invention;

fig. 12 is a schematic cross-sectional structure diagram of preparing a third through hole according to an embodiment of the present invention;

fig. 13 is a schematic cross-sectional structural view of a prepared metal enclosure frame, a partition wall and a copper heat-conducting post according to an embodiment of the present invention;

fig. 14 is a schematic cross-sectional structural diagram of mounting a first chip and a second chip according to an embodiment of the present invention;

fig. 15 is a schematic cross-sectional structural view of a coupling structure and a heat dissipation fin according to an embodiment of the present invention.

Wherein: 1. a ceramic substrate; 2. a first through hole; 3. a first front side seed layer; 4. a first back side seed layer; 5. a first photoresist layer; 6. a first front-side conductor layer; 7. a first back side conductor layer; 8. a first metal pillar; 9. a front dielectric layer; 10. a back dielectric layer; 11. a second front-side conductor layer; 12. a second back side conductor layer; 13. a second chip; 14. a solder resist layer; 15. a first chip; 16. a metal enclosure frame; 17. a partition wall; 18. a copper heat-conducting post; 19. a cover plate; 20. and (4) radiating fins.

Detailed Description

In order to make the technical solution better understood by those skilled in the art, the technical solution in the embodiment of the present invention will be clearly described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present disclosure without any creative effort shall fall within the protection scope of the present disclosure.

The terms "include" and any other variations in the description and claims of this document and the above-described figures, mean "including but not limited to", and are intended to cover non-exclusive inclusions. Furthermore, the terms "first" and "second," etc. are used to distinguish between different objects and are not used to describe a particular order.

The following detailed description of implementations of the present invention is provided in conjunction with the accompanying drawings:

as shown in fig. 1, an embodiment of the present invention provides a hermetically sealed device, including:

the packaging shell adopts a ceramic substrate 1 as a packaging bottom plate, the ceramic substrate 1 is provided with a first through hole 2 penetrating through the upper surface of the ceramic substrate 1 and the lower surface of the ceramic substrate 1, metal is filled in the first through hole 2 of the ceramic substrate 1, and the metal in the first through hole 2 is marked as a first metal column 8;

at least two first chips 15, which are installed inside the package housing and are disposed on the ceramic substrate 1, wherein pads of the first chips 15 are connected with the first metal posts 8 on the ceramic substrate 1 through bonding wires;

and the separation wall 17 is arranged in the packaging shell to divide the packaging shell into different airtight cavities, and the first chip 15 to be separated is arranged in the different airtight cavities.

In the present embodiment, the ceramic substrate 1 is previously sintered, and may be, for example, alumina ceramic, aluminum nitride ceramic, quartz, or the like. The diameter of the first through-hole 2 can be selected with reference to the following constraints: the ratio of the thickness of the ceramic substrate 1 to the diameter of the first through hole 2 is 3:1 to 4:1, and the diameter of the first through hole 2 may be set to 70 to 125 μm depending on the thickness of the ceramic substrate 1 at the time of actual packaging. The first chip 15 may be a radio frequency chip. The first via 2 is filled with a metal, which may be copper. When the first through hole 2 is prepared on the pre-sintered ceramic substrate 1, a picosecond cold laser machining drilling method can be adopted, and the machined first through hole 2 penetrates through the upper surface and the lower surface of the ceramic substrate 1. The hole wall of the first through hole 2 prepared in the mode is smooth, the verticality is high, the difference value of the hole diameters of the upper surface and the lower surface of the ceramic substrate 1 is less than 5%, the precision is higher, metal can be injected into the first through hole 2 in the subsequent process to serve as a signal transmission line, and the transmission loss can be reduced after the metal is injected into the first through hole 2 prepared in the mode.

In this embodiment, the filling of the metal in the first through hole may be performed by using a metal slurry; if the first through hole is internally provided with the first front seed layer, the metal is filled in an electroplating mode, and the invention mainly adopts the electroplating mode.

In this embodiment, the first chip 15 may be a radio frequency chip, and the first chip 15 may be mounted on the ceramic substrate 1 by surface mounting. The first metal column 8 connected with the bonding pad of the first chip 15 is marked as a first conductive column, and a circle of signal shielding structure formed by the first metal column 8 is further arranged on the periphery of the first conductive column. The signal shielding structure may be a coaxial-like signal shielding structure.

Since the first conductive via needs to transmit signals, a signal shielding structure needs to be provided for the first conductive via. The signal shielding structure in the present application may be configured as follows: when the first through hole 2 corresponding to the first conductive via is prepared, a circle of the first through hole 2 is prepared at the periphery of the first through hole 2, metal slurry is injected into the circle of the first through hole 2 to form a first metal column 8, and the first metal column 8 surrounding the first conductive via can form a signal shielding structure.

In the present embodiment, the first chips 15 are separated by the partition walls 17, so that the first chips 15 do not interfere with each other. The thickness of the partition wall 17 may be between 150 and 200 μm. The partition wall 17 may be made of a metal material, such as copper. The partition wall 17 may be prepared by reinforcing the previously prepared partition wall 17 on the ceramic substrate 1, or preparing the partition wall 17 at a position on the ceramic substrate 1 where the partition wall 17 is reserved by means of a semiconductor process. Of course, in practical applications, the partition walls 17 may be prepared in other ways, for example, the partition walls 17 may be prepared by electrochemical deposition.

The embodiment of the utility model provides an in, through set up division wall 17 in the encapsulation shell, division wall 17 will need the chip isolation of keeping apart, is mutual noninterference between the chip, has improved the isolation of airtight encapsulation device, and then has promoted the performance of airtight encapsulation device. Because adopted to prepare on ceramic substrate 1 behind first through-hole 2 and pour into the metal into in first through-hole 2, then with the metal solidification, the utility model discloses pour into the metal into behind the ceramic substrate 1 of sintering earlier, metal and ceramic substrate 1 can not sinter simultaneously, and the position of first through-hole 2 changes to the uniformity of chip package has been improved.

As shown in fig. 1, in an embodiment of the present invention, the package housing further includes:

a metal enclosure frame 16 provided at a position on the ceramic substrate 1 where the metal enclosure frame 16 is provided;

and the cover plate 19 is welded on the metal surrounding frame 16 and the separation wall 17.

In this embodiment, the metal frame 16 is used as a sidewall of the package housing, and the material of the metal frame 16 may be copper. And a grounding through hole is arranged on the corresponding ceramic substrate 1 below the metal enclosure frame 16, and metal is filled in the grounding through hole. The height of the metal enclosure 16 may be 200-1000 μm. The cover plate 19 may be made of metal. The metal enclosure frame 16 is used as a sidewall of a packaged device, and when the metal enclosure frame 16 is prepared, the metal enclosure frame 16 prepared in advance may be reinforced on the ceramic substrate 1, or may be formed by a semiconductor process: for example, the photoresist on the ceramic substrate 1 at the position where the metal enclosure frame 16 is reserved is removed by photolithography, and the metal enclosure frame 16 can also be prepared on the ceramic substrate 1 at the position where the metal enclosure frame 16 is reserved by electroplating after the photoresist is left on other areas of the ceramic substrate 1. The metal enclosure frame 16 directly grows on the ceramic substrate 1, the height of the metal enclosure frame 16 is controllable, the height of the metal enclosure frame 16 is accurately matched with the frequency of a chip, the spatial coupling degree is adjustable, and the radio frequency characteristic of the chip is improved.

In this embodiment, in order to ensure the air tightness of the package casing, the cover plate 19 may be welded to the metal enclosure frame 16 and the partition wall 17 by parallel seam welding or laser welding, and the material of the cover plate 19 may be a metal material. The ceramic substrate 1, the metal frame 16 and the cover plate 19 form a hermetic package structure, and the first chip 15 is located inside the hermetic package structure.

As shown in fig. 1, in an embodiment of the present invention, the package housing further includes:

the front dielectric layer 9 is arranged on the upper surface of the ceramic substrate 1 in a hot pressing mode; the front dielectric layer 9 is provided with a second through hole and a third through hole which penetrate through the upper surface of the front dielectric layer 9 and the lower surface of the front dielectric layer 9, metal is filled in the second through hole, the metal in the second through hole is marked as a second metal column, the upper surface of the front dielectric layer 9 is provided with a second chip 13, a bonding pad of the second chip 13 is connected with at least one second metal column through a bonding wire, and the second metal column is connected with the first metal column 8;

correspondingly, the first chip 15 is arranged in the third through hole, the first chip 15 is mounted on the upper surface of the ceramic substrate 1, and a bonding pad of the first chip 15 is connected with the second metal column through a bonding wire;

correspondingly, the isolation wall 17 is arranged in the package shell, the package shell is divided into different airtight cavities on the front dielectric layer 9, and the first chip 15 and the second chip 13 to be isolated are arranged in the different airtight cavities;

correspondingly, the metal enclosure frame 16 is arranged on the front dielectric layer 9 and used for arranging the metal enclosure frame 16.

In this embodiment, the lower surface of the front dielectric layer 9 is attached to the upper surface of the ceramic substrate 1, and the front dielectric layer 9 completely covers the ceramic substrate 1. The front dielectric layer 9 may be wired, the second chip 13 may be disposed on the front surface of the front dielectric layer 9, and the front dielectric layer 9 may be a Liquid Crystal Polymer (LCP) with low microwave loss and good temperature stability. The diameter of the second through hole can be set between 70 and 125 microns, and the diameter of the second through hole meets the constraint condition: the ratio of the diameter of the second through hole to the thickness of the ceramic substrate 1 in the front dielectric layer 9 is 1: 1. And filling metal, wherein the metal can be copper, in the second through hole. The first chip 15 is to be placed in the third through hole, and the third through hole penetrates through the front dielectric layer 9, so the first chip 15 in the third through hole can be mounted on the upper surface of the ceramic substrate 1, and the pad of the first chip 15 is to be connected with the second metal pillar, and since the second metal pillar is connected with the first metal pillar 8, the signal of the first chip 15 can be transmitted to the first metal pillar 8 through the second metal pillar, and then transmitted downward. And a second metal column connected with a bonding pad of the second chip 13 is marked as a second conduction column, and a circle of signal shielding structure surrounded by the second metal column is arranged around the second conduction column.

In concrete application, the front dielectric layer 9 is arranged on the ceramic substrate 1, the chip can be installed on the ceramic substrate 1 through the third through hole and can be installed on the front dielectric layer 9, the front dielectric layer 9 and the ceramic substrate 1 can be wired, the radio frequency microwave circuit board is convenient and clear to wire, the circuit board with the double-layer structure can divide the sensitive chip and other chips into two layers in different, meanwhile, the isolation wall is arranged on each layer, the isolation degree of the circuit of the whole chip is improved, and the performance of the radio frequency microwave circuit board is further improved. Meanwhile, the core plates of the multilayer circuit board have the temperature equalization function and high thermal conductivity, the second through holes of the front dielectric layer 9 are communicated with the first through holes 2 of the ceramic substrate 1 and are filled with copper, a heat dissipation channel is optimized, and a local heat source on the front dielectric layer 9 can be rapidly transmitted to the ceramic substrate 1 and conducted downwards.

In the embodiment of the present invention, when the upper surface of the ceramic substrate 1 is provided with at least two first chips 15, and at least two first chips 15 need to be connected through a resistor, the rf microwave circuit board further includes:

and the resistance layers are arranged between the two first chips 15 which need to be connected through the resistors on the ceramic substrate 1 and are respectively connected with the two first chips 15 which need to be connected through the resistors.

In the embodiment, the resistance layer is a metal layer for connecting the two first chips 15, and a high-precision resistor is disposed on the ceramic substrate 1, so that the integration density of the rf microwave circuit board is improved, and the resistance deviation of the resistance layer is within ± 1%.

As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:

the first front-side seed layer 3 is arranged between the ceramic substrate 1 and the front-side dielectric layer 9 and is positioned in a first preset area on the ceramic substrate 1 and the inner side wall of the first through hole 2, the first front-side seed layer 3 in the first preset area is used for arranging a first chip 15, and the filled metal is connected with the first through hole 2 through the first front-side seed layer 3;

the second front-side seed layer is arranged in a first preset area on the front-side dielectric layer 9 and on the inner side wall of the second through hole, the second front-side seed layer in the first preset area on the front-side dielectric layer 9 is used for arranging a second chip 13, the second front-side seed layer in the second preset area on the front-side dielectric layer 9 is used for arranging a metal enclosure frame 16, and the filled metal is connected with the second through hole through the second front-side seed layer;

correspondingly, a metal frame 16 is arranged on the second front-side seed layer for arranging the metal frame 16.

In this embodiment, the material of each of the first front-side seed layer 3 and the second front-side seed layer may be Ti, Ta, or Cu, and the thickness may be selected to satisfy the constraint condition of 50nm to 5000nm, and of course, the thicknesses of the first front-side seed layer 3 and the second front-side seed layer may also be set as required. The provision of the first front-side seed layer 3 makes it easier to provide the first chip 15 on the ceramic substrate 1. The provision of the second front-side seed layer makes it easier to provide the second chip 13 on the ceramic substrate 1. And also provides for the subsequent thickening of the chip placement area as well as other areas.

As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:

the first front-side conductor layer 6 is arranged between the first front-side seed layer 3 and the front-side dielectric layer 9 and is positioned on the first front-side seed layer 3, a first area of the first front-side conductor layer 6 is used for arranging a first chip 15, and a second area of the first front-side conductor layer 6 is used for thickening the first metal column 8;

the second front-side conductor layer 11 is arranged on the second front-side seed layer, a first area of the second front-side conductor layer 11 is used for arranging the second chip 13, a second area of the second front-side conductor layer 11 is used for thickening the second metal column, and a third area of the second front-side conductor layer 11 is used for arranging the metal enclosure frame 16;

accordingly, a metal enclosure frame 16 is disposed on the second front-side conductor layer 11 at a position for disposing the metal enclosure frame 16.

In the present embodiment, the thickness of each of the first front-side conductor layer 6 and the second front-side conductor layer 11 may be 15 to 20 μm, and the material of each of the first front-side conductor layer 6 and the second front-side conductor layer 11 may be copper. The first front side conductor layer 6 is arranged to allow the first chip 15 to be better connected to the ceramic substrate 1, and the second front side conductor layer 11 is arranged to allow the second chip 13 to be better connected to the front side dielectric layer 9. The first front conductor layer covers the ceramic substrate and the first metal column, and a complete coating structure is formed between the ceramic substrate and the first metal column, so that the air tightness is guaranteed. The second front conductor layer covers the front cut-off layer and the second metal column, and a complete coating structure is formed between the front dielectric layer and the second metal column, so that the air tightness is guaranteed.

As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:

the back dielectric layer 10 is arranged on the back of the ceramic substrate 1 in a hot pressing mode, a fourth through hole penetrating through the upper surface of the back dielectric layer 10 and the lower surface of the back dielectric layer 10 is formed in the back dielectric layer 10, metal is filled in the fourth through hole, the metal in the fourth through hole is marked as a fourth metal column, and the fourth metal column is connected with the first metal column 8.

In this embodiment, the lower surface of the back dielectric layer 10 is attached to the lower surface of the ceramic substrate 1, and the back dielectric layer 10 completely covers the lower surface of the ceramic substrate 1. The back dielectric layer 10 may be a wiring, and the back dielectric layer 10 may be a Liquid Crystal Polymer (LCP) having low microwave loss and good temperature stability. The diameter of the fourth through hole can be set between 70 and 125 micrometers, and the diameter of the fourth through hole meets the constraint condition: the ratio of the diameter of the fourth through hole to the thickness of the ceramic substrate 1 in the back dielectric layer 10 is 1: 1. And filling metal, wherein the metal can be copper, in the fourth through hole. The front dielectric layer 9, the ceramic substrate 1 and the back dielectric layer 10 form a circuit board with a three-layer dielectric four-layer conductor structure, so that wiring is simpler and clearer, and transmission loss is reduced.

As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:

the first back seed layer 4 is arranged between the ceramic substrate 1 and the back dielectric layer 10 and is positioned in a first preset area below the ceramic substrate 1;

and the second back seed layer is arranged on the first preset area below the back dielectric layer 10 and the inner side wall of the fourth through hole, and the filled metal is connected with the fourth through hole through the second back seed layer.

In this embodiment, the material of both the first back seed layer 4 and the second back seed layer may be Ti or Cu, and the thickness may be selected to satisfy the constraint condition of 50nm to 5000nm, and of course, the thicknesses of the first back seed layer 4 and the second back seed layer may also be set as required.

As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:

the first back conductor layer 7 is arranged between the first back seed layer 4 and the back dielectric layer 10 and is positioned below the first back seed layer 4, and a first area of the first back conductor layer 7 is used for thickening the first metal column 8;

and a second back side conductor layer 12 disposed under the second back side seed layer, wherein a first region of the second back side conductor layer 12 is used for thickening the fourth metal pillar.

In the present embodiment, the thickness of each of the first back side conductor layer 7 and the second back side conductor layer 12 may be 15 to 20 μm, and the material of each of the first back side conductor layer 7 and the second back side conductor layer 12 may be copper. The first back conductor layer is arranged below the ceramic substrate and the first metal column, and a complete coating structure is formed between the ceramic substrate and the first metal column, so that the air tightness is guaranteed. The second back conductor layer is arranged below the back dielectric layer and the fourth metal column, and a complete coating structure is formed between the back dielectric layer and the fourth metal column, so that the air tightness is guaranteed.

As shown in fig. 1, in the embodiment of the present invention, the solder mask layer 14 is further included, and is disposed on the lower surface of the ceramic substrate, and is disposed in a region other than the assembly bonding pad or the heat conduction post 18 except for the first through hole.

When the back dielectric layer is provided, the solder resist layer 14 is provided on the lower surface of the back dielectric layer 10 in a region other than the fourth through hole. The provision of the solder mask layer 14 facilitates assembly with other components.

As shown in fig. 15, in the embodiment of the present invention, the front surface of the cover plate 19 may be further provided with heat dissipation fins 20.

In the present embodiment, the heat dissipation fins 20 are directly formed on the cover plate 19, which is beneficial to heat dissipation of the second chip 13. When the heat dissipation fins 20 are provided on the cover plate 19, the bottom of the second chip 13 is connected to the metal enclosure frame 16, and heat is transferred upward to the heat dissipation fins 20 through the metal enclosure frame 16.

The utility model discloses an in the embodiment, the front of apron 19 can also be equipped with the antenna, is equipped with apron 19 through-hole on the apron 19, and the metal is filled in the 19 through-holes of apron, and the metal in the 19 through-holes of apron is marked as apron 19 metal column. The antenna is connected to the metal post of the cover plate 19 in a through hole of the cover plate 19. The lower end of the metal column of the cover plate 19 is connected with the first end of the spring column, and the second end of the spring column is connected with the second chip 13. The spring posts are fabricated within the metal enclosure 16. The second end of the spring column is connected with the second chip 13 or the second metal seed layer or the second surface conductor layer under the second chip 13 by welding. The first end of the spring post is fastened to the cover plate 19.

In this embodiment, the antenna is directly formed on the cover plate 19, and the lower surface of the antenna is attached to the upper surface of the cover plate 19. In order to avoid the radiation effect of the antenna on the chip, a shielding layer made of a metal material, such as copper, is provided on the back surface of the cover plate 19.

As shown in fig. 15, in the embodiment of the present invention, the present invention further includes:

and the coupling structure 21 is arranged on the back surface of the cover plate 19 and is positioned above the second chip 13 to be coupled.

In the present embodiment, the coupling structure 21 is a planar structure or a stepped structure.

In actual manufacturing, the coupling structure 21 can be obtained by photolithography, deposition and lift-off, and the coupling structure 21 can be a metal material, such as copper, in the same way as the antenna is manufactured on the upper side.

As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:

and the copper heat-conducting columns 18 are arranged on the back surface of the ceramic substrate 1, wherein at least a preset number of copper heat-conducting columns 18 are used as input and output pins of the packaging device and are connected with the first metal columns 8.

In the present embodiment, the copper heat-conducting pillars 18 on the back surface of the ceramic substrate 1 satisfy the following constraint conditions: the height of the copper heat-conducting column 18 is 200 and 1000 microns, and the precision of the copper heat-conducting column 18 is +/-5 microns.

The embodiment of the utility model provides an in, can have partly copper heat conduction post 18 direct with ceramic substrate 1 links to each other, and the copper heat conduction post 18 that is connected with ceramic substrate 1 can be with the heat effluvium on the ceramic substrate 1 on the one hand, and on the other hand can play the supporting role to holistic encapsulation shell, and is more stable when making encapsulation shell link to each other with other structures. The copper heat-conducting column 18 connected with the first metal column 8 serves as a packaging I/O leading-out end and can serve as a heat dissipation channel to help the packaging device dissipate heat, and on the other hand, the copper heat-conducting column can buffer the thermal stress of the packaging device and the PCB installation mother board and avoid cracking caused by thermal mismatch when the packaging device is connected with the PCB installation mother board.

Of course, if a second back seed layer is provided, the copper thermal conductive pillar 18 is disposed under the second back seed layer, and if a second back conductor layer 12 is provided, the copper thermal conductive pillar 18 is disposed under the second back conductor layer 12.

Fig. 2 to fig. 15 are schematic structural diagrams corresponding to respective steps in another process flow for manufacturing a packaged device according to an embodiment of the present application.

First, a first through hole 2 is formed in a ceramic substrate 1, wherein the first through hole 2 penetrates through an upper surface and a lower surface of the ceramic substrate 1. A cross-sectional view of the ceramic substrate 1 after the first through-hole 2 is formed can be seen in fig. 2, and a top view of the ceramic substrate 1 after the first through-hole 2 is formed can be seen in fig. 3.

Secondly, depositing metal on the front surface of the ceramic substrate 1 and the inner side wall of the first through hole 2 to form a first front surface seed layer 3, and reserving positions for arranging a first chip 15, a metal enclosure frame 16 and an isolation wall 17 on the first front surface seed layer 3, which can be specifically shown in fig. 4.

In the present embodiment, the surface of the ceramic substrate 1 and the first via hole 2 are subjected to a cleaning process before the first front-side seed layer 3 is deposited. The first front seed layer 3 is deposited on the front surface of the ceramic substrate 1 by physical vapor deposition or chemical vapor deposition.

Thirdly, metal is injected into the first through hole 2 of the ceramic substrate 1 deposited with the first front-side seed layer 3, and a first metal column 8 penetrating through the upper surface and the lower surface of the ceramic substrate 1 is formed.

In practical application, the first front-side conductor layer 6 can be prepared on the first front-side seed layer 3 while injecting metal into the first through hole 2. As shown with particular reference to fig. 5-7.

Preparing a first front conductor layer 6 on the first front seed layer 3 by an electrochemical deposition method, wherein a position for arranging a first chip 15 is reserved in a first area of the first front conductor layer 6, a second area of the first front conductor layer 6 is used for thickening the first metal column 8, a third area of the first front conductor layer 6 is used for arranging a metal enclosure frame 16, and a fourth area of the first front conductor layer 6 is used for arranging a separation wall 17.

In the embodiment of the present application, the specific method for preparing the first front-side conductor layer 6 and the first metal stud 8 is as follows: coating a first photoresist layer 5 on the first front seed layer 3 by spin coating or film-coating hot pressing, then performing standard photoetching processes such as exposure and development on the position of the first photoresist layer 5 where the first front conductor layer 6 is required to be prepared to obtain a conductor layer through hole for preparing the first front conductor layer 6, and finally depositing metal in the position of the conductor layer through hole on the first photoresist layer 5 and the first through hole 2 by an electrochemical deposition method, specifically applying pulse plating and direct current plating for combined use during metal filling, so that the efficiency can be improved under the condition that no cavity exists in copper deposition in the first through hole 2. After the first through hole 2 is filled, metal is continuously accumulated on the first through hole 2 until the surface protrudes to form a first front conductor layer 6, finally, the first photoresist layer 5 is removed by adopting a standard stripping process to obtain the first front conductor layer 6, and the metal in the first through hole 2 is a first metal column 8.

The first front conductor layer 6 is manufactured by adopting a semiconductor photoetching process, so that the line precision is high, the impedance matching performance is good, and the loss is low. The material of the first photoresist layer 5 can be high-viscosity photoresist or high-resolution photosensitive dry film, and the first photoresist layer 5 satisfies the constraint condition: the thickness is larger than 15 microns, the line resolution is smaller than 10 microns, and the inner side wall of the conductor layer through hole obtained after the first photoresist layer 5 is exposed is steep.

After the first front-side conductor layer 6 is prepared, in order to obtain the first front-side conductor layer 6 with a preset thickness and also in order to obtain the first front-side conductor layer 6 with higher precision and lower surface roughness, thickness reduction and polishing treatment can be performed on the first front-side conductor layer 6.

Specifically, during manufacturing, the first front-side conductor layer 6 may be thinned, some scratches may exist during the grinding process, and the first front-side conductor layer 6 needs to be polished continuously to reduce the surface roughness of the first front-side conductor layer 6 and reduce the transmission loss of the circuit.

Fourthly, the first front seed layer 3 is removed except for the position corresponding to the first front conductor layer 6 and the reserved position where the resistance layer is disposed on the ceramic substrate 1, as shown in fig. 8.

In this embodiment, the first front-side seed layer 3 except the position corresponding to the first front-side conductor layer 6 and the reserved position where the resistance layer is disposed is removed by a method of photolithography and then etching, so that the first front-side seed layer 3 at the reserved position of the resistance layer is not removed, and the first front-side seed layer 3 at the reserved position of the resistance layer is marked as the resistance layer.

Finally, the first front conductor layer 6 and the first back conductor layer 7 on the surface can be protected by adopting a mode of electroless nickel gold plating, so that the environmental tolerance is improved.

In practical applications, of course, if the first front-side conductive layer 6 is not formed, the first front-side seed layer 3 on the region other than the region where the first chip 15 to be packaged, the metal frame 16 and the isolation wall 17 are attached may be removed.

Fifthly, hot-pressing the front dielectric layer 9 on the ceramic substrate 1, and preparing a second through hole on the front dielectric layer 9, wherein the second through hole is communicated with the first through hole 2, as shown in fig. 9-10.

In this embodiment, the front dielectric layer 9 is formed on the ceramic substrate 1 by hot pressing, and the front dielectric layer 9 is made of a liquid crystal polymer, which has a certain fluidity, and flattens the surface of the ceramic substrate 1 again. When the second through hole is prepared on the front dielectric layer 9, the aluminum nitride of the ceramic substrate 1 is used as a target, picosecond cold laser processing drilling can be adopted at the vertical interconnection position, namely the position corresponding to the first through hole 2, and the processed second through hole penetrates through the upper surface and the lower surface of the front dielectric layer 9. The second through hole prepared by the method has smooth hole wall, high verticality and accurate hole position.

Sixthly, depositing metal on the front surface of the front dielectric layer 9 and the inner side wall of the second through hole to form a second front seed layer, and reserving a position for arranging a second chip 13 on the second front seed layer.

In this embodiment, the surface of the front side dielectric layer 9 and the second via hole are cleaned before depositing the second front side seed layer. The second front-side seed layer is deposited on the front side of the front-side dielectric layer 9 by physical vapor deposition or chemical vapor deposition.

Seventhly, injecting metal into the second through hole of the front dielectric layer 9 deposited with the second front seed layer to form a second metal column penetrating through the upper surface and the lower surface of the front dielectric layer 9, as shown in fig. 11.

In the present embodiment, the function of filling metal in the second via hole is the same as the function of filling metal in the first via hole 2.

In the specific manufacturing process, if necessary, the second front-side conductor layer 11 is prepared on the second front-side seed layer by electrochemical deposition while filling metal into the second through hole.

The specific method of preparing the second front-side conductor layer 11 is the same as the method of preparing the first front-side conductor layer 6 in the third embodiment. Reference may be made to the method of manufacturing the first front-side conductor layer 6.

And after the second front-side conductor layer 11 is prepared, removing the second front-side seed layer on the region except the position of the second front-side conductor layer 11 on the front-side dielectric layer 9. In practical application, if the second front-side conductor layer 11 is not formed, the area for forming the metal enclosure frame 16, the area for forming the isolation wall 17, the area for surface mounting the second chip 13 to be packaged, the area of the signal shielding structure around the second conductive via, and the second front-side seed layer in other areas than the area for forming the isolation wall 17 may be removed, as shown in fig. 11.

In this embodiment, the second front-side conductor layer 11 may be thinned, some scratches may exist in the process of grinding, and the second front-side conductor layer 11 needs to be polished continuously to reduce the surface roughness of the second front-side conductor layer 11 and reduce the transmission loss of the circuit.

In practical application, the copper heat-conducting column 18 can be prepared at a position where the copper heat-conducting column 18 is reserved on the back surface of the ceramic substrate 1, wherein the position where the copper heat-conducting column 18 is reserved includes: the back surface of the ceramic substrate 1 corresponds to the first metal posts 8, as shown in fig. 12.

In this embodiment, the copper heat-conducting pillar 18 can be prepared by coating a second photoresist layer on the back surface of the ceramic substrate 1, performing photolithography on the second photoresist layer to form a heat-conducting pillar pattern, depositing metal in the heat-conducting pillar pattern, and stripping the second photoresist layer to obtain the copper heat-conducting pillar 18.

Specifically, during the manufacturing process, the copper heat-conducting pillar 18 may be thinned, and during the grinding process, there may be some scratches, and it is also necessary to continue to polish the copper heat-conducting pillar 18 to reduce the roughness of the copper heat-conducting pillar 18. The Z-phase height of the conductive column is controlled within + -5 μm after the grinding and polishing processes.

Eighthly, a third through hole penetrating through the upper surface and the lower surface of the front dielectric layer 9 is prepared on the front dielectric layer 9, as shown in fig. 13.

In the present embodiment, the third through hole is a blind hole provided between the front dielectric layer 9 and the ceramic substrate 1. Picosecond cold laser machining drilling can be adopted.

Ninthly, welding the metal enclosure frame 16 to the ceramic substrate 1 by brazing at a position where the metal enclosure frame 16 is reserved on the upper surface of the ceramic substrate 1, as shown in fig. 13.

Specifically, the metal enclosure frame 16 may be soldered to the ceramic substrate 1 at a high temperature of 200 to 350 ℃ using tin-based or eutectic solder at a position for disposing the metal enclosure frame 16. If the second front-side conductor layer 11 is provided, the metal enclosure frame 16 is welded to the second front-side conductor layer 11.

In a specific application, the metal enclosure frame 16 and the partition wall 17 may be manufactured together at the same time of manufacturing the metal enclosure frame 16, and both the metal enclosure frame 16 and the partition wall 17 may be formed by coating a third photoresist layer on the second front-side conductor layer 11, etching the patterns of the metal enclosure frame 16 and the partition wall 17 on the third photoresist layer, depositing metal on the patterns of the metal enclosure frame 16 and the partition wall 17, and finally obtaining the metal enclosure frame 16 and the partition wall 17 by stripping the third photoresist layer.

In this embodiment, during actual manufacturing, the upper surfaces of the metal enclosure frame 16 and the isolation wall 17 may be thinned, some scratches may exist during the grinding process, and the upper surfaces of the metal enclosure frame 16 and the isolation wall 17 need to be polished to reduce the surface roughness. In this embodiment, the spatial coupling of the hermetically packaged device can be reduced by precisely controlling the heights of the metal peripheral walls and the internal separation walls 17 through plating thickening and CMP thinning processes.

Tenth, the first chip 15 is prevented from being placed in the third through hole, the first chip 15 placed in the third through hole is mounted at a position where the first chip 15 is reserved on the ceramic substrate 1, and the bonding pad of the first chip 15 is connected with the second metal pillar through a bonding wire. As shown in fig. 14.

In the present embodiment, if the first front side seed layer 3 is provided on the ceramic substrate 1, the first chip 15 is provided on the first front side seed layer 3.

If the ceramic substrate 1 is provided with the first front-side seed layer 3 and the first front-side conductor layer 6, the first chip 15 is provided on the first front-side conductor layer 6.

Eleventh, mounting a second chip 13 on the front dielectric layer 9, and connecting a pad of the second chip 13 with the second metal pillar through a bonding wire, as shown in fig. 14.

Twelfth, the cover plate 19 is sealed on the upper surfaces of the metal enclosure frame 16 and the partition wall 17 by welding, so as to form a hermetic package structure, as shown in fig. 14.

Thirteenth, a solder resist layer 14 is prepared on the back surface of the ceramic substrate 11 as shown in fig. 1.

In the present embodiment, a nickel-gold electroless plating method is adopted to protect the surface metal portion on the back surface of the ceramic substrate 1, and the solder mask layer 14 is prepared on the other region except the position where the copper heat-conducting pillar 18 is reserved. The solder mask layer 14 is prepared to facilitate assembly of the rf microwave circuit board with other components.

In the specific manufacturing process, when the front dielectric layer 9 is prepared, the back dielectric layer 10 can be hot-pressed on the back surface of the ceramic substrate 1, a fourth through hole is prepared on the back dielectric layer 10, metal is filled in the fourth through hole, the metal in the fourth through hole is marked as a fourth metal column, and the fourth metal column is connected with the first metal column 8.

Specifically, the specific method for forming the fourth through hole in the back dielectric layer 10 is the same as the method for forming the second through hole in the front dielectric layer 9, and reference may be made to the method for forming the second through hole. The method of filling the metal paste in the fourth via is the same as the method of filling the metal paste in the second via, and reference may be made to the method of filling the metal paste in the second via.

In the fabrication process, the first back seed layer 4 may be fabricated on the back side of the ceramic substrate 1, and the first back conductor layer 7 may be deposited under the first back seed layer 4 and under the first metal pillar 8. A second back side seed layer may be deposited on the lower surface of the back side dielectric layer 10 and in the fourth via, and a second back side conductor layer 12 is deposited on the back side of the second back side seed layer and under the fourth metal pillar. The preparation methods of the back seed layer and the back conductor layer can refer to the preparation methods of the front seed layer and the front conductor layer. Accordingly, a copper thermally conductive post 18 is disposed beneath the second back conductor layer 12.

As shown in fig. 15, in practical applications, it is of course possible to fabricate heat dissipation fins 20 on the front surface of the cover plate 19 before the cover plate 19 is sealed on the upper surface of the metal enclosure frame 16.

Specifically, the method for manufacturing the heat dissipation fin 20 includes manufacturing a fourth photoresist layer on the front surface of the cover plate 19 by spin coating or film coating hot pressing, etching through holes for manufacturing the heat dissipation fin 20 on the fourth photoresist layer, depositing metal on the positions of the through holes for manufacturing the heat dissipation fin 20 etched on the fourth photoresist layer, and removing the fourth photoresist layer to obtain the heat dissipation fin 20.

In a specific application, when the heat dissipation fins 20 are fabricated, the bottom of the second chip 13 is connected to the metal enclosure frame 16, and if the second chip 13 is fabricated on the second front-side seed layer, the second front-side seed layer under the second chip 13 is connected to the metal enclosure frame 16, and the heat is transferred to the metal enclosure frame 16 through the second front-side seed layer and transferred upward to the heat dissipation fins 20 through the metal enclosure frame 16. If the second chip 13 is fabricated on the second front side conductor layer 11, the second front side conductor layer 11 and the second front side seed layer under the second chip 13 may be connected to the metal enclosure frame 16, or the second front side seed layer may be connected to the metal enclosure frame 16.

In the embodiment of the present invention, before the cover plate 19 is sealed on the upper surfaces of the metal enclosure frame 16 and the partition wall 17, an antenna may be further manufactured on the front surface of the cover plate 19.

Specifically, the method for manufacturing the antenna includes manufacturing a fifth photoresist layer on the front surface of the cover plate 19 by spin coating or film-coating hot pressing, etching a pattern for manufacturing the antenna on the fifth photoresist layer, depositing metal on the position of the pattern for manufacturing the antenna etched on the fifth photoresist layer, and removing the fifth photoresist layer to obtain the antenna.

In specific application, when the antenna is manufactured, a picosecond cold laser machining drilling method can be adopted on the cover plate 19, a through hole of the cover plate 19 is machined, metal slurry is deposited in the through hole of the cover plate 19, the metal slurry in the through hole of the cover plate 19 is marked as a metal column of the cover plate 19, and the antenna is connected with the metal column of the cover plate 19 in the through hole of one cover plate 19.

Correspondingly, spring columns are further mounted in the metal enclosure frame 16, and second ends of the spring columns are connected with the second chip 13 or the front seed layer or the front conductor layer below the second chip 13 through welding. The first end of the spring post is fastened with the cover plate 19, and the first end of the spring post is connected with the lower end of the metal post of the cover plate 19 connected with the antenna.

In a specific application, in order to avoid radiation of the antenna to the second chip 13, a shielding layer is provided on the back surface of the cover plate 19, and the shielding layer is obtained by depositing a shielding material, and the shielding layer may be metallic copper. Or a sixth photoresist layer is manufactured on the back surface of the cover plate 19 in a spin coating or film-covering hot pressing mode, a pattern for manufacturing the shielding layer is etched on the sixth photoresist layer by etching the sixth photoresist layer, a shielding material is deposited on the pattern for manufacturing the shielding layer, and finally the sixth photoresist layer is removed to obtain the shielding layer.

In practical applications, a coupling structure 21 may be further disposed on the back surface of the cover plate 19 above the second chip 13, and the coupling structure 21 may be a planar structure or a step structure.

In practical application, the air tightness of the airtight packaging structure can be further verified, and whether the airtight packaging structure is qualified or not is further judged.

Specifically, the hermetic package structure is placed in a leak-tight vessel, which is filled with helium and pressurized at 0.5 Mpa. And after 4 hours, taking out the airtight packaging structure, performing rough detection by adopting a leakage detection liquid soaking method, and if no bubble is generated on the surface of the leakage detection liquid, determining that the airtight packaging structure is qualified, otherwise, determining that the airtight packaging structure is not qualified. And finally, performing fine inspection on the qualified airtight packaging structure by using a helium mass spectrometer, and if the leak detector shows that the helium flow is lower than 1 × 10-9pa.cm < 3 >/s, the airtight packaging structure is qualified, otherwise, the airtight packaging structure is not qualified.

The steps in the above first to thirteenth may be deleted or recombined according to actual needs.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (10)

1. A hermetically packaged device, comprising:

the packaging shell adopts a ceramic substrate as a packaging bottom plate, the ceramic substrate is provided with a first through hole penetrating through the upper surface of the ceramic substrate and the lower surface of the ceramic substrate, metal is filled in the first through hole of the ceramic substrate, and the metal in the first through hole is marked as a first metal column;

the at least two first chips are arranged inside the packaging shell and arranged on the ceramic substrate, and bonding pads of the first chips are connected with the first metal columns on the ceramic substrate through bonding wires;

and the isolation wall is arranged in the packaging shell and divides the packaging shell into different airtight cavities, and the first chip to be isolated is arranged in the different airtight cavities.

2. The hermetically sealed device of claim 1, wherein the package housing further comprises:

the metal enclosure frame is arranged at the position, used for arranging the metal enclosure frame, on the ceramic substrate;

and the cover plate is welded on the metal enclosure frame and the isolation wall.

3. The hermetically sealed device of claim 2, wherein the package housing further comprises:

the front dielectric layer is arranged on the upper surface of the ceramic substrate in a hot pressing mode; the front dielectric layer is provided with a second through hole and a third through hole which penetrate through the upper surface of the front dielectric layer and the lower surface of the front dielectric layer, metal is filled in the second through hole, the metal in the second through hole is marked as a second metal column, the upper surface of the front dielectric layer is provided with a second chip, a bonding pad of the second chip is connected with at least one second metal column through a bonding wire, and the second metal column is connected with the first metal column;

correspondingly, the first chip is arranged in the third through hole, the first chip is arranged on the upper surface of the ceramic substrate, and a bonding pad of the first chip is connected with the second metal column through a bonding wire;

correspondingly, the isolation wall is arranged in the packaging shell, the packaging shell is divided into different airtight cavities on the front dielectric layer, and the first chip and the second chip to be isolated are arranged in the different airtight cavities;

correspondingly, the metal enclosure frame is arranged on the front dielectric layer and used for arranging the metal enclosure frame.

4. The hermetically packaged device of claim 3, further comprising:

the first front surface seed layer is arranged between the ceramic substrate and the front surface dielectric layer, is positioned in a first preset area on the ceramic substrate and is positioned on the inner side wall of the first through hole, and is used for arranging a first chip, wherein the filled metal is connected with the first through hole through the first front surface seed layer;

the second front surface seed layer is arranged in a first preset area on the front surface dielectric layer and the inner side wall of the second through hole, the second front surface seed layer of the first preset area on the front surface dielectric layer is used for arranging a second chip, the second front surface seed layer of the second preset area on the front surface dielectric layer is used for arranging a metal enclosure frame, and the filled metal is connected with the second through hole through the second front surface seed layer;

correspondingly, the metal enclosure is arranged on the second front-side seed layer and used for arranging the metal enclosure.

5. The hermetically packaged device of claim 4, further comprising:

the first front side conductor layer is arranged between the first front side seed layer and the front side dielectric layer and is positioned on the first front side seed layer, a first area of the first front side conductor layer is used for arranging a first chip, and a second area of the first front side conductor layer is used for thickening the first metal column;

the second front-side conductor layer is arranged on the second front-side seed layer, a first area of the second front-side conductor layer is used for arranging a second chip, a second area of the second front-side conductor layer is used for thickening the second metal column, and a third area of the second front-side conductor layer is used for arranging a metal enclosure frame;

correspondingly, the metal enclosure frame is arranged at the position, used for arranging the metal enclosure frame, on the second front conductor layer.

6. The hermetically packaged device of claim 1, further comprising:

the back dielectric layer is arranged on the back of the ceramic substrate in a hot pressing mode, a fourth through hole penetrating through the upper surface of the back dielectric layer and the lower surface of the back dielectric layer is formed in the back dielectric layer, metal is filled in the fourth through hole, the metal in the fourth through hole is marked as a fourth metal column, and the fourth metal column is connected with the first metal column.

7. The hermetically packaged device of claim 6, further comprising:

the first back seed layer is arranged between the ceramic substrate and the back dielectric layer and positioned in a first preset area below the ceramic substrate, and the first back seed layer in the first preset area is used for growing a first back conductor layer;

the first back conductor layer is arranged between the first back seed layer and the back dielectric layer and positioned below the first back seed layer, and the first back conductor layer is used for thickening the first metal column.

8. The hermetically packaged device of claim 7, further comprising:

the second back surface seed layer is arranged on the inner side wall of the fourth through hole and at a position below the back surface dielectric layer and corresponding to the first preset area of the substrate, and the filled metal is connected with the fourth through hole through the second back surface seed layer;

and the second back conductor layer is arranged below the second back seed layer and is used for thickening the fourth metal column.

9. The hermetically packaged device of claim 8, further comprising:

and the solder mask layer is arranged on the lower surface of the back dielectric layer and is positioned in the area outside the fourth metal column.

10. The hermetically packaged device of claim 2, further comprising:

and the radiating fins are arranged on the front surface of the cover plate.

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