CN210956116U - Pixel circuit and display device - Google Patents
Pixel circuit and display device Download PDFInfo
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- CN210956116U CN210956116U CN201922245223.5U CN201922245223U CN210956116U CN 210956116 U CN210956116 U CN 210956116U CN 201922245223 U CN201922245223 U CN 201922245223U CN 210956116 U CN210956116 U CN 210956116U
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Abstract
The utility model relates to a pixel circuit and display device. The pixel circuit includes: the device comprises a data writing module, a latching module, a driving module, a current collecting module, a comparing module and a compensating module. The first end of the latch module is electrically connected with the first end of the data writing module, the second end of the latch module is electrically connected with the control end of the driving module, the first end of the driving module is electrically connected with the first end of the light-emitting element, the first end of the current acquisition module is electrically connected with the first end of the driving module, the second end of the current acquisition module is electrically connected with the first end of the comparison module, the second end of the comparison module is electrically connected with the first end of the compensation module, and the second end of the compensation module is electrically connected with the second end of the data writing module. According to the utility model discloses an embodiment can reduce pixel circuit's circuit area, moreover, can improve pixel circuit's stability.
Description
Technical Field
The utility model relates to a OLED display device technical field especially relates to a pixel circuit and display device.
Background
A pixel of an OLED (Organic Light-Emitting Diode) display device generally includes an OLED Light-Emitting element (i.e., a pixel) and a pixel circuit for driving the Light-Emitting element to emit Light. The pixel circuit may include at least one transistor. However, the long-term operation of the display device may cause the gate leakage of the transistor and the voltage drop fluctuation, which may result in the OLED light emitting device not being able to operate stably.
SUMMERY OF THE UTILITY MODEL
The utility model provides a pixel circuit and display device to solve not enough in the correlation technique.
According to a first aspect of the embodiments of the present invention, there is provided a pixel circuit, including: the device comprises a data writing module, a latching module, a driving module, a current acquisition module, a comparison module and a compensation module;
the first end of the latch module is electrically connected with the first end of the data writing module, the second end of the latch module is electrically connected with the control end of the driving module, the first end of the driving module is electrically connected with the first end of the light-emitting element, the first end of the current acquisition module is electrically connected with the first end of the driving module, the second end of the current acquisition module is electrically connected with the first end of the comparison module, the second end of the comparison module is electrically connected with the first end of the compensation module, and the second end of the compensation module is electrically connected with the second end of the data writing module;
the data write module is configured to write a first data voltage to the latch module, the latch module is configured to latch the first data voltage, the driving module is configured to output a first driving current according to the first data voltage, the current collecting module is configured to collect the first driving current, the comparison module is configured to obtain a present voltage across the light emitting element according to the first driving current, and comparing a preset voltage with the current voltage to output a comparison result, the compensation module being configured to generate a second data voltage according to the comparison result and output the second data voltage to the data writing module, and the driving module outputs a second driving current according to the second data voltage, and the voltage at two ends of the light-emitting element is the preset voltage.
In one embodiment, the control end of the data writing module is connected to a scanning signal line; the data writing module comprises a first transistor, wherein a first end of the first transistor is connected to a first end of the data writing module, a second end of the first transistor is connected to a second end of the data writing module, and a control end of the first transistor is connected to a control end of the data writing module.
In one embodiment, the latch module comprises a first inverter and a second inverter; the input end of the first phase inverter is connected to the first end of the latch module, the output end of the first phase inverter is connected to the second end of the latch module, the input end of the second phase inverter is connected to the second end of the latch module, and the output end of the second phase inverter is connected to the first end of the latch module.
The latch module comprises a first inverter and a second inverter which are connected end to form a loop, so that the written data voltage can be latched. Since the area of the latch module of this configuration does not increase with an increase in the storage capacity, the circuit area of the pixel circuit can be reduced, and since the latch module has good stability, the stability of the pixel circuit can be improved.
In one embodiment, the latch module further comprises a control terminal; the latch module comprises a third inverter, a fourth inverter, a first tri-state gate and a second tri-state gate; the input end of the first tri-state gate is connected to the first end of the latch module, the first control end of the first tri-state gate is connected to the output end of the third inverter, the second control end of the first tri-state gate is connected with the first control end of the second tri-state gate in parallel and then connected to the input end of the third inverter, and the output end of the first tri-state gate is connected with the output end of the second tri-state gate in parallel and then connected to the input end of the fourth inverter; the output end of the fourth inverter is connected to the input end of the second tri-state gate; the input end of the third inverter is connected to the control end of the latch module; the output end of the third inverter is further connected to the second control end of the second tri-state gate, and the input end of the second tri-state gate is connected to the second end of the latch module.
The latch module comprises a third inverter, a fourth inverter, a first tri-state gate and a second tri-state gate, wherein the third inverter and the fourth inverter are connected end to form a loop, so that the written data voltage can be latched. Since the area of the latch module of this configuration does not increase with an increase in the storage capacity, the circuit area of the pixel circuit can be reduced, and since the latch module has good stability, the stability of the pixel circuit can be improved.
In one embodiment, the second terminal of the driver module is connected to a first power signal line; the driving module comprises a second transistor, a control end of the second transistor is connected to a control end of the driving module, a first end of the second transistor is connected to a first end of the driving module, and a second end of the second transistor is connected to a second end of the driving module.
In one embodiment, the third end of the current collection module is connected to the first power signal line, and the enable end of the current collection module is connected to the enable signal line; the current collection module comprises a current mirror, the first end of the current mirror is connected to the first end of the current collection module, the second end of the current mirror is connected to the second end of the current collection module, the third end of the current mirror is connected to the third end of the current collection module, and the enabling end of the current mirror is connected to the enabling end of the current collection module.
Because the current mirror can copy the first driving current output by the driving module, accurate current data can be acquired.
The current mirror comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the first end of the third transistor is connected to the third end of the current mirror, the second end of the third transistor is connected to the first end of the fifth transistor, and the node where the control end of the third transistor is connected with the control end of the fourth transistor is connected to the first end of the sixth transistor; a first terminal of the fourth transistor is connected to the third terminal of the current mirror, and a second terminal of the fourth transistor is connected to the first terminal of the sixth transistor; a node of the connection of the control terminal of the fifth transistor and the control terminal of the sixth transistor is connected to the second terminal of the sixth transistor, and the second terminal of the fifth transistor is connected to the first terminal of the seventh transistor; a second terminal of the sixth transistor is connected to a first terminal of the eighth transistor, and a second terminal of the eighth transistor is connected to a first terminal of the current mirror; a second terminal of the seventh transistor is connected to a second terminal of the current mirror; and the control end of the seventh transistor is connected with the control end of the eighth transistor in parallel and then connected to the enabling end of the current mirror.
In one embodiment, the comparison module comprises a comparator and a capacitor; the first end of the comparator is connected to the first end of the comparison module, the second end of the comparator is connected to the storage module for storing the preset voltage, the third end of the comparator is connected to the second end of the comparison module, and the capacitor is connected between the first end of the comparator and the third end of the comparator in series.
In one embodiment, the compensation module comprises an analog-to-digital converter; the first end of the analog-to-digital converter is connected to the first end of the compensation module, and the second end of the analog-to-digital converter is connected to the second end of the compensation module.
In one embodiment, the pixel circuit further includes a first reset module; the first end of the first reset module is connected to the second end of the latch module, the second end of the first reset module is connected to the first power signal line, and the control end of the first reset module is connected to the reset signal line; the first reset module comprises a ninth transistor, a first end of the ninth transistor is connected to the first end of the first reset module, a second end of the ninth transistor is connected to the second end of the first reset module, and a control end of the ninth transistor is connected to the control end of the first reset module.
The first end of the first reset module is connected to the second end of the latch module, and the first reset module can reset the latch module, so that the influence of the residual data voltage on the accuracy of the data voltage written into the latch module can be avoided.
In one embodiment, the first reset module includes a ninth transistor, a first terminal of the ninth transistor is connected to the first terminal of the first reset module, a second terminal of the ninth transistor is connected to the second terminal of the first reset module, and a control terminal of the ninth transistor is connected to the control terminal of the first reset module.
In one embodiment, the pixel circuit further comprises a second reset module; a first end of the second reset module is connected with a first end of the driving module in parallel and then connected to a first end of the light-emitting element, a second end of the second reset module is connected to a second power signal line, and a control end of the second reset module is connected to a reset signal line; a second end of the light emitting element is connected to the second power supply signal line; the second reset module comprises a tenth transistor, a first end of the tenth transistor is connected to the first end of the second reset module, a second end of the tenth transistor is connected to the second end of the second reset module, and a control end of the tenth transistor is connected to the control end of the second reset module.
Because the first end of the second reset module is connected to the first end of the light-emitting element, the second reset module can reset the light-emitting element, and the residual light of the light-emitting element is avoided to avoid influencing the light-emitting quality of the light-emitting element.
According to a second aspect of the embodiments of the present invention, there is provided a display device including the pixel circuit described above.
According to the above embodiments, since the latch module is connected in series between the data write module and the driving module, the latch module can latch the first data voltage written by the data write module, and since the area of the latch module does not increase with the increase of the storage capacity, the circuit area of the pixel circuit can be reduced, and since the latch module has good stability, the stability of the pixel circuit can be improved. Meanwhile, the first end of the current collection module is electrically connected with the first end of the driving module, the second end of the current collection module is electrically connected with the first end of the comparison module, the second end of the comparison module is electrically connected with the first end of the compensation module, and the second end of the compensation module is electrically connected with the second end of the data writing module, so that the current collection module can collect the current first driving current and feed the current first driving current back to the comparison module, the comparison module can obtain the current voltages at the two ends of the light-emitting element according to the first driving current and compare the preset voltage with the current voltage to output a comparison result, and the comparison result can be a difference value between the preset voltage and the current voltage. When the comparison result meets the preset condition, the compensation module can generate a second data voltage according to the comparison result and output the second data voltage to the data writing module, so that the driving module outputs a second driving current according to the second data voltage, and the voltages at the two ends of the light-emitting element are adjusted to be preset voltages.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a block diagram illustrating a pixel circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 3 is a timing diagram illustrating an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 5 is a block diagram illustrating another pixel circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 7 is a timing diagram according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
An embodiment of the utility model provides a pixel circuit. As shown in fig. 1, the pixel circuit 1 includes: the device comprises a data writing module 11, a latching module 12, a driving module 13, a current collecting module 14, a comparing module 15 and a compensating module 16.
As shown in fig. 1, a first end of the latch module is electrically connected to a first end of the data writing module, a second end of the latch module is electrically connected to a control end of the driving module, the first end of the driving module is electrically connected to a first end of the light emitting element 2, the first end of the current collection module is electrically connected to the first end of the driving module, the second end of the current collection module is electrically connected to a first end of the comparison module, the second end of the comparison module is electrically connected to a first end of the compensation module, and the second end of the compensation module is electrically connected to a second end of the data writing module.
The data writing module is configured to write a first data voltage into the latch module, the latch module is configured to latch the first data voltage, the driving module is configured to output a first driving current according to the first data voltage, the current collecting module is configured to collect the first driving current, the comparing module is configured to obtain a current voltage across the light-emitting element according to the first driving current and compare the preset voltage with the current voltage to output a comparison result, the compensating module is configured to generate a second data voltage according to the comparison result and output the second data voltage to the data writing module, so that the driving module outputs the second driving current according to the second data voltage, and the voltage across the light-emitting element is the preset voltage.
In this embodiment, the latch module is connected in series between the data write module and the driving module, so that the latch module can latch the first data voltage written by the data write module, and the area of the latch module does not increase with the increase of the storage capacity, so that the circuit area of the pixel circuit can be reduced.
In this embodiment, because the first end of the current collection module is electrically connected to the first end of the driving module, the second end of the current collection module is electrically connected to the first end of the comparison module, the second end of the comparison module is electrically connected to the first end of the compensation module, and the second end of the compensation module is electrically connected to the second end of the data writing module, the current collection module can collect the current first driving current and feed back the current first driving current to the comparison module, the comparison module can obtain the current voltages at the two ends of the light emitting element according to the first driving current, and compare the preset voltage with the current voltage to output a comparison result, and the comparison result can be a difference value between the preset voltage and the current voltage. When the comparison result meets the preset condition, the compensation module can generate a second data voltage according to the comparison result and output the second data voltage to the data writing module, so that the driving module outputs a second driving current according to the second data voltage, and the voltages at the two ends of the light-emitting element are adjusted to be preset voltages.
The embodiment of the utility model provides a still provide a pixel circuit. As shown in fig. 2, in the present embodiment, the control terminal of the DATA writing module 11 is connected to the SCAN signal line SCAN, and the second terminal of the DATA writing module 11 is connected to the DATA signal line DATA.
In the present embodiment, as shown in fig. 2, the data writing module 11 includes a first transistor M1, a first terminal of the first transistor M1 is connected to the first terminal of the data writing module 11, a second terminal of the first transistor M1 is connected to the second terminal of the data writing module 11, and a control terminal of the first transistor M1 is connected to the control terminal of the data writing module 11.
In the present embodiment, the first transistor M1 may be a P-type transistor. The first terminal of the first transistor M1 is a source, the second terminal of the first transistor M1 is a drain, and the control terminal of the first transistor M1 is a gate. That is, the drain of the first transistor M1 is connected to the DATA signal line DATA for receiving the first DATA voltage, and the gate of the first transistor M1 is connected to the SCAN signal line SCAN for receiving the SCAN signal.
In the present embodiment, as shown in fig. 2, the latch module 12 may include a first inverter INV1 and a second inverter INV 2.
An input end of the first inverter INV1 is connected to the first end of the latch module 12, an output end of the first inverter INV1 is connected to the second end of the latch module 12, an input end of the second inverter INV2 is connected to the second end of the latch module 12, and an output end of the second inverter INV2 is connected to the first end of the latch module 12. The latch module comprises a first inverter and a second inverter which are connected end to form a loop, so that the written data voltage can be latched. Since the area of the latch module of this configuration does not increase with an increase in the storage capacity, the circuit area of the pixel circuit can be reduced, and since the latch module has good stability, the stability of the pixel circuit can be improved.
In this embodiment, the first inverter may include a P-type transistor and an N-type transistor. The second inverter may also include a P-type transistor and an N-type transistor. The structure of the first inverter and the second inverter will not be described in detail herein.
In the present embodiment, as shown in fig. 2, the second terminal of the driving module 13 is connected to the first power signal line VDD. The first power supply signal line VDD may be a high voltage power supply signal line.
In the present embodiment, as shown in fig. 2, the driving module 13 includes a second transistor M2, a control terminal of the second transistor M2 is connected to the control terminal of the driving module 13, a first terminal of the second transistor M2 is connected to the first terminal of the driving module 13, and a second terminal of the second transistor M2 is connected to the second terminal of the driving module 13.
In the present embodiment, the second transistor M2 may be a P-type transistor serving as a driving transistor for driving the light emitting element 2 to emit light. The control terminal of the second transistor M2 is a gate, the first terminal of the second transistor M2 is a drain, and the second terminal of the second transistor M2 is a source. That is, the source of the second transistor M2 is connected to the first power supply signal line VDD, and the drain of the second transistor M2 is connected to the first terminal of the light emitting element 2.
In the present embodiment, as shown in fig. 2, the third terminal of the current collection block 14 is connected to the first power signal line VDD, and the enable terminal EN of the current collection block 14 is connected to an enable signal line (not shown) for inputting an enable signal.
In this embodiment, the current collection module 14 may include a current mirror (not shown), a first terminal of the current mirror is connected to the first terminal of the current collection module 14, a second terminal of the current mirror is connected to the second terminal of the current collection module 14, a third terminal of the current mirror is connected to the third terminal of the current collection module 14, and an enable terminal of the current mirror is connected to the enable terminal EN of the current collection module 14. Because the current mirror can copy the first driving current output by the driving module, accurate current data can be acquired.
In the embodiment, as shown in fig. 2, the current mirror includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8.
As shown in fig. 2, a first terminal of the third transistor M3 is connected to the third terminal of the current mirror, a second terminal of the third transistor M3 is connected to the first terminal of the fifth transistor M5, and a node at which a control terminal of the third transistor M3 is connected to a control terminal of the fourth transistor M4 is connected to a first terminal of the sixth transistor M6. A first terminal of the fourth transistor M4 is connected to the third terminal of the current mirror, and a second terminal of the fourth transistor M4 is connected to a first terminal of the sixth transistor M6. A node at which the control terminal of the fifth transistor M5 is connected to the control terminal of the sixth transistor M6 is connected to the second terminal of the sixth transistor M6, and the second terminal of the fifth transistor M5 is connected to the first terminal of the seventh transistor M7. The second terminal of the sixth transistor M6 is connected to the first terminal of the eighth transistor M8, and the second terminal of the eighth transistor M8 is connected to the first terminal of the current mirror. A second terminal of the seventh transistor M7 is connected to the second terminal of the current mirror; the control terminal of the seventh transistor M7 is connected in parallel with the control terminal of the eighth transistor M8 and then connected to the enable terminal of the current mirror.
In the embodiment, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 may all be P-type transistors. The first terminal of the third transistor M3 is a source, the second terminal of the third transistor M3 is a drain, and the control terminal of the third transistor M3 is a gate. The first terminal of the fourth transistor M4 is a source, the second terminal of the fourth transistor M4 is a drain, and the control terminal of the fourth transistor M4 is a gate. The first terminal of the fifth transistor M5 is a source, the second terminal of the fifth transistor M5 is a drain, and the control terminal of the fifth transistor M5 is a gate. The first terminal of the sixth transistor M6 is a source, the second terminal of the sixth transistor M6 is a drain, and the control terminal of the sixth transistor M6 is a gate. The first terminal of the seventh transistor M7 is a source, the second terminal of the seventh transistor M7 is a drain, and the control terminal of the seventh transistor M7 is a gate. The first terminal of the eighth transistor M8 is a source, the second terminal of the eighth transistor M8 is a drain, and the control terminal of the eighth transistor M8 is a gate.
In the present embodiment, as shown in fig. 2, the comparing module 15 includes a comparator Com and a capacitor C. A first end of the comparator Com is connected to the first end of the comparison module 15, a second end of the comparator Com is connected to a storage module (not shown) for storing a preset voltage, a third end of the comparator Com is connected to the second end of the comparison module 15, and the capacitor C is connected in series between the first end of the comparator Com and the third end of the comparator Com.
When the comparator Com receives the first driving current input by the current mirror, the comparator Com may convert the first driving current into a current voltage across the light emitting element 2, read a corresponding preset voltage from the storage module, and compare the preset voltage with the current voltage to output a comparison result to the compensation module 16. In this embodiment, the comparison result may be a difference between the preset voltage and the current voltage.
In the present embodiment, as shown in fig. 2, the compensation module 16 includes an analog-to-digital converter ADC. A first terminal of the analog-to-digital converter ADC is connected to a first terminal of the compensation module 16, and a second terminal of the analog-to-digital converter ADC is connected to a second terminal of the compensation module 16.
The ADC may generate a second data voltage according to the received comparison result, and output the second data voltage to the data writing module 11, so that the driving module 13 outputs a second driving current according to the second data voltage, and the voltage of the light emitting element at two ends is a preset voltage under the driving of the second driving current. For example, the preset voltage may be a gray scale voltage corresponding to the current gray scale.
In this embodiment, when the comparison result meets the preset condition, the ADC generates a second data voltage according to the received comparison result, and outputs the second data voltage to the data writing module 11. The preset condition may be, but is not limited to, that an absolute value of a difference between the preset voltage and the current voltage is greater than or equal to a preset threshold. That is, when the absolute value of the difference between the preset voltage and the current voltage is greater than or equal to the preset threshold, the analog-to-digital converter ADC generates the second data voltage according to the received comparison result, and outputs the second data voltage to the data writing module 11. When the absolute value of the difference between the preset voltage and the current voltage is less than the preset threshold, the analog-to-digital converter ADC may not perform the operation of "generating the second data voltage according to the received comparison result, and outputting the second data voltage to the data writing module 11".
In the present embodiment, the light emitting element 2 includes a light emitting diode D. A second terminal of the light emitting element 2 is connected to the second power source signal line VSS. The second power source signal line VSS may be a low voltage power source signal line. The anode of the light emitting diode D is connected to the first end of the light emitting element, and the cathode of the light emitting diode D is connected to the second end of the light emitting element. The light emitting diode D may be an Organic Light Emitting Diode (OLED), but is not limited thereto.
As shown in fig. 3, in the time period t2, the Scan signal Scan is at a low level, the first Data voltage Data is at a high level, the first transistor M1 is turned on, the second transistor M2 is turned on, the first Data voltage Data is written into the latch module 12, and the latch module 12 latches the first Data voltage Data.
As shown in fig. 3, during the time period t3, the second transistor M2 is continuously turned on, and the light emitting diode D performs light emitting display under the control of the first Data voltage Data.
In the normal working process of the pixel circuit, the current flowing through the light emitting diode D continuously collects the current of the light emitting channel through the current copying function of the current mirror, then is compared with the preset voltage to operate, and outputs a signal to control the first transistor M1 to regulate the current of the light emitting channel, so that abnormal distortion of the signal caused by threshold voltage drift and electric leakage is avoided, the anode signal of the light emitting diode D is continuously, stably and effectively ensured, and the current of the light emitting diode D is finally kept continuously, stably and effectively and stably emits light.
The embodiment of the utility model provides a still provide a pixel circuit. As shown in fig. 4, in the present embodiment, the latch module 12 further includes a control terminal Con. The latch module 12 includes a third inverter INV3, a fourth inverter INV4, a first tri-state gate TTL1, and a second tri-state gate TTL 2.
The input end of the first tri-state gate TTL1 is connected to the first end of the latch module 12, the first control end of the first tri-state gate TTL1 is connected to the output end of the third inverter INV3, the second control end of the first tri-state gate TTL1 is connected in parallel with the first control end of the second tri-state gate TTL2 and then connected to the input end of the third inverter INV3, the output end of the first tri-state gate TTL1 is connected in parallel with the output end of the second tri-state gate TTL2 and then connected to the input end of the fourth inverter INV4, and the output end of the fourth inverter INV4 is connected to the input end of the second tri-state gate TTL 2. The input end of the third inverter INV3 is connected to the control end of the latch module; the output terminal of the third inverter INV3 is further connected to the second control terminal of the second tri-state gate TTL2, and the input terminal of the second tri-state gate TTL2 is connected to the second terminal of the latch module 12.
When the first control terminal of the first tri-state gate TTL1 inputs a low level and the second control terminal of the first tri-state gate TTL1 inputs a high level, the first tri-state gate TTL1 is turned on. When the first control terminal of the first tri-state gate TTL1 inputs a high level and the second control terminal of the first tri-state gate TTL1 inputs a low level, the first tri-state gate TTL1 is closed.
When the first control terminal of the second tri-state gate TTL2 inputs a low level and the second control terminal of the second tri-state gate TTL2 inputs a high level, the second tri-state gate TTL2 is turned on. When the first control terminal of the second tri-state gate TTL2 inputs high level and the second control terminal of the second tri-state gate TTL2 inputs low level, the second tri-state gate TTL2 is closed.
When the control signal inputted by the control terminal Con is at a high level, the third inverter INV3 outputs a low level, the first tri-state gate TTL1 is turned on, the second tri-state gate TTL2 is turned off, and the first Data voltage Data enters a loop formed by the third inverter INV3 and the fourth inverter INV 4. When the control signal inputted from the control terminal Con is low, the third inverter INV3 outputs high, the first three-state gate TTL1 is turned off, the second three-state gate TTL2 is turned on, and the first Data voltage Data is held in a loop formed by the third inverter INV3 and the fourth inverter INV 4.
The latch module comprises a third inverter, a fourth inverter, a first tri-state gate and a second tri-state gate, wherein the third inverter and the fourth inverter are connected end to form a loop, so that the written data voltage can be latched. Since the area of the latch module of this configuration does not increase with an increase in the storage capacity, the circuit area of the pixel circuit can be reduced, and since the latch module has good stability, the stability of the pixel circuit can be improved.
It should be noted that the first and second tri-state gates TTL1 and TTL2 may also be clocked inverters.
The embodiment of the utility model provides a still provide a pixel circuit. As shown in fig. 5, in the present embodiment, the pixel circuit further includes a first reset module 17.
A first end of the first RESET block 17 is connected to the second end of the latch block 12, a second end of the first RESET block 17 is connected to the first power signal line VDD, and a control end of the first RESET block 17 is connected to the RESET signal line RESET.
As shown in fig. 6, the first reset module 17 includes a ninth transistor M9, a first terminal of the ninth transistor M9 is connected to the first terminal of the first reset module 17, a second terminal of the ninth transistor M9 is connected to the second terminal of the first reset module 17, and a control terminal of the ninth transistor M9 is connected to the control terminal of the first reset module 17.
In the present embodiment, as shown in fig. 6, the ninth transistor M9 is a P-type transistor. The first terminal of the ninth transistor M9 is a drain, the second terminal of the ninth transistor M9 is a source, and the control terminal of the ninth transistor M9 is a gate.
In the present embodiment, as shown in fig. 5, the pixel circuit further includes a second reset module 18. A first terminal of the second RESET module 18 is connected to the first terminal of the light emitting element 2 after being connected in parallel with the first terminal of the driving module 13, a second terminal of the second RESET module 18 is connected to the second power signal line VSS, a control terminal of the second RESET module 18 is connected to the RESET signal line RESET, and a second terminal of the light emitting element 2 is connected to the second power signal line VSS.
As shown in fig. 6, the second reset module 18 includes a tenth transistor M10, a first terminal of the tenth transistor M10 is connected to the first terminal of the second reset module 18, a second terminal of the tenth transistor M10 is connected to the second terminal of the second reset module 18, and a control terminal of the tenth transistor M10 is connected to the control terminal of the second reset module 18.
In the present embodiment, the tenth transistor M10 is a P-type transistor. The first terminal of the tenth transistor M10 is a drain, the second terminal of the tenth transistor M10 is a source, and the control terminal of the tenth transistor M10 is a gate.
In the present embodiment, as shown in fig. 7, in the time period t1, the RESET signal RESET input from the RESET signal line RESET is at a low level, and the ninth transistor M9 and the tenth transistor M10 are turned on. The ninth transistor M9 performs reset initialization on the latch module 12. The ninth transistor M9 is turned on so that the second transistor M2 is turned off, and the tenth transistor M10 performs reset initialization of the potential of the anode of the light emitting diode D, which is the potential VSS of the second power supply signal line VSS after the reset initialization. Since the potential of the cathode of the light emitting diode D is also Vss, the potential of the anode of the light emitting diode D is the same as the potential of the cathode, and the light emitting diode D does not emit light, so that residual light can be removed.
In this embodiment, since the first end of the first reset module is connected to the second end of the latch module, the first reset module can reset the latch module, and therefore, the influence of the residual data voltage on the accuracy of the data voltage written into the latch module can be avoided.
In this embodiment, since the first end of the second resetting module is connected to the first end of the light emitting element, the second resetting module can reset the light emitting element, so as to prevent the residual light of the light emitting element from affecting the light emitting quality of the light emitting element.
The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor may be N-type transistors.
The embodiment of the utility model also provides a display device, including any one of the above-mentioned embodiments pixel circuit.
In this embodiment, the latch module is connected in series between the data write module and the driving module, so that the latch module can latch the first data voltage written by the data write module, and the area of the latch module does not increase with the increase of the storage capacity, so that the circuit area of the pixel circuit can be reduced. Meanwhile, the first end of the current collection module is electrically connected with the first end of the driving module, the second end of the current collection module is electrically connected with the first end of the comparison module, the second end of the comparison module is electrically connected with the first end of the compensation module, and the second end of the compensation module is electrically connected with the second end of the data writing module, so that the current collection module can collect the current first driving current and feed the current first driving current back to the comparison module, the comparison module can obtain the current voltages at the two ends of the light-emitting element according to the first driving current and compare the preset voltage with the current voltage to output a comparison result, and the comparison result can be a difference value between the preset voltage and the current voltage. When the comparison result meets the preset condition, the compensation module can generate a second data voltage according to the comparison result and output the second data voltage to the data writing module, so that the driving module outputs a second driving current according to the second data voltage, and the voltages at the two ends of the light-emitting element are adjusted to be preset voltages.
The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
In the present application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.
Claims (10)
1. A pixel circuit, comprising: the device comprises a data writing module, a latching module, a driving module, a current acquisition module, a comparison module and a compensation module;
the first end of the latch module is electrically connected with the first end of the data writing module, the second end of the latch module is electrically connected with the control end of the driving module, the first end of the driving module is electrically connected with the first end of the light-emitting element, the first end of the current acquisition module is electrically connected with the first end of the driving module, the second end of the current acquisition module is electrically connected with the first end of the comparison module, the second end of the comparison module is electrically connected with the first end of the compensation module, and the second end of the compensation module is electrically connected with the second end of the data writing module;
the data write module is configured to write a first data voltage to the latch module, the latch module is configured to latch the first data voltage, the driving module is configured to output a first driving current according to the first data voltage, the current collecting module is configured to collect the first driving current, the comparison module is configured to obtain a present voltage across the light emitting element according to the first driving current, and comparing a preset voltage with the current voltage to output a comparison result, the compensation module being configured to generate a second data voltage according to the comparison result and output the second data voltage to the data writing module, and the driving module outputs a second driving current according to the second data voltage, and the voltage at two ends of the light-emitting element is the preset voltage.
2. The pixel circuit according to claim 1, wherein a control terminal of the data writing module is connected to a scan signal line;
the data writing module comprises a first transistor, wherein a first end of the first transistor is connected to a first end of the data writing module, a second end of the first transistor is connected to a second end of the data writing module, and a control end of the first transistor is connected to a control end of the data writing module.
3. The pixel circuit according to claim 1, wherein the latch module comprises a first inverter and a second inverter;
the input end of the first inverter is connected to the first end of the latch module, the output end of the first inverter is connected to the second end of the latch module, the input end of the second inverter is connected to the second end of the latch module, and the output end of the second inverter is connected to the first end of the latch module; alternatively, the first and second electrodes may be,
the latch module also comprises a control end; the latch module comprises a third inverter, a fourth inverter, a first tri-state gate and a second tri-state gate;
the input end of the first tri-state gate is connected to the first end of the latch module, the first control end of the first tri-state gate is connected to the output end of the third inverter, the second control end of the first tri-state gate is connected with the first control end of the second tri-state gate in parallel and then connected to the input end of the third inverter, and the output end of the first tri-state gate is connected with the output end of the second tri-state gate in parallel and then connected to the input end of the fourth inverter; the output end of the fourth inverter is connected to the input end of the second tri-state gate;
the input end of the third inverter is connected to the control end of the latch module; the output end of the third inverter is further connected to the second control end of the second tri-state gate, and the input end of the second tri-state gate is connected to the second end of the latch module.
4. The pixel circuit according to claim 1, wherein the second terminal of the driver block is connected to a first power supply signal line;
the driving module comprises a second transistor, a control end of the second transistor is connected to a control end of the driving module, a first end of the second transistor is connected to a first end of the driving module, and a second end of the second transistor is connected to a second end of the driving module.
5. The pixel circuit according to claim 1, wherein a third terminal of the current collection block is connected to a first power signal line, and an enable terminal of the current collection block is connected to an enable signal line;
the current acquisition module comprises a current mirror, the first end of the current mirror is connected to the first end of the current acquisition module, the second end of the current mirror is connected to the second end of the current acquisition module, the third end of the current mirror is connected to the third end of the current acquisition module, and the enable end of the current mirror is connected to the enable end of the current acquisition module;
the current mirror comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;
the first end of the third transistor is connected to the third end of the current mirror, the second end of the third transistor is connected to the first end of the fifth transistor, and the node where the control end of the third transistor is connected with the control end of the fourth transistor is connected to the first end of the sixth transistor;
a first terminal of the fourth transistor is connected to the third terminal of the current mirror, and a second terminal of the fourth transistor is connected to the first terminal of the sixth transistor;
a node of the connection of the control terminal of the fifth transistor and the control terminal of the sixth transistor is connected to the second terminal of the sixth transistor, and the second terminal of the fifth transistor is connected to the first terminal of the seventh transistor;
a second terminal of the sixth transistor is connected to a first terminal of the eighth transistor, and a second terminal of the eighth transistor is connected to a first terminal of the current mirror;
a second terminal of the seventh transistor is connected to a second terminal of the current mirror; and the control end of the seventh transistor is connected with the control end of the eighth transistor in parallel and then connected to the enabling end of the current mirror.
6. The pixel circuit according to claim 1, wherein the comparing module comprises a comparator and a capacitor;
the first end of the comparator is connected to the first end of the comparison module, the second end of the comparator is connected to the storage module for storing the preset voltage, the third end of the comparator is connected to the second end of the comparison module, and the capacitor is connected between the first end of the comparator and the third end of the comparator in series.
7. The pixel circuit of claim 1, wherein the compensation module comprises an analog-to-digital converter;
the first end of the analog-to-digital converter is connected to the first end of the compensation module, and the second end of the analog-to-digital converter is connected to the second end of the compensation module.
8. The pixel circuit according to claim 1, further comprising a first reset module;
the first end of the first reset module is connected to the second end of the latch module, the second end of the first reset module is connected to the first power signal line, and the control end of the first reset module is connected to the reset signal line;
the first reset module comprises a ninth transistor, a first end of the ninth transistor is connected to the first end of the first reset module, a second end of the ninth transistor is connected to the second end of the first reset module, and a control end of the ninth transistor is connected to the control end of the first reset module.
9. The pixel circuit according to claim 1, further comprising a second reset module;
a first end of the second reset module is connected with a first end of the driving module in parallel and then connected to a first end of the light-emitting element, a second end of the second reset module is connected to a second power signal line, and a control end of the second reset module is connected to a reset signal line; a second end of the light emitting element is connected to the second power supply signal line;
the second reset module comprises a tenth transistor, a first end of the tenth transistor is connected to the first end of the second reset module, a second end of the tenth transistor is connected to the second end of the second reset module, and a control end of the tenth transistor is connected to the control end of the second reset module.
10. A display device comprising the pixel circuit according to any one of claims 1 to 9.
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| CN201922245223.5U CN210956116U (en) | 2019-12-13 | 2019-12-13 | Pixel circuit and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114783381A (en) * | 2022-04-29 | 2022-07-22 | 惠科股份有限公司 | Pixel driving circuit and display panel |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114783381A (en) * | 2022-04-29 | 2022-07-22 | 惠科股份有限公司 | Pixel driving circuit and display panel |
| CN114783381B (en) * | 2022-04-29 | 2023-11-03 | 惠科股份有限公司 | Pixel driving circuit and display panel |
| US11948511B2 (en) | 2022-04-29 | 2024-04-02 | HKC Corporation Limited | Pixel driving circuit and display panel |
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