CN210897297U

CN210897297U - Solar cell

Info

Publication number: CN210897297U
Application number: CN201922340359.4U
Authority: CN
Inventors: 伏进文; 袁中存
Original assignee: CSI Cells Co Ltd; CSI GCL Solar Manufacturing Yancheng Co Ltd
Current assignee: Funing atlas sunshine Power Technology Co., Ltd; CSI Cells Co Ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2020-06-30
Anticipated expiration: 2029-12-24

Abstract

The application provides a solar cell, be in including silicon substrate, setting the electrode grid line of silicon substrate surface, the electrode grid line is including distributing in the marginal grid line of interconnection in the corner region of silicon substrate, the marginal grid line of interconnection adopts non-linear design or inside and outside double-line design. This application solar cell carries out optimal design through the marginal grid line of interconnection to the corner region, avoids the corner region of silicon substrate probably exists around plating, dirty unusual lead to the marginal grid line contact of interconnection bad, guarantees the battery performance.

Description

Solar cell

Technical Field

The application relates to the technical field of solar manufacturing, in particular to a solar cell.

Background

Crystalline silicon solar cells still occupy the important position in the photovoltaic market, and the crystalline silicon solar cells realize current collection and output through surface metal electrodes, and the surface metal electrodes are usually prepared by adopting screen printing and sintering processes. With the development of battery technology and process, the back passivation technology can effectively reduce the recombination of the back of the battery, and is applied in large scale in the industry, so that the battery efficiency is greatly improved. However, in the preparation process of the back passivation film layer, the edge position of the front side of the battery may have a plating-around phenomenon, and particularly, in a chamfer area of the battery piece, contamination and the like caused by the plating-around and etching processes may cause that electrode paste printed in the area cannot be burnt through, and then abnormal conditions such as grid breakage and the like occur in the chamfer area.

Particularly, the laminated tile assembly enables the front main grid lines of one cell to be overlapped with the back main grid lines of the back of the other cell through conductive adhesive by mutually connecting the cells in a tighter mode, so that gaps among the cells are minimized, thereby effectively reducing ineffective power generation space caused by cell intervals and improving the irradiation utilization rate of unit area. The laminated tile assembly generally uses strip-shaped battery pieces obtained by cutting a whole battery piece, as shown in fig. 1, for a strip-shaped area 201 corresponding to each strip-shaped battery piece, a thin grid 203 at an edge position is connected to a front main grid line 202 through a corner grid line 204, and when the corner grid line 204 is abnormal due to wire breakage caused by plating, etching, dirt and the like, normal transmission of current is affected, so that battery efficiency is reduced.

In view of the above, there is a need for a new solar cell.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a solar cell can improve the connection reliability of electrode grid line, reduces disconnected bars risk, guarantees battery quality.

In order to achieve the above object, an embodiment of the present application provides a solar cell, including a silicon substrate, an electrode gate line disposed on a surface of the silicon substrate, where the electrode gate line includes interconnection edge gate lines distributed in corner regions of the silicon substrate, and the interconnection edge gate line adopts a non-linear design or an inner and outer double-line design.

As a further improvement of the embodiment of the present application, the interconnection edge grid line adopts a non-linear design, and the interconnection edge grid line extends in a curve.

As a further improvement of the embodiment of the present application, the interconnection edge gate line adopts an inner and outer double line design, and includes a first interconnection gate line and a second interconnection gate line located at an inner side of the first interconnection gate line.

As a further improvement of the embodiment of the present application, the first interconnection gate line and the second interconnection gate line are parallel to each other and linearly extend.

As a further improvement of the embodiment of the present application, the electrode gate line further includes a first edge gate line and a second edge gate line connected to two ends of the interconnection edge gate line and perpendicular to each other, the first edge gate line and the second edge gate line respectively have a first end point and a second end point located in the corner region, and at least a portion of the interconnection edge gate line is located on one side of a straight line connecting the first end point and the second end point, which faces the center of the silicon substrate.

As a further improvement of the embodiment of the present application, the electrode gate line further includes a sub-gate line parallel to the second edge gate line and connected to the first edge gate line or the interconnection edge gate line.

As a further improvement of the embodiment of the present application, the solar cell includes a plurality of strip-shaped cell regions sequentially arranged along the extending direction of the second edge grid line, and each strip-shaped cell region is provided with a bus main grid.

The beneficial effect of this application is: adopt this application solar cell, carry out optimal design through the regional interconnected edge grid line of opposite corner, avoid the corner region probably exists around plating, dirty unusual lead to interconnected edge grid line contact failure, improve the connection reliability of electrode grid line, reduce disconnected bars risk, guarantee battery quality.

Drawings

FIG. 1 is a schematic structural diagram of a conventional solar cell;

FIG. 2 is a schematic structural diagram of a solar cell according to a preferred embodiment of the present invention;

FIG. 3 is an enlarged view of area A of FIG. 2;

FIG. 4 is a schematic structural diagram of another preferred embodiment of a solar cell of the present application;

fig. 5 is an enlarged view of the region a' in fig. 4.

100-solar cell; 10-a silicon substrate; 101-bar cell area; 11-a first side; 12-a second side edge; 13-third side; 21-a first edge gate line; 211-a first endpoint; 22-a second edge grid line; 221-a second endpoint; 23-interconnecting edge grid lines; 231-first interconnect gate line; 232-a second interconnect gate line; 24-a secondary grid line; 201-bar shaped area; 202-front side bus bar; 203-fine grid; 204-corner grid lines.

Detailed Description

The present application will be described in detail below with reference to embodiments shown in the drawings. The present invention is not limited to the above embodiments, and structural, methodological, or functional changes made by one of ordinary skill in the art according to the present embodiments are included in the scope of the present invention.

Referring to fig. 2 and 3, a solar cell 100 provided in the present application includes a silicon substrate 10 and electrode grid lines disposed on a surface of the silicon substrate 10. The silicon substrate 10 has a first side 11 extending along a first direction, a second side 12 extending along a second direction, and a third side 13 connecting the first side 11 and the second side 12; the electrode gate lines include a first edge gate line 21 disposed along the first side 11, a second edge gate line 22 disposed along the second side 12, and an interconnection edge gate line 23 connecting the first edge gate line 21 and the second edge gate line 22 and disposed adjacent to the third side 13.

The silicon substrate 10 is a Czochralski monocrystalline silicon wafer, the first side edge 11 and the second side edge 12 are perpendicular to each other, and the third side edge 13 is a chamfered edge connecting the first side edge 11 and the second side edge 12. The first edge gate line 21, the second edge gate line 22, and the interconnection edge gate line 23 refer to a frame gate line disposed on the front surface of the silicon substrate 10, and may be formed by printing and sintering corresponding silver paste. In addition, the electrode gate line further includes a sub-gate line 24 parallel to the second edge gate line 22 and connected to the first edge gate line 21 or the interconnection edge gate line 23.

The first edge gate line 21 and the second edge gate line 22 respectively have a first endpoint 211 and a second endpoint 221 facing the third side 13, and at least a portion of the interconnection edge gate line 23 and the third side 13 are respectively located on two sides of a straight line L connecting the first endpoint 211 and the second endpoint 221. In the back passivation and etching processes of the solar cell 100, defects such as plating and smudging may be caused in the corner region of the silicon substrate 10, and compared with the prior art (the corner grid line 204 shown in fig. 1), the interconnection edge grid line 23 is arranged away from the third side 13, so that the defects of the corner region are greatly avoided, the interconnection edge grid line 23 is not well printed and sintered, and the reliability of electrode grid line connection is ensured.

Here, the solar cell 100 includes a plurality of strip-shaped cell regions 101 sequentially arranged along a second direction, and each of the strip-shaped cell regions 101 is provided with a main bus bar along the first direction. The first edge grid lines 21 are arranged as bus bars on the corresponding strip-shaped cell regions 101, in other words, after the solar cells 100 are divided along the strip-shaped cell regions 101, the first edge grid lines 21 are used for connecting the corresponding strip-shaped cell slices with another strip-shaped cell slice. The second edge gate line 22, the interconnection edge gate line 23 and the sub-gate line 24 are used for collecting the surface current of the silicon substrate 10 onto the first edge gate line 21.

The line width of the first edge gate line 21 is usually set to be much larger than the line width of the second edge gate line 22; the line width of the interconnection edge grid line 23 is equivalent to that of the second edge grid line 22. Since the first edge grating 21 has a relatively large line width, it should be noted that the first end point 211 specifically refers to a terminal end of a side edge of the first edge grating 21 facing the first side 11 and close to the third side 13.

In this embodiment, the entirety of the interconnection edge gate line 23 is located on a side of the straight line L toward the center of the silicon substrate 10 except for the end point positions. The distance between the interconnection edge gate line 23 and the third side 13 is greater than the distance between the first edge gate line 21 and the first side 11, and the distance between the interconnection edge gate line 23 and the third side 13 is greater than the distance between the second edge gate line 22 and the second side 12.

The interconnection edge grid line 23 may be arranged in a wave shape, a square wave shape or a zigzag shape, and extend in a bending manner, and two ends of the interconnection edge grid line 23 are respectively connected to the first end point 211 and the second end point 221. Here, in order to avoid the screen blocking and missing phenomenon at the corner of the folding line during the screen printing process, the interconnection edge grid lines 23 are preferably arranged to extend in a curved line, and the line width of the interconnection edge grid lines 23 is set to be about 100 μm.

Referring to fig. 4 and 5, in another embodiment of the present application, the interconnection edge gate line 23 includes a first interconnection gate line 231 and a second interconnection gate line 232 which are spaced apart from each other. Two ends of the first interconnection gate line 231 are connected to the first end point 211 and the second end point 221 respectively; the second interconnection gate line 232 is located at a side of the first interconnection gate line 231 away from the third side edge 13. A portion of the finger lines 24 intersects the second interconnection gate line 232 along the second direction, and its end is connected to the first interconnection gate line 231.

The first interconnection gate line 231 and the second interconnection gate line 232 are parallel to each other and extend linearly. Particularly, the line widths of the first interconnection gate line 231 and the second interconnection gate line 232 may be set to about 50 μm, and the distance between the first interconnection gate line 231 and the second interconnection gate line 232 is set to 0.5 to 1.0 mm.

In summary, according to the solar cell 100, the interconnection edge gate lines 23 connecting the first edge gate lines 21 and the second edge gate lines 22 move towards the center side of the silicon substrate 10, that is, the interconnection edge gate lines 23 are far away from the third side 13, so that the problem that the interconnection edge gate lines 23 are in poor contact due to abnormal winding plating and dirt in the corner regions is avoided, the connection reliability of the electrode gate lines is improved, the risk of grid breakage is reduced, and the cell quality is ensured.

It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.

The above list of details is only for the concrete description of the feasible embodiments of the present application, they are not intended to limit the scope of the present application, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present application are intended to be included within the scope of the present application.

Claims

1. The utility model provides a solar cell, includes the silicon substrate, sets up the electrode grid line of silicon substrate surface, the electrode grid line is including distributing in the interconnection edge grid line in the corner region of silicon substrate which characterized in that: the interconnection edge grid line adopts a non-linear design or an inner and outer double-line design.

2. The solar cell of claim 1, wherein: the interconnection edge grid line adopts a non-linear design and extends in a curve.

3. The solar cell of claim 1, wherein: the interconnection edge grid line adopts an inner and outer double-line design and comprises a first interconnection grid line and a second interconnection grid line positioned on the inner side of the first interconnection grid line.

4. The solar cell of claim 3, wherein: the first interconnection grid line and the second interconnection grid line are parallel to each other and are arranged in a linear extending mode.

5. The solar cell of claim 1, wherein: the electrode grid line further comprises a first edge grid line and a second edge grid line which are connected to two ends of the interconnection edge grid line and are perpendicular to each other, the first edge grid line and the second edge grid line respectively comprise a first end point and a second end point which are located in the corner area, and at least one part of the interconnection edge grid line is located on one side, facing the center of the silicon substrate, of a straight line connecting the first end point and the second end point.

6. The solar cell of claim 5, wherein: the electrode grid line further comprises a secondary grid line which is parallel to the second edge grid line and is connected with the first edge grid line or the interconnection edge grid line.

7. The solar cell of claim 5, wherein: the solar cell comprises a plurality of strip-shaped cell areas which are sequentially arranged along the extending direction of the second edge grid line, and each strip-shaped cell area is provided with a confluence main grid.

8. The solar cell of claim 7, wherein: the line width of the first edge grid line is larger than that of the second edge grid line, and the first edge grid line is set as a main convergence grid on the corresponding strip-shaped battery region.