CN210864699U - Interface circuit of display device and IIC device - Google Patents

Abstract

The utility model provides an interface circuit of display device and IIC device. A display device including an IIC bus; the IIC device, a pull-up circuit and an isolating switch circuit; the IIC device is provided with an IIC interface and a power supply end; the controlled end of the isolating switch circuit is connected with the power end, the first end of the isolating switch circuit is connected with the IIC interface, and the second end of the isolating switch circuit is connected with the IIC bus interface circuit and the pull-up circuit. According to the embodiment, the influence of the working state of the IIC device on the IIC bus is reduced, and the working reliability between the IIC bus and each IIC device in the display equipment is improved.

Description

Interface circuit of display device and IIC device

Technical Field

The utility model relates to a display device field, in particular to interface circuit of display device and IIC device.

Background

The display equipment is internally provided with an IIC bus, and a plurality of IIC devices can be hung on the IIC bus. And all IIC devices transmit and receive data through an IIC bus to realize signal interaction. IIC devices attached to the IIC bus typically transmit signals by pulling the voltage on the IIC bus low. And after the signal transmission is finished, pulling up the voltage at the interface of the IIC device through a pull-up power supply and a pull-up resistor connected at the interface of the IIC device.

Some display devices have a standby function, and in order to reduce power consumption during standby, the enable terminal of an IIC device that does not need to operate is usually pulled down, so that the IIC device does not operate. However, some IIC devices have no design enable terminal, or have excessive standby power consumption, and are powered off when the display device is in standby.

For the IIC device using CMOS process, in order to protect the IIC interface from electrostatic damage, an anti-electrostatic diode is usually connected between the IIC interface and the power supply terminal of the IIC device, and when the electronic device is in standby, VDD becomes 0V, so that a pull-up power source is pumped into the power supply terminal from 3.3V through the pull-up resistor of the IIC and the ESD diode. Since the voltage drop of the anti-static diode is 0.7V, the voltage on the IIC bus is pulled down to 0.7V, so that the IIC bus can not transmit signals for other IIC devices.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to solve the influence of IIC device after the power failure among the prior art to voltage on the IIC bus.

In order to solve the technical problem, the utility model adopts the following technical scheme:

the utility model provides a display device, include:

an IIC bus;

an IIC device having an IIC interface and a power supply terminal;

a pull-up circuit;

and the controlled end of the isolating switch circuit is connected with the power supply end, the first end of the isolating switch circuit is connected with the IIC interface, and the second end of the isolating switch circuit is interconnected with the IIC bus interface circuit and the pull-up circuit.

Optionally, the isolation switch circuit includes an isolation switch tube.

Optionally, the isolation switch tube is an MOS tube, a gate of the isolation switch tube is connected to the power supply end, a source of the isolation switch tube is connected to the IIC interface, and a drain of the isolation switch tube is interconnected to the IIC bus and the pull-up circuit.

Optionally, the threshold voltage of the isolation switch tube satisfies V_th＜V_DD-V₀×0.7；

Wherein, V_thIs the threshold voltage, V, of the isolating switch tube_DDIs the supply voltage, V, on said supply terminal₀Is the operating voltage on the IIC bus.

Optionally, the isolation switch circuit further includes a first resistor, and two ends of the first resistor are respectively connected to the power supply end and the first end of the isolation switch tube.

Optionally, the resistance value of the first resistor is less than or equal to 40 ohms and greater than or equal to 20 ohms.

Optionally, the pull-up circuit includes a pull-up power source and a pull-up resistor, one end of the pull-up resistor is connected to the pull-up power source, and the other end of the pull-up resistor is interconnected with the second end of the isolation switch tube and the IIC bus.

Optionally, the IIC bus includes a clock line and a data line, the isolation switch circuit includes two isolation switch tubes, and the two isolation switch tubes are respectively used for isolating the IIC interface from the clock line and isolating the IIC interface from the data line.

Optionally, the IIC device is a CMOS process device.

The utility model discloses still provide an interface circuit of IIC device, include:

the IIC interface is used for connecting the IIC device with the IIC bus;

the power supply end is used for supplying power to the IIC;

and the controlled end of the isolating switch circuit is connected with the power supply end, the first end of the isolating switch circuit is connected with the IIC interface, and the second end of the isolating switch circuit is interconnected with the IIC bus interface circuit and the pull-up circuit.

In the embodiment, the isolation switch circuit is arranged, and the controlled end of the isolation switch circuit is connected with the power end of the IIC device, so that the isolation switch tube is kept turned off when the IIC device does not need to send a signal. When the IIC device needs to send signals, the isolating switch circuit is conducted under the action of the low level output by the IIC interface, so that the IIC device can normally send the signals, and in the conducting process of the isolating switch circuit, the anti-static diode in the IIC device can be forced not to be conducted in the forward direction, and the influence of a pull-up power source on an IIC bus through the MOS tube when the isolating switch circuit is conducted is avoided. Therefore, the influence of the working state of the IIC device on the IIC bus is reduced, and the working reliability between the IIC bus and each IIC device in the display equipment is improved.

Drawings

FIG. 1 is an exploded view of the display device of the present embodiment;

FIG. 2 is a timing diagram of the IIC signal;

FIG. 3 is a schematic diagram of a circuit for connecting an IIC device to an IIC bus in the related art;

FIG. 4 is a schematic diagram of an embodiment of a circuit for connecting the IIC device and the IIC bus according to the present embodiment;

FIG. 5 is a schematic diagram of another embodiment of a circuit for connecting the IIC device and the IIC bus according to the present embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

In the present disclosure, unless expressly stated or limited otherwise, the terms "connected" and "connected" are to be construed broadly, e.g., as meaning either a fixed connection or a removable connection, or an integral part; can be electrically connected or can be communicated with each other; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

Furthermore, in the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. "and/or" describes the association relationship of the associated objects, and means that there may be three relationships, for example, a and/or B, and that there may be three cases of a alone, B alone, and a and B simultaneously. The symbol "/" generally indicates that the former and latter associated objects are in an "or" relationship. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

The structure of the display device is explained here, and referring to fig. 1, fig. 1 is an exploded view of the display device of this embodiment. As shown in fig. 1, the display device includes a panel 1, a backlight assembly 2, a main board 3, a power board 4, a rear case 5, and a base 6. Wherein, the panel 1 is used for presenting pictures for users; the backlight assembly 2 is located below the panel 1, usually some optical assemblies, and is used for supplying sufficient light sources with uniform brightness and distribution, so that the panel 1 can normally display images, the backlight assembly 2 further includes a back plate 201, the main plate 3 and the power supply board 4 are arranged on the back plate 201, usually some convex hull structures are formed by punching on the back plate 201, and the main plate 3 and the power supply board 4 are fixed on the convex hulls through screws or hooks; the rear case 5 covers the panel 1 to hide the components of the display device such as the backlight assembly 2, the main board 3, and the power board 4, thereby achieving an aesthetic effect.

The main control chip of the display device generally performs signal transmission with each IIC device through an IIC bus. All devices supporting the IIC protocol may be referred to herein as IIC devices, such as EEPROM with an IIC interface, DCDC, audio power amplifiers, etc.

The IIC bus is a simple, bi-directional two-wire system synchronous serial bus. The device can be connected between a main control chip and a controlled chip, and bidirectional transmission is carried out between the chips. Various controlled circuits are connected in parallel to the bus. It requires only two wires to transfer information between IIC devices connected to the bus. These two lines are SCL and SDA, respectively. SDA is the bidirectional data line and SCL is the clock line. The various controlled circuits are connected in parallel on the bus, but just like a telephone set, the controlled circuits can work only by dialing respective numbers, so that each circuit and each module have unique addresses, and each module circuit connected in parallel on the IIC bus is a master controller (or a slave controller) and a transmitter (or a receiver) in the process of information transmission, which depends on the functions to be completed by the controlled circuits. The control signal sent by the main control chip is divided into an address code and a control quantity, wherein the address code is used for selecting addresses, namely, a circuit to be controlled is switched on, and the type of control is determined; the control amount determines the type of adjustment (e.g., contrast, brightness, etc.) and the amount of adjustment required. Thus, the control circuits are independent and independent of each other although hung on the same bus.

Referring to fig. 2, the IIC bus shares three types of signals during data transmission, which are: a start signal, an end signal and a response signal. During the time that the clock line SCL remains high, the level on the data line SDA is pulled low (negative transition), defined as the start signal of the I2C bus, which marks the start of a data transmission. The enable signal is actively asserted by the master, and the I2C bus must be idle before this signal is asserted. During the time that the clock line SCL remains high, the data line SDA is released, causing SDA to return a high level (i.e., a positive transition), referred to as the end signal of the I2C bus, which marks the end of a data transfer. The end signal is also actively asserted by the master, and after this signal is asserted, the I2C bus will return to the idle state. Response signal: after receiving 8-bit data, the IC receiving the data sends a specific low-level pulse to the IC transmitting the data, indicating that the data has been received. For example, after the master control chip sends a signal to the controlled unit, it waits for the controlled unit to send a response signal, and after the master control chip receives the response signal, it determines whether to continue to transmit the signal according to the actual situation. If the answer signal is not received, the controlled unit is judged to be in fault. Of these signals, the start signal is required, and the end signal and the response signal are unnecessary.

The adoption of IIC bus control has three main advantages: firstly, the connection among all parts of circuits becomes very simple, a plurality of input/output (I/O) interfaces in a control system are saved, a large number of components and connecting pieces are reduced, the cost is reduced, and the reliability of the whole machine is improved; secondly, because the IIC bus has multiple functions, the IIC bus is very convenient to adjust and test by using a computer on a production line, and the improvement of the product quality is facilitated; and thirdly, the television set applying the IIC bus has a self-diagnosis function and is convenient to maintain.

The display equipment adopts IIC bus control technology, can conveniently adjust and control various analog quantities, including white balance, line field amplitude and synchronization, sound and picture parameters, various function switching and the like, not only greatly reduces the number of circuit elements of the whole machine, simplifies the circuit and improves the reliability of products, but also can conveniently increase various functions of the machine through program setting.

A schematic of the interface internal circuitry of the IIC device 11, produced in a CMOS process design, is shown in figure 3. The IIC device 11 has a power supply terminal V_DDAnd an I/O port located inside the IIC device 11, and a power supply terminal V at the I/O and the IIC device 11 for protecting the IIC port from electrostatic damage_DDAn anti-static diode Vd connected between them. Power supply end V_DDIs thatThe IIC device 11 supplies power; a pull-up resistor R0 and a pull-up power supply V0 are also connected to the interface of the IIC device 11. The I/O port pulls down the voltage of the IIC interface by outputting a low level, so that the voltage of the IIC bus 10 is pulled down to transmit signals; when the I/O port is disconnected to suspend the IIC interface, the voltage at the IIC interface can be pulled up to a high level through the pull-up power supply V0 and the pull-up resistor R0.

When the device works normally, the negative electrode of the anti-static diode Vd is connected with a power supply end V_DDSo that the voltage is high, e.g., 3.3V, to power the IIC device 11, and the power supply terminal V_DDThe voltage on the diode is always larger than the voltage of the I/O port, so that the static-free diode Vd always works in a reverse cut-off state, which is equivalent to an open circuit.

When the electronic device is in standby state, the power supply terminal V_DDThe upper voltage is 0V, a pull-up power supply V0, a pull-up resistor R0, an anti-static diode Vd and a power supply end V_DDA loop is formed, and current can be pumped into a power supply end V from a pull-up power supply V0 through a pull-up resistor R0 and an anti-static diode Vd_DD. Since the voltage drop of the diode Vd is 0.7V, the voltage on the IIC bus 10 is pulled down to 0.7V, so that the IIC bus 10 cannot transmit signals to other IIC devices 11 during standby.

Optionally, a MOS transistor isolator is used between the pull-up power supply V0 and the anti-static diode Vd, and a power supply terminal V is connected to the MOS transistor isolator_DDDisconnecting the isolating switch before power failure and at power supply end V_DDAnd after the power is on, the isolating switch is opened.

The present embodiment provides a display device. Referring to fig. 4, the display device includes an IIC bus 10, an IIC device 11, a pull-up circuit 12, and an isolation switch circuit 13. Controlled end and power end V of isolating switch circuit 13_DDAnd a first end of the isolating switch circuit 13 is connected with the IIC interface, and a second end of the isolating switch circuit 13 is interconnected with the IIC bus 10 interface circuit and the pull-up circuit 12. The IIC bus 10 may be disposed between the display apparatus main control chip and the IIC device 11. May also be disposed between IIC device 11 and IIC device 11. The isolating switch circuit 13 includes an isolating switch tube, or may be another component having a switching characteristic, and is a single-pole switch.

The IIC bus 10 includes the clock line SCL and the data line SDA. The two threads are independent. Therefore, the isolation switch circuit 13 includes two isolation switch tubes, and the two isolation switch tubes 13 are respectively used for isolating the IIC interface from the clock line SCL and isolating the IIC interface from the data line SDA. The operation of the isolation switch circuit 13 is the same for the clock line SCL and the data line SDA, and therefore, in the following embodiments, the specific embodiment in which the isolation switch circuit 13 is applied to the clock line SCL and the data line SDA is not separately described.

The pull-up circuit 12 here comprises a pull-up power supply V0 and a pull-up resistor R0, the pull-up resistor R0 being connected at one end to the pull-up power supply V0 and at the other end to the second end of the disconnector tube, which is interconnected to the IIC bus 10. When the I/O port inside the IIC interface outputs a low level, the IIC bus 10 is at a low level. When the I/O port inside the IIC interface is disconnected to suspend the IIC interface, the pull-up voltage pulls the IIC bus 10 high through the pull-up resistor R0.

In this embodiment, the isolation switch tube may be an MOS tube Q1, and the gate of the isolation switch tube is connected to the power supply terminal V_DDAnd the source electrode of the isolating switch tube is connected with the IIC interface, and the drain electrode of the isolating switch tube is interconnected with the IIC bus 10 and the pull-up circuit 12. In another embodiment, the isolation switch may also use a transistor, and those skilled in the art can replace the MOS transistor Q1 with a transistor according to the prior knowledge. In the following embodiments, the example in which the isolation switch transistor is the MOS transistor Q1 will be described.

Referring to fig. 5, in the present embodiment, since the gate of the MOS transistor Q1 is connected to the power supply terminal of the IIC device 11, the driving voltage of the MOS transistor Q1 uses the power supply voltage of the IIC device 11, which is 3.3V as an example. Corresponding to the marks in the figure, the gate voltage of the MOS transistor Q1 is denoted as Vg, the source voltage is denoted as Vs, and the drain voltage is denoted as Vd. Since the drain of the MOS transistor Q1 is connected to the IIC bus 10, the voltage on the IIC bus 10 is generally constant at 3.3V or 5V, such as 3.3V.

When the display device is in standby, the power supply terminal V_DDThe upper voltage is 0, and at this time, the gate voltage of the MOS transistor Q1 is 0, so the MOS transistor Q1 is in an off state. MOS switch in off stateThe pull-up power supply V0, the pull-up resistor R0, the anti-static diode Vd and the power supply end V are disconnected_DDThe formed loop ensures that the voltage on the IIC signal end is not influenced by the power-down of the IIC device 11.

When the display device works normally, but the IIC device 11 does not need to transmit signals to the IIC bus 10, so that the 1/O port inside the IIC interface is disconnected, and the source of the MOS transistor Q1 is suspended, so that the MOS transistor Q1 is disconnected, and the voltage on the IIC signal end can be ensured not to be influenced by the power-off of the IIC device 11.

When the display device is operating normally and the IIC device 11 needs to transmit signals to the IIC bus 10, the 1/O port inside the IIC interface is turned on, the source of the MOS transistor Q1 is grounded, and the conduction condition of the MOS transistor Q1Vg is: Vg-Vs > Vth; where Vth is the threshold voltage of the MOS transistor Q1, typically 0.7V. It can be seen that at this time, the MOS transistor Q1 is turned on, and the drain voltage of the MOS transistor Q1 is pulled down to 0 by the source, so that the voltage on the IIC bus 10 is pulled down, and the IIC device 11 can transmit a signal.

When the IIC device 11 completes signal transmission, the 1/O port inside the IIC interface is disconnected, and the source of the MOS transistor Q1 returns to a floating state, but the MOS transistor Q1 is not turned off at this time, and a current flows from the IIC bus to the source through the opened MOS transistor Q1, so that the voltage of the source of the MOS transistor Q1 continuously rises, and when the source voltage Vs rises to approach VDD-Vth, the on-resistance of the MOS transistor Q1 becomes large, and the current injected into the source decreases, so that the Vs rises and becomes slow. When VS is VDD-Vth, the VS voltage no longer rises. The voltage is the maximum voltage that the source of the MOS transistor Q1 can reach, and above this voltage, the MOS transistor Q1 is turned off because it does not satisfy the on condition.

During the turn-on process of the MOS transistor Q1, the source voltage Vs is always smaller than the gate voltage Vg. The positive conduction condition of the anti-static diode Vd is Vs-Vg > Vd; where Vd is the turn-on voltage drop of the diode Vd. Obviously, due to the existence of the MOS transistor Q1, this condition is not satisfied all the time, so that there is no situation that the diode Vd is turned on in the forward direction to pull down the voltage of the IIC bus 10, and the influence of the pull-up power source V0 on the IIC bus 10 through the MOS transistor Q1 when the MOS transistor Q1 is turned on is avoided.

In the present embodiment, the threshold voltage requirement of the MOS transistor Q1Satisfy V_th＜V_DDVS × 0.7, wherein V_thVg is the threshold voltage of MOS transistor Q1, and Vg is the power supply terminal V_DDVs is the operating voltage on IIC bus 10. When the operating voltage Vs on the IIC bus 10 is 3.3V, the voltage on the IIC bus 10 must be higher than 3.3 × 0.7 — 2.31V according to the IIC protocol requirement, and therefore Vth should satisfy V_th＜V_DD-2.31。

The IIC protocol requires a maximum transition time from 0 to 3.3V for the IIC signal, and the rise time for the actual IIC signal to transition from low to high must be less than the maximum rise time. Since the voltage at the IIC interface, i.e., the voltage on the source of the MOS transistor Q1, and the change of the voltage on the source of the MOS transistor Q1 is related to the threshold voltage of the MOS transistor Q1, the larger the threshold voltage is, the slower the change of the voltage on the source of the MOS transistor Q1 is. Therefore, this implementation sets that Vth should satisfy V_th＜V_DD2.31 to guarantee the signal rise time of IIC.

Further, the present embodiment also provides an isolation switch circuit 13 based on a high threshold voltage MOS transistor Q1. Referring to fig. 5, the isolating switch circuit 13 further includes a first resistor R1, two ends of the first resistor R1 are respectively connected to the power source terminal V_DDThe first terminal of the MOS transistor Q1 is connected to a power supply terminal VDD and a potential of the terminal of the MOS transistor Q1. The parasitic capacitance of the MOS transistor Q1 at the source is small, and the voltage of the MOS transistor Q1 at the source changes from high to low and from low to high only at a slow speed, in the order of microseconds, so that it can be considered that: vs ═ V_DD(ii) a There are two cases here, one is that when the display device is on standby, the power supply terminal V_DDThe upper voltage is 0, and the other is that the display device is operating normally, but the IIC device 11 does not need to transmit a signal to the IIC bus 10, and thus the 1/O port inside the IIC interface is open. Corresponding to the two cases, the Vs-Vg can be known according to the conduction condition of the MOS transistor Q1>Vth, and Vg ═ V_DDIt can be seen that Vg will always be in the off state. The MOS in the OFF state cuts off the pull-up power supply V0, the pull-up resistor R0, the anti-static diode Vd, and the power supply terminal V_DDThe formed loop ensures that the voltage on the IIC signal end is not influenced by the power-down of the IIC device 11.

When the IIC device 11 needs to send a signal to the IIC bus 10, the I/O port inside the IIC outputs a low level signal to pull down the source of the MOS transistor Q1, when Vg-Vs < Vth, the MOS transistor Q1 is turned on, the current on the IIC bus 10 flows into the I/O through the MOS transistor Q1, and when the voltage on the bus is pulled down, the IIC device 11 performs communication activities normally through the IIC bus 10.

In this embodiment, too small a value of the first resistor R1 may increase the pull-down current injected into the I/O of the IIC interface, so that when the IIC interface needs to communicate, the pull-up current cannot counteract the pull-down current, and the IIC interface cannot be pulled high; the excessive value of the first resistor R1 will cause the power source terminal V_DDThe source voltage difference from the MOS transistor is large, which causes the MOS transistor Q1 to be conducted by mistake. In this embodiment, the resistance of the first resistor R1 is set to be less than or equal to 40 ohms and greater than or equal to 20 ohms.

This implementation has reduced the requirement to MOS pipe Q1 threshold voltage for optional MOS pipe Q1 kind greatly increased, is favorable to reducing manufacturing cost.

In the embodiment, the isolation switch tube is arranged, and the controlled end of the isolation switch tube is connected with the power end V of the IIC device 11_DDConnected so that the isolation switch tube remains off when no signal is required from the IIC device 11. When the IIC device 11 needs to send a signal, the isolation switch tube is turned on under the action of the low level output by the IIC interface, so that the IIC device 11 can send the signal normally, and in the turning-on process of the isolation switch tube, the anti-static diode Vd in the IIC device 11 is forced not to be turned on in the forward direction, so that when the isolation switch tube is turned on, the pull-up power source V0 affects the IIC bus 10 through the MOS tube Q1. Therefore, the present embodiment reduces the influence of the operating state of the IIC device 11 on the IIC bus 10, and improves the reliability of the operation between the IIC bus 10 and each IIC device 11 in the display device.

The embodiment also provides an interface circuit of the IIC device 11, where the interface circuit of the IIC device 11 includes the IIC device 11 and an isolation switch circuit 13; the IIC device 11 has an IIC interface and a power supply terminal V_DD(ii) a The isolating switch circuit 13 comprises an isolating switch tube, and the controlled end of the isolating switch tube and the power end V are connected_DDConnection of the first and second disconnecting switch tubesOne end of the isolating switch tube is connected with the IIC interface, and the second end of the isolating switch tube is used for interconnecting the IIC bus and the pull-up circuit.

The IIC device 11 is the same as the explanation of the IIC device 11 in the above embodiment; i.e., all devices supporting the IIC protocol, may be referred to as IIC devices 11, such as EEPROM with IIC interface, DCDC, audio power amplifier, etc. For the specific embodiments of the IIC device 11 and the isolation switch circuit 13 in the interface circuit of the IIC device 11, please refer to the above embodiments, which are not described herein again.

In this embodiment, when the IIC device 11 is a chip, the isolation switch circuit 13 may be packaged inside a package of the IIC device 11, so that the packaged IIC device 11 has better isolation from the IIC, and the volume of the isolation switch circuit 13 can be reduced.

In this embodiment, the isolation switch tube is an MOS transistor Q1, and the gate of the isolation switch tube and the power supply terminal V are connected to each other_DDAnd the source electrode of the isolating switch tube is connected with the IIC interface, and the drain electrode of the isolating switch tube is connected with the IIC bus.

In this embodiment, the threshold voltage of the isolation switch tube satisfies V_th＜V_DD-V₀× 0.7.7, wherein V_thIs the threshold voltage, V, of the isolating switch tube_DDIs the power supply end V_DDSupply voltage of₀Is the operating voltage on the IIC bus 10.

In this embodiment, the isolating switch circuit 13 further includes a first resistor R1, and two ends of the first resistor R1 are respectively connected to the power source terminal V_DDAnd a first end of the isolation switch tube.

For the details of the above embodiments, please refer to related embodiments in the display device, which are not described herein again.

While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims (10)

1. A display device, comprising:

an IIC bus;

an IIC device having an IIC interface and a power supply terminal;

a pull-up circuit;

and the controlled end of the isolating switch circuit is connected with the power supply end, the first end of the isolating switch circuit is connected with the IIC interface, and the second end of the isolating switch circuit is interconnected with the IIC bus interface circuit and the pull-up circuit.

2. The display device according to claim 1, wherein the isolation switch circuit comprises an isolation switch tube.

3. The display device according to claim 1, wherein the isolation switch tube is an MOS tube, a gate of the isolation switch tube is connected to the power supply terminal, a source of the isolation switch tube is connected to the IIC interface, and a drain of the isolation switch tube is interconnected with the IIC bus and the pull-up circuit.

4. The display device according to claim 2, wherein the threshold voltage of the isolation switch tube satisfies V_th＜V_DD-V₀×0.7；

Wherein, V_thIs the threshold voltage, V, of the isolating switch tube_DDIs the supply voltage, V, on said supply terminal₀Is the operating voltage on the IIC bus.

5. The display device according to claim 2, wherein the isolating switch circuit further comprises a first resistor, and two ends of the first resistor are respectively connected to the power supply terminal and the first end of the isolating switch tube.

6. The display device according to claim 5, wherein the first resistor has a resistance value of 40 ohms or less and 20 ohms or more.

7. The display device according to claim 1, wherein the pull-up circuit comprises a pull-up power source and a pull-up resistor, one end of the pull-up resistor is connected with the pull-up power source, and the other end of the pull-up resistor is interconnected with the second end of the isolation switch tube and the IIC bus.

8. The display device according to claim 2, wherein the IIC bus comprises a clock line and a data line, and the isolation switch circuit comprises two isolation switch tubes for isolating the IIC interface from the clock line and isolating the IIC interface from the data line, respectively.

9. The display device of claim 1, wherein the IIC device is a CMOS process device.

10. An interface circuit for an IIC device, comprising:

the IIC interface is used for connecting the IIC device with the IIC bus;

the power supply end is used for supplying power to the IIC;

and the controlled end of the isolating switch circuit is connected with the power supply end, the first end of the isolating switch circuit is connected with the IIC interface, and the second end of the isolating switch circuit is interconnected with the IIC bus interface circuit and the pull-up circuit.

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