CN210835056U

CN210835056U - Parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection

Info

Publication number: CN210835056U
Application number: CN201921375550.6U
Authority: CN
Inventors: 马红星; 董诗阳; 唐厚君; 杨喜军; 谢伟新; 韩永馗; 方万; 孟祥群; 田威
Original assignee: Jiangsu Boda Nc Complete Equipment Co ltd
Current assignee: Jiangsu Boda Nc Complete Equipment Co ltd
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2020-06-23
Anticipated expiration: 2029-08-22

Abstract

The utility model relates to a parallelly connected IGBT time delay overcurrent protection circuit based on saturation voltage drop detects, its characterized in that: the IGBT power supply device comprises a PWM pulse main loop and a saturation voltage drop delay detection control circuit, wherein the PWM pulse main loop converts a control pulse sent by a control system into a PWM driving pulse with driving capability to drive the IGBT to be switched on and switched off; the AND gates U1 and U3 process the overcurrent fault signal generated by the saturated voltage drop delay detection control circuit, and when the overcurrent fault signal is at a high level, the logic of the PWM pulse main loop is unchanged; when the overcurrent fault signal is at a low level, no matter the control pulse is at a high level or a low level, the outputs of the AND gates U1 and U3 are at a low level, and the IGBT drive pulse is at a low level, so that the overcurrent protection of the IGBT is realized. The utility model discloses in carry out time delay to IGBT saturation pressure drop and detect, the unstable mistake protection that causes of saturation pressure drop when avoiding IGBT to open has improved the rationality and the reliability of circuit.

Description

Parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection

Technical Field

The utility model relates to a IGBT time delay overcurrent protection circuit especially relates to a parallelly connected IGBT time delay overcurrent protection circuit based on saturation voltage drop detects. Belongs to the technical field of power electronics.

Background

A conventional overcurrent protection circuit is a typical IGBT parallel application circuit as shown in fig. 1: the drains and sources of 2 IGBT modules (IGBT1 and IGBT2) are connected together, respectively; the grid electrode is connected with the PWM pulse driving circuit, and R1 and R3 are gate electrode driving resistors and play a role in limiting current; d1 and D2 are voltage-stabilizing tubes to prevent overvoltage of driving pulse voltage; r2 and R4 are gate-to-ground resistances, and prevent false triggering due to high-frequency interference.

Introduction of the traditional IGBT overcurrent protection principle:

as shown in fig. 1, when the PWM driving pulse is at a high level, the IGBT is turned on, and a current flows through the IGBT, and the voltage between the drain and the source of the IGBT is low, about 0 to 5V. The voltage is called saturation voltage drop, and the magnitude of the saturation voltage drop is in direct proportion to the current flowing through the IGBT, namely the larger the current is, the larger the saturation voltage drop of the IGBT is. Therefore, by utilizing the rule, a hardware circuit can be designed to detect the saturation voltage drop of the IGBT, and when the saturation voltage drop is larger than a certain set value (the saturation voltage drop value corresponding to the overcurrent protection threshold), the PWM driving pulse is turned off, and the IGBT is turned off, so that the module is prevented from being burnt out by large current. This is the principle of overcurrent protection typically achieved by detecting a saturated voltage drop.

However, in practical applications, when the PWM driving pulse changes from low level to high level, the IGBT is turned on and the current flows, but the saturation voltage drop does not immediately decrease to an ideal value, and often needs to be stabilized by a short oscillation. A typical waveform is shown in fig. 2. In the figure, the time from t1 to t2 is related to factors such as the manufacturer, model and service time of the module, and the value is about 3-5 us.

The traditional IGBT overcurrent protection circuit has the following defects:

1. according to the traditional scheme, when the PWM driving pulse is changed from a low level to a high level, the saturation voltage drop is immediately detected, and overcurrent protection is carried out according to a detection value. However, since the IGBT saturation voltage drop is not stable for the time t1 to t2, the protection is likely to be mistakenly performed.

2. Traditional parallelly connected IGBT current foldback circuit is mostly two into one two independent protection circuit unites, and circuit structure is redundant, and components and parts are in large quantity, the analysis and the maintenance of being not convenient for.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a circuit structure is simple is provided to above-mentioned prior art, and components and parts are small in quantity, the parallel connection IGBT time delay overcurrent protection circuit based on saturation voltage drop detection of being convenient for design and maintenance.

The utility model relates to a solve the technical scheme who adopts of above-mentioned problem and do: a parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection comprises a PWM pulse main loop and a saturation voltage drop time-delay detection control circuit.

The PWM pulse main loop converts control pulses sent by a control system into PWM driving pulses with driving capability, and drives the IGBT to be switched on and switched off. The AND gates U1 and U3 process the overcurrent fault signal generated by the saturated voltage drop delay detection control circuit, and when the overcurrent fault signal is at a high level, the logic of the PWM pulse main loop is unchanged; when the overcurrent fault signal is at a low level, no matter the control pulse is at a high level or a low level, the outputs of the AND gates U1 and U3 are at a low level, and the IGBT drive pulse is at a low level, so that the overcurrent protection of the IGBT is realized.

Preferably, the input of the saturation voltage drop delay detection control circuit is IGBT drain-source voltage drop and control pulse, and the output is an overcurrent fault signal, and the saturation voltage drop delay detection control circuit includes: the IGBT power supply comprises an overcurrent signal generating circuit which takes the voltage drop of a drain source electrode of the IGBT as input to generate an overcurrent signal, two control pulse delay circuits and a fault comprehensive processing circuit which is formed by combining the delayed control pulse and the overcurrent fault signal.

Preferably, the overcurrent signal generating circuit takes saturation voltage drop between the drain and the source of the IGBT as input, and is connected to the positive electrode of the comparator U5 after passing through an RC filter circuit composed of a resistor R1 and a capacitor C1, while the overcurrent reference voltage Vref1 is connected to the negative electrode of the comparator U5, and the overcurrent signal output by the comparator U5 is taken as input of the fault comprehensive processing circuit.

Preferably, a fast recovery diode D1 is arranged between the IGBT drain and the RC filter circuit to prevent a strong electric current from flowing back to the control system, and an offset compensation resistor is arranged between the output end of the RC filter circuit and the positive electrode of the comparator to realize impedance matching of the positive and negative input electrodes of the comparator.

Preferably, the two control pulse delay circuits are respectively used for delaying the

control pulses

1 and 2, and each control pulse delay circuit comprises a first nand gate, an RC charge and discharge circuit, a comparator, a second nand gate, a first reverse schmitt trigger and a second reverse schmitt trigger, output voltage of an overcurrent fault signal fed back by the control pulse and the fault comprehensive processing circuit after passing through the first nand gate is divided into two paths, one path of the output voltage is connected to the input end of the second nand gate after passing through the reverse schmitt trigger, the other path of the output voltage is connected to the positive electrode of the comparator after passing through the RC charge and discharge circuit, and is compared with a delay reference voltage Vref2 connected to the negative electrode of the comparator, the adjustment of the control pulse delay time can be realized through an RC parameter, the output end of the comparator is connected to the input end of the second nand gate, the output end of the second nand gate is connected to the input end of the second reverse, and the output voltage of the second reverse Schmitt trigger is connected to the fault comprehensive processing circuit.

Preferably, the RC charging and discharging circuit includes a MOSFET transistor, a charging and discharging resistor, and a charging and discharging capacitor, the gate of the MOSFET transistor is connected to the output end of the first nand gate, the source is grounded, the drain is connected to the power supply through the charging and discharging resistor, two ends of the charging and discharging capacitor are connected to the source and the drain of the MOSFET transistor, respectively, and the output of the RC charging and discharging circuit is connected to the anode of the comparator after passing through the current limiting resistor.

Preferably, the fault synthesis processing circuit comprises a nand gate, and the inputs of the nand gate are output signals of the overcurrent signal generating circuit and the control pulse delay circuit. When the output of the over-current signal generating circuit is at a high level and the output of the control pulse delay circuit is at a low level, the over-current fault signal is at a high level, and the circuit has no fault; otherwise, the output of the over-current signal production circuit is at a high level and the control pulse delay output is at a high level, and the over-current fault signal is at a low level, so that the circuit has a fault.

Preferably, the output of the nand gate in the fault comprehensive processing circuit is connected with a delay circuit, the delay circuit delays the overcurrent fault signal to provide sufficient time for the main control circuit to process the overcurrent fault, and the delay time is generally in the order of ms.

Compared with the prior art, the utility model has the advantages of:

1. the utility model discloses well two way IGBT overcurrent protection electric currents adopt same signal generation circuit that overflows, have simplified circuit design.

2. The utility model discloses in carry out time delay to IGBT saturation pressure drop and detect, the unstable mistake protection that causes of saturation pressure drop when avoiding IGBT to open has improved the rationality and the reliability of circuit.

Drawings

Fig. 1 is a circuit diagram of a typical prior art parallel IGBT application.

Fig. 2 is a graph of the relationship between the PWM driving pulse and the IGBT saturation voltage drop.

Fig. 3 is a schematic diagram of the PWM pulse main loop according to the embodiment of the present invention.

Fig. 4 is the embodiment of the present invention, a schematic diagram of a saturation voltage drop delay detection control circuit.

Fig. 5 is a timing diagram of the control pulse delay circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the following embodiments.

As shown in fig. 3 to 4, the parallel IGBT delay overcurrent protection circuit based on saturation drop detection in this embodiment includes a PWM pulse main loop and a saturation drop delay detection control circuit.

The PWM pulse main loop

converts control pulses

1 and 2 sent by a control system (a single chip microcomputer or DSP and the like) into

PWM driving pulses

1 and 2 with driving capability to drive the IGBT to be switched on and switched off. Meanwhile, the and gates U1 and U3 can process the

overcurrent fault signals

1 and 2, and when the signals are high level (i.e. no overcurrent fault), the logic of the PWM pulse main loop is not changed; when the signal is at a low level (that is, an overcurrent fault exists), no matter the

control pulses

1 and 2 are at a high level or a low level, the outputs of the and gates U1 and U3 are at a low level, and the

IGBT driving pulses

1 and 2 are at a low level, so that the overcurrent protection of the IGBT is realized.

The

overcurrent fault signals

1 and 2 are generated by a saturation voltage drop delay detection control circuit, the input of the saturation voltage drop delay detection control circuit is IGBT drain-source voltage drop and

control pulses

1 and 2, the output is

overcurrent fault signals

1 and 2. the saturation voltage drop delay detection control circuit comprises 4 parts in total, ① is an overcurrent signal generating circuit, ② and ③ are

control pulse

1 and 2 delay circuits, ④ is a fault comprehensive processing circuit, and each part of the circuit is explained in detail in the following:

① overcurrent signal generating circuit:

the input of the circuit is IGBT drain-source voltage drop, the output is overcurrent signal (high level is effective), wherein D1 is a fast recovery diode, and the control system can prevent heavy current from flowing backwards; r1 and C1 form an RC filter circuit for filtering the collected saturated voltage drop; r3 and R4 are pull-up resistors, U5 is a comparator, and R2 is an offset compensation resistor, so that impedance matching of the positive and negative input electrodes of the comparator is realized. The overcurrent reference voltage Vref1 is a saturation voltage drop value corresponding to the overcurrent protection threshold, and the value is determined according to a current and saturation voltage drop curve of the selected IGBT model. Specifically, when the current is lower than the overcurrent protection threshold, the IGBT saturation voltage drop is lower than the overcurrent reference voltage Vref1, and the output voltage of the comparator U5 is low, otherwise it is high. I.e., the output of U5 is high, indicating that an overcurrent fault has occurred.

② and ③

control pulse

1 and 2 delay circuits:

u6, U9, U11 and U14 are NAND gates, T1 and T2 are MOSFETs, R5 and R8 are RC charge-discharge resistors, C2 and C3 are RC charge-discharge capacitors, and T1, R5 and C2 respectively form 2 RC charge-discharge circuits with T2, R8 and C3; r6 and R9 are current-limiting resistors, U7 and U12 are comparators, R7 and R10 are pull-up resistors, and U8, U10, U13 and U15 are reverse Schmitt triggers.

The function of the circuit is to delay the

control pulses

1 and 2, the delay time is set to 6 us., the principle of the circuit is the same as that of fig. ② and ③, only the principle of fig. ② is taken as an example to explain the circuit, the overcurrent fault signal 1 is assumed to be high level, namely, no overcurrent fault exists, when the control pulse 1 is converted from low level to high level, the output of the nand gate U6 is low level, the mosfet T1 is turned off, the power supply VCC charges the capacitor C2 through the resistor R5, when the charging voltage of C2 is lower than the delay reference voltage Vref2, the comparator U7 is low level, when the charging voltage is higher than the reference voltage, the comparator is converted to high level, the delay time of the control pulse 1 can be accurate to about 6us by reasonably setting the values of the resistor R5, the capacitor C2 and the delay reference voltage Vref2, as shown in fig. 5, the output of U7 is a waveform, the inverse Schmitt trigger U8 reversely recovers the output of the NAND gate U6, as a combined waveform of a combined signal U8 and a U465 output waveform as a combined logic 465;

④ fault comprehensive processing circuit

From the above analysis, when an overcurrent fault occurs, the circuit ① outputs a high level, the

circuits

② and ③ output square waves after delaying the

control pulses

1 and 2 by 6us, the circuit ④ functions to perform nand logic operation on the two signals, and has the effects that the overcurrent fault is not processed within the delay time because the circuit ① outputs a high level and the

circuits

② and ③ output a low level within 6us of the delay time (t 1-t 2), when the delay time is over, because the circuit ① outputs a high level and the

circuits

② and ③ output a high level, the

overcurrent fault signals

1 and 2 are both low levels, namely, the circuit has a fault, the overcurrent fault is processed after the delay time is over, in addition, the overcurrent fault signal is output before the time is delayed, the delay is used for processing the overcurrent fault to the main control circuit, the time is generally in ms level, can be set to be about 1.5, but the overcurrent fault signal is processed after the delay time is changed from the high level, the delay time is changed into the delay time of the high level, and the delay time of the circuit is changed into the delay time of the control pulses 1.5ms, and the delay time of the main circuit is controlled by adopting the delay time of the other circuits, and the delay time of the circuit is controlled by adopting the other circuits, and the delay time of the delay time.

Introduction of overcurrent fault signal logic (taking overcurrent fault signal 1 as an example):

the signal is generated by the control pulse delay circuit ② and the fault comprehensive processing circuit ④, when there is no overcurrent fault, the signal is at high level, at this time, the signal does not affect the normal logic of the PWM driving pulse main loop, when there is overcurrent fault, the signal is at low level, at this time, the PWM driving pulse main loop is forced to be locked at low level, no matter "control pulse 1" is at high level or low level (U1 is an and gate, when overcurrent fault signal 1 is at low level, its output must be at low level), in addition, the input of nand gate U6 also introduces the feedback of overcurrent fault signal 1, in order to disable the control pulse delay circuit ② during overcurrent fault (overcurrent fault signal 1 is at low level), because one input of U6 is at low level, its output is always at high level.

In addition to the above embodiments, the present invention also includes other embodiments, and all technical solutions formed by equivalent transformation or equivalent replacement should fall within the protection scope of the claims of the present invention.

Claims

1. The utility model provides a parallelly connected IGBT time delay overcurrent protection circuit based on saturation voltage drop detects which characterized in that: the IGBT power supply device comprises a PWM pulse main loop and a saturation voltage drop delay detection control circuit, wherein the PWM pulse main loop converts a control pulse sent by a control system into a PWM driving pulse with driving capability to drive the IGBT to be switched on and switched off; the AND gates U1 and U3 process the overcurrent fault signal generated by the saturated voltage drop delay detection control circuit, and when the overcurrent fault signal is at a high level, the logic of the PWM pulse main loop is unchanged; when the overcurrent fault signal is at a low level, no matter the control pulse is at a high level or a low level, the outputs of the AND gates U1 and U3 are at a low level, and the IGBT drive pulse is at a low level, so that the overcurrent protection of the IGBT is realized.

2. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 1, wherein: the input of the saturation voltage drop time delay detection control circuit is IGBT drain source electrode voltage drop, control pulse, the output is overcurrent fault signal, the saturation voltage drop time delay detection control circuit includes: the IGBT power supply comprises an overcurrent signal generating circuit which takes the voltage drop of a drain source electrode of the IGBT as input to generate an overcurrent signal, two control pulse delay circuits and a fault comprehensive processing circuit which is formed by combining the delayed control pulse and the overcurrent fault signal.

3. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 2, wherein: the overcurrent signal generating circuit takes saturation voltage drop between the drain and the source of the IGBT as input, the saturation voltage drop passes through an RC filter circuit consisting of a resistor R1 and a capacitor C1 and then is connected to the positive pole of a comparator U5, an overcurrent reference voltage Vref1 is connected to the negative pole of the comparator U5, and an overcurrent signal output by the comparator U5 serves as input of a fault comprehensive processing circuit.

4. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 3, wherein: a fast recovery diode is arranged between the IGBT drain electrode and the RC filter circuit to prevent a strong current from flowing back to the control system, and an offset compensation resistor is arranged between the output end of the RC filter circuit and the positive electrode of the comparator to realize impedance matching of the positive and negative input electrodes of the comparator.

5. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 2, wherein: the two control pulse delay circuits are respectively used for delaying control pulses 1 and 2 and respectively comprise a first NAND gate, an RC charge-discharge circuit, a comparator, a second NAND gate, a first reverse Schmitt trigger and a second reverse Schmitt trigger, the output voltage of an overcurrent fault signal fed back by the control pulse and fault comprehensive processing circuit after passing through the first NAND gate is divided into two paths, one path of the output voltage is connected to the input end of the second NAND gate after being reversely recovered by the reverse Schmitt trigger, the other path of the output voltage is connected to the anode of the comparator after passing through the RC charge-discharge circuit and is compared with a delay reference voltage Vref2 connected to the cathode of the comparator, the adjustment of the delay time of the control pulse can be realized through RC parameters, the output end of the comparator is connected to the input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the second reverse Schmitt trigger, and the output voltage of the second reverse Schmitt trigger is connected to the fault comprehensive processing circuit.

6. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 5, wherein: the RC charge-discharge circuit comprises an MOSFET transistor, a charge-discharge resistor and a charge-discharge capacitor, the grid of the MOSFET transistor is connected with the output end of the first NAND gate, the source electrode of the MOSFET transistor is grounded, the drain electrode of the MOSFET transistor is connected with the power supply through the charge-discharge resistor, the two ends of the charge-discharge capacitor are respectively connected with the source electrode and the drain electrode of the MOSFET transistor, and the output of the RC charge-discharge circuit is connected with the anode of the comparator after passing through the current-.

7. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 2, wherein: the fault comprehensive processing circuit comprises a NAND gate, the input of the NAND gate is output signals of an overcurrent signal generating circuit and a control pulse delay circuit, and when the output of the overcurrent signal generating circuit is high level and the output of the control pulse delay circuit is low level, an overcurrent fault signal is high level, the circuit has no fault; otherwise, the output of the over-current signal production circuit is at a high level and the control pulse delay output is at a high level, and the over-current fault signal is at a low level, so that the circuit has a fault.

8. The parallel IGBT time-delay overcurrent protection circuit based on saturation voltage drop detection of claim 5, wherein: the output of the NAND gate in the fault comprehensive processing circuit is connected with a delay circuit, the delay circuit delays the overcurrent fault signal to provide sufficient time for the main control circuit to process the overcurrent fault, and the delay time is in the order of ms.