CN210697666U

CN210697666U - Data acquisition processing system based on serial output detector module

Info

Publication number: CN210697666U
Application number: CN201920784990.0U
Authority: CN
Inventors: 朱炯; 王武斌; 陈修儒; 李敏; 方泽莉; 黄振强
Original assignee: FMI Technologies Inc
Current assignee: Minfound Medical Systems Co Ltd; FMI Technologies Inc
Priority date: 2019-05-29
Filing date: 2019-05-29
Publication date: 2020-06-09
Anticipated expiration: 2029-05-29

Abstract

The utility model provides a data acquisition processing system based on serial output detector module relates to CT detector technical field, include the detector base plate and place the detector module subassembly on the detector base plate, the detector module subassembly comprises a plurality of detector modules, its characterized in that: each detector module comprises a PD scintillator, an AD chip and an FPGA; the AD chip is connected with the FPGA, the AD chip is used for converting analog signals into digital signals and then sending the digital signals to the FPGA, and the FPGA processes the data and then sends the digital signals to a previous detector module and receives the data of a next detector module at the same time. The utility model discloses data acquisition and data processing make detector module simple structure at same module. Meanwhile, the FPGA code amount of the detector module is greatly reduced.

Description

Data acquisition processing system based on serial output detector module

Technical Field

The utility model relates to a CT detector technical field, in particular to data acquisition processing system based on serial output detector module.

Background

The detector is a core component in the CT system, and the correct output data of the detector module is crucial to the quality of the image. The reliability, stability, real-time performance of the data acquisition and transmission system and the accuracy of the acquired data directly affect the quality of the reconstructed image. Designing a stable and reliable detector module is therefore of paramount importance for CT systems. The detector module through serial output has simple structure and stable and rapid transmission speed, and can meet the requirement of image to data.

The detector module structure with serial output in the prior art has the following defects:

1. data after AD conversion of the existing 16-row CT detector is processed in a backboard in a centralized way, and the configuration of an AD chip is controlled by the backboard, so that FPGA codes are complex;

2. the existing data acquisition and data processing of the 16-row CT detector are processed on different PCBs (printed circuit boards), namely the data of the 16-row CT detector is firstly acquired on an AD (analog-digital) board and then the acquired data is sent to a back board for sequencing and other series of processing, the data arrangement dislocation can be caused in the process, and the number of the PCBs in the detector is increased by connecting the detector together through the back board, so that the structure of the detector is complex, and the fault points of the detector are increased.

Based on this, the present case has been made.

SUMMERY OF THE UTILITY MODEL

In order to solve the above-mentioned defect that exists among the prior art, the utility model provides a data acquisition processing system based on serial output detector module.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a data acquisition processing system based on serial output detector modules comprises a detector substrate and a detector module assembly placed on the detector substrate, wherein the detector module assembly consists of a plurality of detector modules, and each detector module comprises a PD scintillator, an AD chip and an FPGA; the AD chip is connected with the FPGA, the AD chip is used for converting analog signals into digital signals and then sending the digital signals to the FPGA, and the FPGA processes the data and then sends the digital signals to a previous detector module and receives the data of a next detector module at the same time.

Preferably, each of the detector modules is further provided with two connectors for transmitting and receiving data information, respectively.

The utility model discloses a theory of operation: the detector module receives rays from the PD scintillator and converts the rays into dark current, the dark current is input into the AD chip and converted into digital signals to be sent to the FPGA, the FPGA recombines the acquired data according to corresponding sequencing, the data are sent to the previous module from the first connector after the sequencing is completed, and the data of the previous module are received from the second connector, namely, one connector is a sending end, and the other connector is a receiving end.

The utility model discloses can realize following technological effect:

(1) the utility model discloses data acquisition and data processing make detector module simple structure at same module.

(2) The utility model discloses detector module FPGA code volume significantly reduces.

Drawings

FIG. 1 is a diagram of a detector module distribution according to the present invention;

fig. 2 is a schematic structural diagram of the detector module of the present invention;

fig. 3 is a schematic diagram of data transmission of the detector module according to the present invention.

Description of the labeling: PD scintillator 1, detector module assembly 2, detector AD board 3, PD scintillator 11,

AD chips

12, 13, 14, 15, FPGA 16,

connectors

17, 18, power interface 19.

Detailed Description

In order to make the technical means and the technical effects achieved by the technical means of the present invention clearer and more complete, the following embodiments are provided and are described in detail with reference to the accompanying drawings as follows:

as shown in fig. 1, a detector module assembly 2 is placed on a detector substrate 1, a detector AD board 3 is installed in the detector module assembly 2, and the number of modules can be reduced after adding according to the requirements.

As shown in fig. 2 and fig. 3, each detector module mainly includes a PD scintillator 11, four

AD chips

12, 13, 14, and 15, an FPGA 16, two

connectors

17 and 18, and a power interface 19. The detector module receives rays from the PD scintillator 11 and converts the rays into dark current, the dark current is input into the AD chip and converted into digital signals to be sent to the FPGA 16, the FPGA 16 recombines the acquired data according to corresponding sequencing, and the data are packaged and sent to the previous module from the connector 17 after the sequencing is finished and the data of the previous module are received from the connector 18; the FPGA code of each module in the whole detector is completely consistent. And gradually sending the data acquired once to the DCB board for processing through a pipeline mode. The interface 19 (power interface 19) is an external power input that provides power to the detector module.

The above is a detailed description of the technical solutions provided in connection with the preferred embodiments of the present invention, and it should not be assumed that the embodiments of the present invention are limited to the above description, and it will be apparent to those skilled in the art that the present invention can be implemented in a variety of ways without departing from the spirit and scope of the present invention.

Claims

1. The utility model provides a data acquisition processing system based on serial output detector module, includes detector base plate and places the detector module subassembly on the detector base plate, the detector module subassembly comprises a plurality of detector modules, its characterized in that: each detector module comprises a PD scintillator, an AD chip and an FPGA; the AD chip is connected with the FPGA, the AD chip is used for converting analog signals into digital signals and then sending the digital signals to the FPGA, and the FPGA processes the data and then sends the digital signals to a previous detector module and receives the data of a next detector module at the same time.

2. The data acquisition and processing system based on the serial output detector module as claimed in claim 1, wherein: each detector module is also provided with two connectors which are respectively used for sending and receiving data information.