CN211123672U

CN211123672U - 10-channel FMC-ADC daughter card

Info

Publication number: CN211123672U
Application number: CN201921623945.3U
Authority: CN
Inventors: 盖武; 盖昱升
Original assignee: Chengdu Ruinaibo Technology Co ltd
Current assignee: Chengdu Ruinaibo Technology Co ltd
Priority date: 2019-09-26
Filing date: 2019-09-26
Publication date: 2020-07-28
Anticipated expiration: 2029-09-26

Abstract

The utility model discloses a 10 passageway FMC-ADC daughter cards adopts 5 binary channels ADC chips to establish 10 signal acquisition of passageway, comes centralized control by the control communication bus who is connected with the FMC connector, guarantees sampling frequency and input gain and stably keeps at the high requirement level to but the free choice 2, 4, 6, 8 crossover passage. 5 clock signals and a synchronous clock signal to the FMC carrier plate are output by 1 sampling clock chip, then the synchronous clock signal of the FMC carrier plate is output to 5 double-channel ADC chips by one synchronous clock chip, impedance matching with analog signal input is carried out by 1 sampling clock chip, and the clock chips are used as few as possible, so that interference of a clock signal circuit device to an analog signal input high-frequency circuit is reduced. This is novel more in passageway quantity, has still guaranteed the good performance of daughter card under the condition under the high-speed requirement of acquisition rate still keeping.

Description

10-channel FMC-ADC daughter card

Technical Field

The utility model belongs to the technical field of signal acquisition, concretely relates to 10 passageway FMC-ADC daughter cards.

Background

The FMC-ADC daughter card is of an FMC daughter card structure and is mounted on the signal processing carrier plate through an FMC interface, and the signal acquisition function is completed. The ADC card generally employs an ADC chip for signal acquisition. The existing FMC-ADC daughter card is powered through an FMC connector and generally supports 2, 4, 6 and 8 channels. Under the condition that some signal acquisition requirements are higher, the number of channels needs to be more, the acquisition rate still needs to be kept high, and after the channels are increased, due to the matching difficulty of a plurality of channel clock signals and the fact that a plurality of clock signal circuit devices of the channels easily interfere with the signals of an acquisition signal high-frequency circuit, the high-speed FMC-ADC daughter card with excellent multi-channel performance is difficult to realize.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a: the problem that when channels are increased, due to the matching difficulty of a plurality of channel clock signals and the fact that a plurality of clock signal circuit devices of the channels are prone to causing interference on collected signal high-frequency circuit signals, multi-channel performance and high speed are difficult to achieve under the condition that the requirements for signal collection of the FMC-ADC signal collecting daughter card are higher is solved, and the 10-channel FMC-ADC daughter card is provided.

The utility model adopts the technical scheme as follows:

a10-channel FMC-ADC daughter card comprises an FMC connector connected with an FMC carrier plate, and further comprises 5 double-channel ADC chips correspondingly connected with the input end of a signal end of the FMC connector, wherein the signal acquisition ends of the 5 double-channel ADC chips are connected with an analog signal input circuit, the 5 double-channel ADC chips are connected through a control communication bus, the control communication bus is further connected to the FMC connector, and FMC frequency and gain control signals are transmitted to the 5 double-channel ADC chips through the FMC connector;

the sampling clock chip module comprises 1 sampling clock chip, the sampling clock chip outputs 5 clock signals to 5 sampling clock signal circuits of 5 double-channel ADC chips, the sampling clock chip also outputs a synchronous clock signal, and the synchronous clock signal is output to the FMC carrier plate by connecting an FMC connector; the synchronous clock chip is connected with the FMC connector and used for receiving synchronous clock signals of the FMC carrier plate, the signal output end of the synchronous clock chip is connected with the 5 double-channel ADC chips, and the synchronous clock signals of the FMC carrier plate are output to the 5 double-channel ADC chips.

Further, the two-channel ADC chip adopts an ADS 42L B69 chip.

Further, the sampling clock chips of the synchronous clock chip and the sampling clock chip module adopt ADC L K946 BCPZ.

Furthermore, board-level local shielding or ground wire isolation is adopted between the sampling clock chip module and 2 modules of the synchronous clock chip and the high-frequency circuit.

Furthermore, the analog signal input circuit adopts a signal input circuit formed by 2 broadband transformers connected in series.

Furthermore, the analog signal input circuit is connected with an input analog signal through an SSMC coaxial connector, and the sampling clock chip module is connected with an input external clock signal through the SSMC coaxial connector.

To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:

1. the utility model discloses in, adopt 5 binary channels ADC chips to construct the signal acquisition of 10 passageways, come centralized control by the control communication bus who is connected with the FMC connector, guarantee sampling frequency and input gain and stably keep at the high requirement level to but the

free choice

2, 4, 6, 8 crossover passage. 5 clock signals and a synchronous clock signal to the FMC carrier plate are output by 1 sampling clock chip, then the synchronous clock signal of the FMC carrier plate is output to 5 double-channel ADC chips by one synchronous clock chip, impedance matching with analog signal input is carried out by 1 sampling clock chip, and the clock chips are used as few as possible, so that interference of a clock signal circuit device to an analog signal input high-frequency circuit is reduced. This is novel more in passageway quantity, has still guaranteed the good performance of daughter card under the condition under the high-speed requirement of acquisition rate still keeping.

2. The utility model discloses in, adopt the local shielding or the ground wire of board level to keep apart between 2 modules of sampling clock chip module and synchronous clock chip and the high frequency circuit, further reduce the interference of clock signal circuit device to analog signal input high frequency circuit.

3. The utility model discloses in, the analog signal input circuit can be simplified to the signal input circuit that the broadband transformer that adopts 2 series connections constitutes to integrated broadband transformer can be stronger than pure component circuit interference immunity.

4. The utility model discloses in, analog signal input circuit passes through SSMC coaxial connector and connects the analog signal of input, and the external clock signal of input is connected through SSMC coaxial connector to sampling clock chip module, has strengthened the isolation of signal between each passageway.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is an overall architecture diagram of the FMC-ADC daughter card of the present invention;

FIG. 2 is a schematic circuit diagram of the ADS 42L B69 chip of the present invention;

fig. 3 is a schematic circuit diagram of the sampling clock chip module according to the present invention;

FIG. 4 is a schematic circuit diagram of the synchronous clock chip of the present invention;

FIG. 5 is a schematic diagram of the FMC connector of the present invention connected to a power module;

fig. 6 is the circuit connection schematic diagram of the FMC connector and 5 binary channels ADC chips, sampling clock chip module and synchronous clock chip of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention, i.e., the described embodiments are merely some, but not all, embodiments of the invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.

It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The features and properties of the present invention are described in further detail below with reference to examples.

Example 1

The utility model discloses a 10 passageway FMC-ADC daughter cards that preferred embodiment provided, as shown in FIG. 1, include the FMC connector of being connected with FMC carrier plate, still include the 5 binary channels ADC chips of being connected with FMC connector signal end input correspondence, 5 binary channels ADC chip signal acquisition end connection analog signal input circuit, connect through control communication bus between the 5 binary channels ADC chips, control communication bus still is connected to the FMC connector, FMC's frequency and gain control signal transmit to 5 binary channels ADC chips through the FMC connector;

In this embodiment, the dual-channel ADC chip employs an ADS 42L B69 chip, a circuit diagram of one ADS 42L B69 chip is shown in fig. 2, circuit diagrams of other 4 ADS 42L B69 chips are the same as those of the other chips, and corresponding data signal terminals of 5 chips are numbered according to 1-5.

Further, in the present embodiment, the analog signal input circuit employs a signal input circuit composed of 2 series-connected wideband transformers, as shown in fig. 2, the signal input circuit composed of 2 series-connected wideband transformers can simplify the analog signal input circuit, and the integrated wideband transformer can be more interference-resistant than a pure element circuit, in the present embodiment, the wideband transformer employs WBC1-1T L.

In this embodiment, the sampling clock chips of the synchronous clock chip and the sampling clock chip module adopt ADC L k946bcpz, a circuit schematic diagram of the sampling clock chip module is shown in fig. 3, and a circuit schematic diagram of the synchronous clock chip is shown in fig. 4.

Further, in this embodiment, the analog signal input circuit is connected to the input analog signal through the SSMC coaxial connector, and the sampling clock chip module is connected to the input external clock signal through the SSMC coaxial connector. The use of the SSMC coaxial connectors enhances the isolation of signals between the channels.

In this embodiment, the FMC connector is connected to the power module to supply power to the FMC-ADC daughter card, and a schematic circuit diagram is shown in fig. 5. The schematic diagram of the FMC connector connected to the 5 dual-channel ADC chips, the sampling clock chip module and the synchronous clock chip is shown in fig. 6.

The utility model discloses in, adopt 5 binary channels ADC chips to construct the signal acquisition of 10 passageways, come centralized control by the control communication bus who is connected with the FMC connector, guarantee sampling frequency and input gain and stably keep at the high requirement level to but the

free choice

Example 2

The utility model discloses preferred embodiment is on embodiment 1's basis, adopt local shielding or ground wire isolation of board level between 2 modules of sampling clock chip module and synchronous clock chip and the high frequency circuit, further reduce the interference of clock signal circuit device to analog signal input high frequency circuit.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. The utility model provides a 10 passageway FMC-ADC daughter cards, includes the FMC connector of being connected with the FMC support plate which characterized in that: the FMC frequency and gain control signal transmission device further comprises 5 double-channel ADC chips correspondingly connected with the input end of the signal end of the FMC connector, the signal acquisition ends of the 5 double-channel ADC chips are connected with the analog signal input circuit, the 5 double-channel ADC chips are connected through a control communication bus, the control communication bus is further connected to the FMC connector, and the FMC frequency and gain control signal is transmitted to the 5 double-channel ADC chips through the FMC connector;

2. The 10-channel FMC-ADC daughter card of claim 1 wherein said dual-channel ADC chip is an ADS 42L B69 chip.

3. The 10-channel FMC-ADC daughter card of claim 1 wherein the sampling clock chips of said synchronous clock chip and sampling clock chip modules are ADC L K946 BCPZ.

4. The 10-channel FMC-ADC daughter card of claim 1, wherein: and the sampling clock chip module and 2 synchronous clock chip modules are isolated from the high-frequency circuit by adopting plate-level local shielding or ground wire.

5. The 10-channel FMC-ADC daughter card of claim 1, wherein: the analog signal input circuit adopts a signal input circuit formed by 2 broadband transformers connected in series.

6. The 10-channel FMC-ADC daughter card of claim 1, wherein: the analog signal input circuit is connected with an input analog signal through the SSMC coaxial connector, and the sampling clock chip module is connected with an input external clock signal through the SSMC coaxial connector.